32 #define TRACE_LEVEL NIC_TRACE_LEVEL
44 #if defined(__ICCARM__)
47 #pragma data_alignment = 4
50 #pragma data_alignment = 4
53 #pragma data_alignment = 4
56 #pragma data_alignment = 4
119 TRACE_INFO(
"Initializing GD32F307 Ethernet MAC...\r\n");
122 nicDriverInterface = interface;
128 rcu_periph_clock_enable(RCU_ENET);
129 rcu_periph_clock_enable(RCU_ENETTX);
130 rcu_periph_clock_enable(RCU_ENETRX);
133 rcu_periph_reset_enable(RCU_ENETRST);
134 rcu_periph_reset_disable(RCU_ENETRST);
137 ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR;
139 while((ENET_DMA_BCTL & ENET_DMA_BCTL_SWR) != 0)
144 ENET_MAC_PHY_CTL = ENET_MDC_HCLK_DIV62;
147 if(interface->phyDriver != NULL)
150 error = interface->phyDriver->init(interface);
152 else if(interface->switchDriver != NULL)
155 error = interface->switchDriver->init(interface);
170 ENET_MAC_CFG = ENET_MAC_CFG_ROD;
173 ENET_MAC_ADDR0L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
174 ENET_MAC_ADDR0H = interface->macAddr.w[2] | ENET_MAC_ADDR0H_MO;
189 ENET_MAC_FRMF = ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_HMF;
193 ENET_DMA_CTL = ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD;
196 ENET_DMA_BCTL = ENET_DMA_BCTL_AA | ENET_DMA_BCTL_UIP | ENET_RXDP_1BEAT |
197 ENET_ARBITRATION_RXTX_1_1 | ENET_PGBL_1BEAT | ENET_DMA_BCTL_DFM;
204 ENET_MSC_TINTMSK = ENET_MSC_TINTMSK_TGFIM | ENET_MSC_TINTMSK_TGFMSCIM |
205 ENET_MSC_TINTMSK_TGFSCIM;
209 ENET_MSC_RINTMSK = ENET_MSC_RINTMSK_RGUFIM | ENET_MSC_RINTMSK_RFAEIM |
210 ENET_MSC_RINTMSK_RFCEIM;
213 ENET_MAC_INTMSK = ENET_MAC_INTMSK_TMSTIM | ENET_MAC_INTMSK_WUMIM;
215 ENET_DMA_INTEN = ENET_DMA_INTEN_NIE | ENET_DMA_INTEN_RIE | ENET_DMA_INTEN_TIE;
225 ENET_MAC_CFG |= ENET_MAC_CFG_TEN | ENET_MAC_CFG_REN;
227 ENET_DMA_CTL |= ENET_DMA_CTL_STE | ENET_DMA_CTL_SRE;
238 #if defined(USE_GD32307C_EVAL)
248 rcu_periph_clock_enable(RCU_AF);
251 rcu_periph_clock_enable(RCU_GPIOA);
252 rcu_periph_clock_enable(RCU_GPIOB);
253 rcu_periph_clock_enable(RCU_GPIOC);
256 gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_8);
259 rcu_pll2_config(RCU_PLL2_MUL10);
260 rcu_osci_on(RCU_PLL2_CK);
261 rcu_osci_stab_wait(RCU_PLL2_CK);
262 rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2);
265 gpio_ethernet_phy_select(GPIO_ENET_PHY_RMII);
268 gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_1);
270 gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
272 gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_7);
275 gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_11);
277 gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_12);
279 gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13);
282 gpio_init(GPIOC, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1);
284 gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4);
286 gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_5);
305 txDmaDesc[i].tdes0 = ENET_TDES0_INTC | ENET_TDES0_TCHM;
369 if(interface->phyDriver != NULL)
372 interface->phyDriver->tick(interface);
374 else if(interface->switchDriver != NULL)
377 interface->switchDriver->tick(interface);
394 NVIC_EnableIRQ(ENET_IRQn);
397 if(interface->phyDriver != NULL)
400 interface->phyDriver->enableIrq(interface);
402 else if(interface->switchDriver != NULL)
405 interface->switchDriver->enableIrq(interface);
422 NVIC_DisableIRQ(ENET_IRQn);
425 if(interface->phyDriver != NULL)
428 interface->phyDriver->disableIrq(interface);
430 else if(interface->switchDriver != NULL)
433 interface->switchDriver->disableIrq(interface);
458 status = ENET_DMA_STAT;
461 if((status & ENET_DMA_STAT_TS) != 0)
464 ENET_DMA_STAT = ENET_DMA_STAT_TS;
467 if((txCurDmaDesc->
tdes0 & ENET_TDES0_DAV) == 0)
475 if((status & ENET_DMA_STAT_RS) != 0)
478 ENET_DMA_STAT = ENET_DMA_STAT_RS;
481 nicDriverInterface->nicEvent =
TRUE;
487 ENET_DMA_STAT = ENET_DMA_STAT_NI;
542 if((txCurDmaDesc->
tdes0 & ENET_TDES0_DAV) != 0)
553 txCurDmaDesc->
tdes0 |= ENET_TDES0_LSG | ENET_TDES0_FSG;
555 txCurDmaDesc->
tdes0 |= ENET_TDES0_DAV;
558 ENET_DMA_STAT = ENET_DMA_STAT_TBU;
566 if((txCurDmaDesc->
tdes0 & ENET_TDES0_DAV) == 0)
590 if((rxCurDmaDesc->
rdes0 & ENET_RDES0_DAV) == 0)
593 if((rxCurDmaDesc->
rdes0 & ENET_RDES0_FDES) != 0 &&
594 (rxCurDmaDesc->
rdes0 & ENET_RDES0_LDES) != 0)
597 if((rxCurDmaDesc->
rdes0 & ENET_RDES0_ERRS) == 0)
600 n = (rxCurDmaDesc->
rdes0 & ENET_RDES0_FRML) >> 16;
627 rxCurDmaDesc->
rdes0 = ENET_RDES0_DAV;
638 ENET_DMA_STAT = ENET_DMA_STAT_RBU;
659 uint32_t hashTable[2];
667 ENET_MAC_ADDR0L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
668 ENET_MAC_ADDR0H = interface->macAddr.w[2] | ENET_MAC_ADDR0H_MO;
684 entry = &interface->macAddrFilter[i];
697 k = (crc >> 26) & 0x3F;
700 hashTable[k / 32] |= (1 << (k % 32));
708 unicastMacAddr[j++] = entry->
addr;
718 ENET_MAC_ADDR1L = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
719 ENET_MAC_ADDR1H = unicastMacAddr[0].w[2] | ENET_MAC_ADDR1H_AFE;
732 ENET_MAC_ADDR2L = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
733 ENET_MAC_ADDR2H = unicastMacAddr[1].w[2] | ENET_MAC_ADDR2H_AFE;
746 ENET_MAC_ADDR3L = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
747 ENET_MAC_ADDR3H = unicastMacAddr[2].w[2] | ENET_MAC_ADDR3H_AFE;
757 ENET_MAC_HLL = hashTable[0];
758 ENET_MAC_HLH = hashTable[1];
761 TRACE_DEBUG(
" ENET_MAC_HLL = %08" PRIX32
"\r\n", ENET_MAC_HLL);
762 TRACE_DEBUG(
" ENET_MAC_HLH = %08" PRIX32
"\r\n", ENET_MAC_HLH);
780 config = ENET_MAC_CFG;
785 config |= ENET_MAC_CFG_SPD;
789 config &= ~ENET_MAC_CFG_SPD;
795 config |= ENET_MAC_CFG_DPM;
799 config &= ~ENET_MAC_CFG_DPM;
803 ENET_MAC_CFG = config;
827 temp = ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_CLR;
829 temp |= ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PB;
831 temp |= MAC_PHY_CTL_PA(phyAddr);
833 temp |= MAC_PHY_CTL_PR(
regAddr);
836 ENET_MAC_PHY_DATA =
data & ENET_MAC_PHY_DATA_PD;
839 ENET_MAC_PHY_CTL = temp;
841 while((ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB) != 0)
870 temp = ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_CLR;
872 temp |= ENET_MAC_PHY_CTL_PB;
874 temp |= MAC_PHY_CTL_PA(phyAddr);
876 temp |= MAC_PHY_CTL_PR(
regAddr);
879 ENET_MAC_PHY_CTL = temp;
881 while((ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB) != 0)
886 data = ENET_MAC_PHY_DATA & ENET_MAC_PHY_DATA_PD;
914 p = (uint8_t *)
data;
919 for(i = 0; i <
length; i++)
922 for(j = 0; j < 8; j++)
925 if((((crc >> 31) ^ (
p[i] >> j)) & 0x01) != 0)
927 crc = (crc << 1) ^ 0x04C11DB7;