mimxrt1052_eth_driver.c
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1 /**
2  * @file mimxrt1052_eth_driver.c
3  * @brief i.MX RT1050 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include "fsl_device_registers.h"
34 #include "fsl_gpio.h"
35 #include "fsl_iomuxc.h"
36 #include "core/net.h"
38 #include "debug.h"
39 
40 //Underlying network interface
41 static NetInterface *nicDriverInterface;
42 
43 //IAR EWARM compiler?
44 #if defined(__ICCARM__)
45 
46 //TX buffer
47 #pragma data_alignment = 16
48 #pragma location = ".ram_no_cache"
50 //RX buffer
51 #pragma data_alignment = 16
52 #pragma location = ".ram_no_cache"
54 //TX buffer descriptors
55 #pragma data_alignment = 16
56 #pragma location = ".ram_no_cache"
57 static uint32_t txBufferDesc[MIMXRT1052_ETH_TX_BUFFER_COUNT][8];
58 //RX buffer descriptors
59 #pragma data_alignment = 16
60 #pragma location = ".ram_no_cache"
61 static uint32_t rxBufferDesc[MIMXRT1052_ETH_RX_BUFFER_COUNT][8];
62 
63 //ARM or GCC compiler?
64 #else
65 
66 //TX buffer
68  __attribute__((aligned(16), __section__(".ram_no_cache")));
69 //RX buffer
71  __attribute__((aligned(16), __section__(".ram_no_cache")));
72 //TX buffer descriptors
73 static uint32_t txBufferDesc[MIMXRT1052_ETH_TX_BUFFER_COUNT][8]
74  __attribute__((aligned(16), __section__(".ram_no_cache")));
75 //RX buffer descriptors
76 static uint32_t rxBufferDesc[MIMXRT1052_ETH_RX_BUFFER_COUNT][8]
77  __attribute__((aligned(16), __section__(".ram_no_cache")));
78 
79 #endif
80 
81 //TX buffer index
82 static uint_t txBufferIndex;
83 //RX buffer index
84 static uint_t rxBufferIndex;
85 
86 
87 /**
88  * @brief i.MX RT1052 Ethernet MAC driver
89  **/
90 
92 {
94  ETH_MTU,
105  TRUE,
106  TRUE,
107  TRUE,
108  FALSE
109 };
110 
111 
112 /**
113  * @brief i.MX RT1052 Ethernet MAC initialization
114  * @param[in] interface Underlying network interface
115  * @return Error code
116  **/
117 
119 {
120  error_t error;
121  uint32_t value;
122 
123  //Debug message
124  TRACE_INFO("Initializing i.MX RT1052 Ethernet MAC...\r\n");
125 
126  //Save underlying network interface
127  nicDriverInterface = interface;
128 
129  //Enable ENET peripheral clock
130  CLOCK_EnableClock(kCLOCK_Enet);
131 
132  //GPIO configuration
133  mimxrt1052EthInitGpio(interface);
134 
135  //Reset ENET module
136  ENET->ECR = ENET_ECR_RESET_MASK;
137  //Wait for the reset to complete
138  while(ENET->ECR & ENET_ECR_RESET_MASK);
139 
140  //Receive control register
141  ENET->RCR = ENET_RCR_MAX_FL(1518) | ENET_RCR_RMII_MODE_MASK |
142  ENET_RCR_MII_MODE_MASK;
143 
144  //Transmit control register
145  ENET->TCR = 0;
146  //Configure MDC clock frequency
147  ENET->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
148 
149  //PHY transceiver initialization
150  error = interface->phyDriver->init(interface);
151  //Failed to initialize PHY transceiver?
152  if(error)
153  return error;
154 
155  //Set the MAC address (upper 16 bits)
156  value = interface->macAddr.b[5];
157  value |= (interface->macAddr.b[4] << 8);
158  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
159 
160  //Set the MAC address (lower 32 bits)
161  value = interface->macAddr.b[3];
162  value |= (interface->macAddr.b[2] << 8);
163  value |= (interface->macAddr.b[1] << 16);
164  value |= (interface->macAddr.b[0] << 24);
165  ENET->PALR = ENET_PALR_PADDR1(value);
166 
167  //Hash table for unicast address filtering
168  ENET->IALR = 0;
169  ENET->IAUR = 0;
170  //Hash table for multicast address filtering
171  ENET->GALR = 0;
172  ENET->GAUR = 0;
173 
174  //Disable transmit accelerator functions
175  ENET->TACC = 0;
176  //Disable receive accelerator functions
177  ENET->RACC = 0;
178 
179  //Use enhanced buffer descriptors
180  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
181  //Clear MIC counters
182  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
183 
184  //Initialize buffer descriptors
185  mimxrt1052EthInitBufferDesc(interface);
186 
187  //Clear any pending interrupts
188  ENET->EIR = 0xFFFFFFFF;
189  //Enable desired interrupts
190  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
191 
192  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
193  NVIC_SetPriorityGrouping(MIMXRT1052_ETH_IRQ_PRIORITY_GROUPING);
194 
195  //Configure ENET interrupt priority
196  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(MIMXRT1052_ETH_IRQ_PRIORITY_GROUPING,
198 
199  //Enable Ethernet MAC
200  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
201  //Instruct the DMA to poll the receive descriptor list
202  ENET->RDAR = ENET_RDAR_RDAR_MASK;
203 
204  //Accept any packets from the upper layer
205  osSetEvent(&interface->nicTxEvent);
206 
207  //Successful initialization
208  return NO_ERROR;
209 }
210 
211 
212 //MIMXRT1050-EVK evaluation board?
213 #if defined(USE_MIMXRT1050_EVK)
214 
215 /**
216  * @brief GPIO configuration
217  * @param[in] interface Underlying network interface
218  **/
219 
220 void mimxrt1052EthInitGpio(NetInterface *interface)
221 {
222  gpio_pin_config_t pinConfig;
223  clock_enet_pll_config_t pllConfig;
224 
225  //Configure ENET PLL (50MHz)
226  pllConfig.enableClkOutput0 = true;
227  pllConfig.enableClkOutput1 = false;
228  pllConfig.enableClkOutput2 = false;
229  pllConfig.loopDivider0 = 1;
230  pllConfig.loopDivider1 = 0;
231  CLOCK_InitEnetPll(&pllConfig);
232 
233  //Enable ENET1_TX_CLK output driver
234  IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
235 
236  //Enable IOMUXC clock
237  CLOCK_EnableClock(kCLOCK_Iomuxc);
238 
239  //Configure GPIO_B1_04 pin as ENET_RX_DATA00
240  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
241 
242  //Set GPIO_B1_04 pad properties
243  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00,
244  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
245  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
246  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
247  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
248  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
249  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
250  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
251  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
252 
253  //Configure GPIO_B1_05 pin as ENET_RX_DATA01
254  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
255 
256  //Set GPIO_B1_05 pad properties
257  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01,
258  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
259  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
260  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
261  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
262  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
263  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
264  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
265  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
266 
267  //Configure GPIO_B1_06 pin as ENET_RX_EN
268  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
269 
270  //Set GPIO_B1_06 pad properties
271  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN,
272  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
273  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
274  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
275  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
276  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
277  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
278  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
279  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
280 
281  //Configure GPIO_B1_07 pin as ENET_TX_DATA00
282  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
283 
284  //Set GPIO_B1_07 pad properties
285  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00,
286  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
287  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
288  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
289  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
290  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
291  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
292  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
293  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
294 
295  //Configure GPIO_B1_08 pin as ENET_TX_DATA01
296  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
297 
298  //Set GPIO_B1_08 pad properties
299  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01,
300  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
301  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
302  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
303  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
304  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
305  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
306  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
307  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
308 
309  //Configure GPIO_B1_09 pin as ENET_TX_EN
310  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
311 
312  //Set GPIO_B1_09 pad properties
313  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN,
314  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
315  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
316  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
317  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
318  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
319  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
320  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
321  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
322 
323  //Configure GPIO_B1_10 pin as ENET_REF_CLK
324  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
325 
326  //Set GPIO_B1_10 pad properties
327  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK,
328  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
329  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
330  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
331  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
332  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
333  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
334  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
335  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
336 
337  //Configure GPIO_B1_11 pin as ENET_RX_ER
338  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
339 
340  //Set GPIO_B1_11 pad properties
341  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER,
342  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
343  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
344  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
345  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
346  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
347  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
348  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
349  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
350 
351  //Configure GPIO_EMC_40 pin as ENET_MDC
352  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
353 
354  //Set GPIO_EMC_40 pad properties
355  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC,
356  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
357  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
358  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
359  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
360  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
361  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
362  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
363  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
364 
365  //Configure GPIO_EMC_41 pin as ENET_MDIO
366  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
367 
368  //Set GPIO_EMC_41 pad properties
369  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO,
370  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
371  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
372  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
373  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
374  IOMUXC_SW_PAD_CTL_PAD_ODE(1) |
375  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
376  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
377  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
378 
379  //Configure GPIO_AD_B0_09 pin as GPIO1_IO09
380  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
381 
382  //Set GPIO_AD_B0_09 pad properties
383  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
384  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
385  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
386  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
387  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
388  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
389  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
390  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
391  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
392 
393  //Configure GPIO_AD_B0_10 pin as GPIO1_IO10
394  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0);
395 
396  //Set GPIO_AD_B0_10 pad properties
397  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,
398  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
399  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
400  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
401  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
402  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
403  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
404  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
405  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
406 
407  //Configure ENET_RST as an output
408  pinConfig.direction = kGPIO_DigitalOutput;
409  pinConfig.outputLogic = 0;
410  pinConfig.interruptMode = kGPIO_NoIntmode;
411  GPIO_PinInit(GPIO1, 9, &pinConfig);
412 
413  //Configure ENET_INT as an input
414  pinConfig.direction = kGPIO_DigitalInput;
415  pinConfig.outputLogic = 0;
416  pinConfig.interruptMode = kGPIO_NoIntmode;
417  GPIO_PinInit(GPIO1, 10, &pinConfig);
418 
419  //Reset PHY transceiver (hard reset)
420  GPIO_PinWrite(GPIO1, 9, 0);
421  sleep(10);
422  GPIO_PinWrite(GPIO1, 9, 1);
423  sleep(10);
424 }
425 
426 #endif
427 
428 
429 /**
430  * @brief Initialize buffer descriptors
431  * @param[in] interface Underlying network interface
432  **/
433 
435 {
436  uint_t i;
437  uint32_t address;
438 
439  //Clear TX and RX buffer descriptors
440  memset(txBufferDesc, 0, sizeof(txBufferDesc));
441  memset(rxBufferDesc, 0, sizeof(rxBufferDesc));
442 
443  //Initialize TX buffer descriptors
444  for(i = 0; i < MIMXRT1052_ETH_TX_BUFFER_COUNT; i++)
445  {
446  //Calculate the address of the current TX buffer
447  address = (uint32_t) txBuffer[i];
448  //Transmit buffer address
449  txBufferDesc[i][1] = address;
450  //Generate interrupts
451  txBufferDesc[i][2] = ENET_TBD2_INT;
452  }
453 
454  //Mark the last descriptor entry with the wrap flag
455  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
456  //Initialize TX buffer index
457  txBufferIndex = 0;
458 
459  //Initialize RX buffer descriptors
460  for(i = 0; i < MIMXRT1052_ETH_RX_BUFFER_COUNT; i++)
461  {
462  //Calculate the address of the current RX buffer
463  address = (uint32_t) rxBuffer[i];
464  //The descriptor is initially owned by the DMA
465  rxBufferDesc[i][0] = ENET_RBD0_E;
466  //Receive buffer address
467  rxBufferDesc[i][1] = address;
468  //Generate interrupts
469  rxBufferDesc[i][2] = ENET_RBD2_INT;
470  }
471 
472  //Mark the last descriptor entry with the wrap flag
473  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
474  //Initialize RX buffer index
475  rxBufferIndex = 0;
476 
477  //Start location of the TX descriptor list
478  ENET->TDSR = (uint32_t) txBufferDesc;
479  //Start location of the RX descriptor list
480  ENET->RDSR = (uint32_t) rxBufferDesc;
481  //Maximum receive buffer size
482  ENET->MRBR = MIMXRT1052_ETH_RX_BUFFER_SIZE;
483 }
484 
485 
486 /**
487  * @brief i.MX RT1052 Ethernet MAC timer handler
488  *
489  * This routine is periodically called by the TCP/IP stack to
490  * handle periodic operations such as polling the link state
491  *
492  * @param[in] interface Underlying network interface
493  **/
494 
496 {
497  //Handle periodic operations
498  interface->phyDriver->tick(interface);
499 }
500 
501 
502 /**
503  * @brief Enable interrupts
504  * @param[in] interface Underlying network interface
505  **/
506 
508 {
509  //Enable Ethernet MAC interrupts
510  NVIC_EnableIRQ(ENET_IRQn);
511  //Enable Ethernet PHY interrupts
512  interface->phyDriver->enableIrq(interface);
513 }
514 
515 
516 /**
517  * @brief Disable interrupts
518  * @param[in] interface Underlying network interface
519  **/
520 
522 {
523  //Disable Ethernet MAC interrupts
524  NVIC_DisableIRQ(ENET_IRQn);
525  //Disable Ethernet PHY interrupts
526  interface->phyDriver->disableIrq(interface);
527 }
528 
529 
530 /**
531  * @brief Ethernet MAC interrupt
532  **/
533 
534 void ENET_IRQHandler(void)
535 {
536  bool_t flag;
537  uint32_t events;
538 
539  //Enter interrupt service routine
540  osEnterIsr();
541 
542  //This flag will be set if a higher priority task must be woken
543  flag = FALSE;
544  //Read interrupt event register
545  events = ENET->EIR;
546 
547  //A packet has been transmitted?
548  if(events & ENET_EIR_TXF_MASK)
549  {
550  //Clear TXF interrupt flag
551  ENET->EIR = ENET_EIR_TXF_MASK;
552 
553  //Check whether the TX buffer is available for writing
554  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
555  {
556  //Notify the TCP/IP stack that the transmitter is ready to send
557  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
558  }
559 
560  //Instruct the DMA to poll the transmit descriptor list
561  ENET->TDAR = ENET_TDAR_TDAR_MASK;
562  }
563 
564  //A packet has been received?
565  if(events & ENET_EIR_RXF_MASK)
566  {
567  //Disable RXF interrupt
568  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
569 
570  //Set event flag
571  nicDriverInterface->nicEvent = TRUE;
572  //Notify the TCP/IP stack of the event
573  flag = osSetEventFromIsr(&netEvent);
574  }
575 
576  //System bus error?
577  if(events & ENET_EIR_EBERR_MASK)
578  {
579  //Disable EBERR interrupt
580  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
581 
582  //Set event flag
583  nicDriverInterface->nicEvent = TRUE;
584  //Notify the TCP/IP stack of the event
585  flag |= osSetEventFromIsr(&netEvent);
586  }
587 
588  //Leave interrupt service routine
589  osExitIsr(flag);
590 }
591 
592 
593 /**
594  * @brief i.MX RT1052 Ethernet MAC event handler
595  * @param[in] interface Underlying network interface
596  **/
597 
599 {
600  error_t error;
601  uint32_t status;
602 
603  //Read interrupt event register
604  status = ENET->EIR;
605 
606  //Packet received?
607  if(status & ENET_EIR_RXF_MASK)
608  {
609  //Clear RXF interrupt flag
610  ENET->EIR = ENET_EIR_RXF_MASK;
611 
612  //Process all pending packets
613  do
614  {
615  //Read incoming packet
616  error = mimxrt1052EthReceivePacket(interface);
617 
618  //No more data in the receive buffer?
619  } while(error != ERROR_BUFFER_EMPTY);
620  }
621 
622  //System bus error?
623  if(status & ENET_EIR_EBERR_MASK)
624  {
625  //Clear EBERR interrupt flag
626  ENET->EIR = ENET_EIR_EBERR_MASK;
627 
628  //Disable Ethernet MAC
629  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
630  //Reset buffer descriptors
631  mimxrt1052EthInitBufferDesc(interface);
632  //Resume normal operation
633  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
634  //Instruct the DMA to poll the receive descriptor list
635  ENET->RDAR = ENET_RDAR_RDAR_MASK;
636  }
637 
638  //Re-enable Ethernet MAC interrupts
639  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
640 }
641 
642 
643 /**
644  * @brief Send a packet
645  * @param[in] interface Underlying network interface
646  * @param[in] buffer Multi-part buffer containing the data to send
647  * @param[in] offset Offset to the first data byte
648  * @return Error code
649  **/
650 
652  const NetBuffer *buffer, size_t offset)
653 {
654  static uint8_t temp[MIMXRT1052_ETH_TX_BUFFER_SIZE];
655  size_t length;
656 
657  //Retrieve the length of the packet
658  length = netBufferGetLength(buffer) - offset;
659 
660  //Check the frame length
662  {
663  //The transmitter can accept another packet
664  osSetEvent(&interface->nicTxEvent);
665  //Report an error
666  return ERROR_INVALID_LENGTH;
667  }
668 
669  //Make sure the current buffer is available for writing
670  if(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R)
671  return ERROR_FAILURE;
672 
673  //Copy user data to the transmit buffer
674  netBufferRead(temp, buffer, offset, length);
675  memcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
676 
677  //Clear BDU flag
678  txBufferDesc[txBufferIndex][4] = 0;
679 
680  //Check current index
681  if(txBufferIndex < (MIMXRT1052_ETH_TX_BUFFER_COUNT - 1))
682  {
683  //Give the ownership of the descriptor to the DMA engine
684  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
686 
687  //Point to the next buffer
688  txBufferIndex++;
689  }
690  else
691  {
692  //Give the ownership of the descriptor to the DMA engine
693  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
695 
696  //Wrap around
697  txBufferIndex = 0;
698  }
699 
700  //Data synchronization barrier
701  __DSB();
702 
703  //Instruct the DMA to poll the transmit descriptor list
704  ENET->TDAR = ENET_TDAR_TDAR_MASK;
705 
706  //Check whether the next buffer is available for writing
707  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
708  {
709  //The transmitter can accept another packet
710  osSetEvent(&interface->nicTxEvent);
711  }
712 
713  //Successful processing
714  return NO_ERROR;
715 }
716 
717 
718 /**
719  * @brief Receive a packet
720  * @param[in] interface Underlying network interface
721  * @return Error code
722  **/
723 
725 {
726  static uint8_t temp[MIMXRT1052_ETH_RX_BUFFER_SIZE];
727  error_t error;
728  size_t n;
729 
730  //Make sure the current buffer is available for reading
731  if(!(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E))
732  {
733  //The frame should not span multiple buffers
734  if(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L)
735  {
736  //Check whether an error occurred
737  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
739  {
740  //Retrieve the length of the frame
741  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
742  //Limit the number of data to read
744 
745  //Copy data from the receive buffer
746  memcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
747 
748  //Pass the packet to the upper layer
749  nicProcessPacket(interface, temp, n);
750 
751  //Valid packet received
752  error = NO_ERROR;
753  }
754  else
755  {
756  //The received packet contains an error
757  error = ERROR_INVALID_PACKET;
758  }
759  }
760  else
761  {
762  //The packet is not valid
763  error = ERROR_INVALID_PACKET;
764  }
765 
766  //Clear BDU flag
767  rxBufferDesc[rxBufferIndex][4] = 0;
768 
769  //Check current index
770  if(rxBufferIndex < (MIMXRT1052_ETH_RX_BUFFER_COUNT - 1))
771  {
772  //Give the ownership of the descriptor back to the DMA engine
773  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
774  //Point to the next buffer
775  rxBufferIndex++;
776  }
777  else
778  {
779  //Give the ownership of the descriptor back to the DMA engine
780  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
781  //Wrap around
782  rxBufferIndex = 0;
783  }
784 
785  //Instruct the DMA to poll the receive descriptor list
786  ENET->RDAR = ENET_RDAR_RDAR_MASK;
787  }
788  else
789  {
790  //No more data in the receive buffer
791  error = ERROR_BUFFER_EMPTY;
792  }
793 
794  //Return status code
795  return error;
796 }
797 
798 
799 /**
800  * @brief Configure MAC address filtering
801  * @param[in] interface Underlying network interface
802  * @return Error code
803  **/
804 
806 {
807  uint_t i;
808  uint_t k;
809  uint32_t crc;
810  uint32_t unicastHashTable[2];
811  uint32_t multicastHashTable[2];
812  MacFilterEntry *entry;
813 
814  //Debug message
815  TRACE_DEBUG("Updating i.MX RT1052 hash table...\r\n");
816 
817  //Clear hash table (unicast address filtering)
818  unicastHashTable[0] = 0;
819  unicastHashTable[1] = 0;
820 
821  //Clear hash table (multicast address filtering)
822  multicastHashTable[0] = 0;
823  multicastHashTable[1] = 0;
824 
825  //The MAC address filter contains the list of MAC addresses to accept
826  //when receiving an Ethernet frame
827  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
828  {
829  //Point to the current entry
830  entry = &interface->macAddrFilter[i];
831 
832  //Valid entry?
833  if(entry->refCount > 0)
834  {
835  //Compute CRC over the current MAC address
836  crc = mimxrt1052EthCalcCrc(&entry->addr, sizeof(MacAddr));
837 
838  //The upper 6 bits in the CRC register are used to index the
839  //contents of the hash table
840  k = (crc >> 26) & 0x3F;
841 
842  //Multicast address?
843  if(macIsMulticastAddr(&entry->addr))
844  {
845  //Update the multicast hash table
846  multicastHashTable[k / 32] |= (1 << (k % 32));
847  }
848  else
849  {
850  //Update the unicast hash table
851  unicastHashTable[k / 32] |= (1 << (k % 32));
852  }
853  }
854  }
855 
856  //Write the hash table (unicast address filtering)
857  ENET->IALR = unicastHashTable[0];
858  ENET->IAUR = unicastHashTable[1];
859 
860  //Write the hash table (multicast address filtering)
861  ENET->GALR = multicastHashTable[0];
862  ENET->GAUR = multicastHashTable[1];
863 
864  //Debug message
865  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
866  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
867  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
868  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
869 
870  //Successful processing
871  return NO_ERROR;
872 }
873 
874 
875 /**
876  * @brief Adjust MAC configuration parameters for proper operation
877  * @param[in] interface Underlying network interface
878  * @return Error code
879  **/
880 
882 {
883  //Disable Ethernet MAC while modifying configuration registers
884  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
885 
886  //10BASE-T or 100BASE-TX operation mode?
887  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
888  {
889  //100 Mbps operation
890  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
891  }
892  else
893  {
894  //10 Mbps operation
895  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
896  }
897 
898  //Half-duplex or full-duplex mode?
899  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
900  {
901  //Full-duplex mode
902  ENET->TCR |= ENET_TCR_FDEN_MASK;
903  //Receive path operates independently of transmit
904  ENET->RCR &= ~ENET_RCR_DRT_MASK;
905  }
906  else
907  {
908  //Half-duplex mode
909  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
910  //Disable reception of frames while transmitting
911  ENET->RCR |= ENET_RCR_DRT_MASK;
912  }
913 
914  //Reset buffer descriptors
915  mimxrt1052EthInitBufferDesc(interface);
916 
917  //Re-enable Ethernet MAC
918  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
919  //Instruct the DMA to poll the receive descriptor list
920  ENET->RDAR = ENET_RDAR_RDAR_MASK;
921 
922  //Successful processing
923  return NO_ERROR;
924 }
925 
926 
927 /**
928  * @brief Write PHY register
929  * @param[in] phyAddr PHY address
930  * @param[in] regAddr Register address
931  * @param[in] data Register value
932  **/
933 
934 void mimxrt1052EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
935 {
936  uint32_t value;
937 
938  //Set up a write operation
939  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
940  //PHY address
941  value |= ENET_MMFR_PA(phyAddr);
942  //Register address
943  value |= ENET_MMFR_RA(regAddr);
944  //Register value
945  value |= ENET_MMFR_DATA(data);
946 
947  //Clear MII interrupt flag
948  ENET->EIR = ENET_EIR_MII_MASK;
949  //Start a write operation
950  ENET->MMFR = value;
951  //Wait for the write to complete
952  while(!(ENET->EIR & ENET_EIR_MII_MASK));
953 }
954 
955 
956 /**
957  * @brief Read PHY register
958  * @param[in] phyAddr PHY address
959  * @param[in] regAddr Register address
960  * @return Register value
961  **/
962 
963 uint16_t mimxrt1052EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
964 {
965  uint32_t value;
966 
967  //Set up a read operation
968  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
969  //PHY address
970  value |= ENET_MMFR_PA(phyAddr);
971  //Register address
972  value |= ENET_MMFR_RA(regAddr);
973 
974  //Clear MII interrupt flag
975  ENET->EIR = ENET_EIR_MII_MASK;
976  //Start a read operation
977  ENET->MMFR = value;
978  //Wait for the read to complete
979  while(!(ENET->EIR & ENET_EIR_MII_MASK));
980 
981  //Return PHY register contents
982  return ENET->MMFR & ENET_MMFR_DATA_MASK;
983 }
984 
985 
986 /**
987  * @brief CRC calculation
988  * @param[in] data Pointer to the data over which to calculate the CRC
989  * @param[in] length Number of bytes to process
990  * @return Resulting CRC value
991  **/
992 
993 uint32_t mimxrt1052EthCalcCrc(const void *data, size_t length)
994 {
995  uint_t i;
996  uint_t j;
997 
998  //Point to the data over which to calculate the CRC
999  const uint8_t *p = (uint8_t *) data;
1000  //CRC preset value
1001  uint32_t crc = 0xFFFFFFFF;
1002 
1003  //Loop through data
1004  for(i = 0; i < length; i++)
1005  {
1006  //Update CRC value
1007  crc ^= p[i];
1008  //The message is processed bit by bit
1009  for(j = 0; j < 8; j++)
1010  {
1011  if(crc & 0x00000001)
1012  crc = (crc >> 1) ^ 0xEDB88320;
1013  else
1014  crc = crc >> 1;
1015  }
1016  }
1017 
1018  //Return CRC value
1019  return crc;
1020 }
void mimxrt1052EthEventHandler(NetInterface *interface)
i.MX RT1052 Ethernet MAC event handler
MacAddr addr
MAC address.
Definition: ethernet.h:210
uint16_t mimxrt1052EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t mimxrt1052EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
TCP/IP stack core.
Debugging facilities.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
void mimxrt1052EthInitGpio(NetInterface *interface)
Generic error code.
Definition: error.h:43
#define ENET_RBD0_DATA_LENGTH
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:98
#define txBuffer
#define ENET_TBD0_TC
#define ENET_RBD0_TR
#define ENET_TBD2_INT
error_t mimxrt1052EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define sleep(delay)
Definition: os_port.h:126
#define MIMXRT1052_ETH_IRQ_GROUP_PRIORITY
void mimxrt1052EthTick(NetInterface *interface)
i.MX RT1052 Ethernet MAC timer handler
error_t mimxrt1052EthInit(NetInterface *interface)
i.MX RT1052 Ethernet MAC initialization
void mimxrt1052EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define MIMXRT1052_ETH_TX_BUFFER_SIZE
#define ENET_TBD0_L
#define MIMXRT1052_ETH_TX_BUFFER_COUNT
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
void mimxrt1052EthEnableIrq(NetInterface *interface)
Enable interrupts.
uint32_t mimxrt1052EthCalcCrc(const void *data, size_t length)
CRC calculation.
#define ENET_RBD0_W
void mimxrt1052EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define ENET_TBD0_R
#define ENET_RBD0_CR
#define ENET_RBD0_NO
error_t mimxrt1052EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define ENET_RBD0_E
NIC driver.
Definition: nic.h:161
i.MX RT1050 Ethernet MAC controller
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define ENET_RBD0_LG
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
void mimxrt1052EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
Ethernet interface.
Definition: nic.h:69
#define ENET_TBD0_W
Success.
Definition: error.h:42
#define rxBuffer
Ipv6Addr address
const NicDriver mimxrt1052EthDriver
i.MX RT1052 Ethernet MAC driver
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
#define ENET_RBD2_INT
unsigned int uint_t
Definition: compiler_port.h:43
__start_packed struct @112 MacAddr
MAC address.
void ENET_IRQHandler(void)
Ethernet MAC interrupt.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint8_t value[]
Definition: dtls_misc.h:141
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define MIMXRT1052_ETH_RX_BUFFER_SIZE
#define MIMXRT1052_ETH_IRQ_PRIORITY_GROUPING
#define MIMXRT1052_ETH_IRQ_SUB_PRIORITY
#define osExitIsr(flag)
#define ENET_TBD0_DATA_LENGTH
#define osEnterIsr()
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define MIMXRT1052_ETH_RX_BUFFER_COUNT
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
error_t mimxrt1052EthReceivePacket(NetInterface *interface)
Receive a packet.
#define ENET_RBD0_OV
#define ENET_RBD0_L
MAC filter table entry.
Definition: ethernet.h:208
#define TRACE_DEBUG(...)
Definition: debug.h:98