mimxrt1060_eth_driver.c
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1 /**
2  * @file mimxrt1060_eth_driver.c
3  * @brief i.MX RT1060 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 16
50 #pragma location = ".ram_no_cache"
52 //RX buffer
53 #pragma data_alignment = 16
54 #pragma location = ".ram_no_cache"
56 //TX buffer descriptors
57 #pragma data_alignment = 16
58 #pragma location = ".ram_no_cache"
59 static uint32_t txBufferDesc[MIMXRT1060_ETH_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 16
62 #pragma location = ".ram_no_cache"
63 static uint32_t rxBufferDesc[MIMXRT1060_ETH_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(16), __section__(".ram_no_cache")));
71 //RX buffer
73  __attribute__((aligned(16), __section__(".ram_no_cache")));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MIMXRT1060_ETH_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(16), __section__(".ram_no_cache")));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MIMXRT1060_ETH_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(16), __section__(".ram_no_cache")));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX RT1060 Ethernet MAC driver
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX RT1060 Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX RT1060 Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mimxrt1060EthInitGpio(interface);
136 
137  //Reset ENET module
138  ENET->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while(ENET->ECR & ENET_ECR_RESET_MASK)
141  {
142  }
143 
144  //Receive control register
145  ENET->RCR = ENET_RCR_MAX_FL(MIMXRT1060_ETH_RX_BUFFER_SIZE) |
146  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
147 
148  //Transmit control register
149  ENET->TCR = 0;
150  //Configure MDC clock frequency
151  ENET->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
152 
153  //PHY transceiver initialization
154  error = interface->phyDriver->init(interface);
155  //Failed to initialize PHY transceiver?
156  if(error)
157  return error;
158 
159  //Set the MAC address of the station (upper 16 bits)
160  value = interface->macAddr.b[5];
161  value |= (interface->macAddr.b[4] << 8);
162  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
163 
164  //Set the MAC address of the station (lower 32 bits)
165  value = interface->macAddr.b[3];
166  value |= (interface->macAddr.b[2] << 8);
167  value |= (interface->macAddr.b[1] << 16);
168  value |= (interface->macAddr.b[0] << 24);
169  ENET->PALR = ENET_PALR_PADDR1(value);
170 
171  //Hash table for unicast address filtering
172  ENET->IALR = 0;
173  ENET->IAUR = 0;
174  //Hash table for multicast address filtering
175  ENET->GALR = 0;
176  ENET->GAUR = 0;
177 
178  //Disable transmit accelerator functions
179  ENET->TACC = 0;
180  //Disable receive accelerator functions
181  ENET->RACC = 0;
182 
183  //Use enhanced buffer descriptors
184  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
185  //Clear MIC counters
186  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
187 
188  //Initialize buffer descriptors
189  mimxrt1060EthInitBufferDesc(interface);
190 
191  //Clear any pending interrupts
192  ENET->EIR = 0xFFFFFFFF;
193  //Enable desired interrupts
194  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
195 
196  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
197  NVIC_SetPriorityGrouping(MIMXRT1060_ETH_IRQ_PRIORITY_GROUPING);
198 
199  //Configure ENET interrupt priority
200  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(MIMXRT1060_ETH_IRQ_PRIORITY_GROUPING,
202 
203  //Enable Ethernet MAC
204  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
205  //Instruct the DMA to poll the receive descriptor list
206  ENET->RDAR = ENET_RDAR_RDAR_MASK;
207 
208  //Accept any packets from the upper layer
209  osSetEvent(&interface->nicTxEvent);
210 
211  //Successful initialization
212  return NO_ERROR;
213 }
214 
215 
216 //MIMXRT1060-EVK or MIMXRT1064-EVK evaluation board?
217 #if defined(USE_MIMXRT1060_EVK) || defined(USE_MIMXRT1064_EVK)
218 
219 /**
220  * @brief GPIO configuration
221  * @param[in] interface Underlying network interface
222  **/
223 
224 void mimxrt1060EthInitGpio(NetInterface *interface)
225 {
226  gpio_pin_config_t pinConfig;
227  clock_enet_pll_config_t pllConfig;
228 
229  //Configure ENET PLL (50MHz)
230  pllConfig.enableClkOutput = true;
231  pllConfig.enableClkOutput25M = false;
232  pllConfig.loopDivider = 1;
233  pllConfig.src = 0;
234  pllConfig.enableClkOutput1 = true;
235  pllConfig.loopDivider1 = 1;
236  CLOCK_InitEnetPll(&pllConfig);
237 
238  //Enable ENET1_TX_CLK output driver
239  IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
240 
241  //Enable IOMUXC clock
242  CLOCK_EnableClock(kCLOCK_Iomuxc);
243 
244  //Configure GPIO_B1_04 pin as ENET_RX_DATA00
245  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
246 
247  //Set GPIO_B1_04 pad properties
248  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00,
249  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
250  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
251  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
252  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
253  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
254  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
255  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
256  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
257 
258  //Configure GPIO_B1_05 pin as ENET_RX_DATA01
259  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
260 
261  //Set GPIO_B1_05 pad properties
262  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01,
263  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
264  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
265  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
266  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
267  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
268  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
269  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
270  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
271 
272  //Configure GPIO_B1_06 pin as ENET_RX_EN
273  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
274 
275  //Set GPIO_B1_06 pad properties
276  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN,
277  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
278  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
279  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
280  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
281  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
282  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
283  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
284  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
285 
286  //Configure GPIO_B1_07 pin as ENET_TX_DATA00
287  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
288 
289  //Set GPIO_B1_07 pad properties
290  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00,
291  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
292  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
293  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
294  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
295  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
296  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
297  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
298  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
299 
300  //Configure GPIO_B1_08 pin as ENET_TX_DATA01
301  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
302 
303  //Set GPIO_B1_08 pad properties
304  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01,
305  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
306  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
307  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
308  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
309  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
310  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
311  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
312  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
313 
314  //Configure GPIO_B1_09 pin as ENET_TX_EN
315  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
316 
317  //Set GPIO_B1_09 pad properties
318  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN,
319  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
320  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
321  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
322  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
323  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
324  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
325  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
326  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
327 
328  //Configure GPIO_B1_10 pin as ENET_REF_CLK
329  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
330 
331  //Set GPIO_B1_10 pad properties
332  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK,
333  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
334  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
335  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
336  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
337  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
338  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
339  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
340  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
341 
342  //Configure GPIO_B1_11 pin as ENET_RX_ER
343  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
344 
345  //Set GPIO_B1_11 pad properties
346  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER,
347  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
348  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
349  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
350  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
351  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
352  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
353  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
354  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
355 
356  //Configure GPIO_EMC_40 pin as ENET_MDC
357  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
358 
359  //Set GPIO_EMC_40 pad properties
360  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC,
361  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
362  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
363  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
364  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
365  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
366  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
367  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
368  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
369 
370  //Configure GPIO_EMC_41 pin as ENET_MDIO
371  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
372 
373  //Set GPIO_EMC_41 pad properties
374  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO,
375  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
376  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
377  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
378  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
379  IOMUXC_SW_PAD_CTL_PAD_ODE(1) |
380  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
381  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
382  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
383 
384  //Configure GPIO_AD_B0_09 pin as GPIO1_IO09
385  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
386 
387  //Set GPIO_AD_B0_09 pad properties
388  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
389  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
390  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
391  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
392  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
393  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
394  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
395  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
396  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
397 
398  //Configure GPIO_AD_B0_10 pin as GPIO1_IO10
399  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0);
400 
401  //Set GPIO_AD_B0_10 pad properties
402  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,
403  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
404  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
405  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
406  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
407  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
408  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
409  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
410  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
411 
412  //Configure ENET_RST as an output
413  pinConfig.direction = kGPIO_DigitalOutput;
414  pinConfig.outputLogic = 0;
415  pinConfig.interruptMode = kGPIO_NoIntmode;
416  GPIO_PinInit(GPIO1, 9, &pinConfig);
417 
418  //Configure ENET_INT as an input
419  pinConfig.direction = kGPIO_DigitalInput;
420  pinConfig.outputLogic = 0;
421  pinConfig.interruptMode = kGPIO_NoIntmode;
422  GPIO_PinInit(GPIO1, 10, &pinConfig);
423 
424  //Reset PHY transceiver (hard reset)
425  GPIO_PinWrite(GPIO1, 9, 0);
426  sleep(10);
427  GPIO_PinWrite(GPIO1, 9, 1);
428  sleep(10);
429 }
430 
431 #endif
432 
433 
434 /**
435  * @brief Initialize buffer descriptors
436  * @param[in] interface Underlying network interface
437  **/
438 
440 {
441  uint_t i;
442  uint32_t address;
443 
444  //Clear TX and RX buffer descriptors
445  memset(txBufferDesc, 0, sizeof(txBufferDesc));
446  memset(rxBufferDesc, 0, sizeof(rxBufferDesc));
447 
448  //Initialize TX buffer descriptors
449  for(i = 0; i < MIMXRT1060_ETH_TX_BUFFER_COUNT; i++)
450  {
451  //Calculate the address of the current TX buffer
452  address = (uint32_t) txBuffer[i];
453  //Transmit buffer address
454  txBufferDesc[i][1] = address;
455  //Generate interrupts
456  txBufferDesc[i][2] = ENET_TBD2_INT;
457  }
458 
459  //Mark the last descriptor entry with the wrap flag
460  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
461  //Initialize TX buffer index
462  txBufferIndex = 0;
463 
464  //Initialize RX buffer descriptors
465  for(i = 0; i < MIMXRT1060_ETH_RX_BUFFER_COUNT; i++)
466  {
467  //Calculate the address of the current RX buffer
468  address = (uint32_t) rxBuffer[i];
469  //The descriptor is initially owned by the DMA
470  rxBufferDesc[i][0] = ENET_RBD0_E;
471  //Receive buffer address
472  rxBufferDesc[i][1] = address;
473  //Generate interrupts
474  rxBufferDesc[i][2] = ENET_RBD2_INT;
475  }
476 
477  //Mark the last descriptor entry with the wrap flag
478  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
479  //Initialize RX buffer index
480  rxBufferIndex = 0;
481 
482  //Start location of the TX descriptor list
483  ENET->TDSR = (uint32_t) txBufferDesc;
484  //Start location of the RX descriptor list
485  ENET->RDSR = (uint32_t) rxBufferDesc;
486  //Maximum receive buffer size
487  ENET->MRBR = MIMXRT1060_ETH_RX_BUFFER_SIZE;
488 }
489 
490 
491 /**
492  * @brief i.MX RT1060 Ethernet MAC timer handler
493  *
494  * This routine is periodically called by the TCP/IP stack to
495  * handle periodic operations such as polling the link state
496  *
497  * @param[in] interface Underlying network interface
498  **/
499 
501 {
502  //Handle periodic operations
503  interface->phyDriver->tick(interface);
504 }
505 
506 
507 /**
508  * @brief Enable interrupts
509  * @param[in] interface Underlying network interface
510  **/
511 
513 {
514  //Enable Ethernet MAC interrupts
515  NVIC_EnableIRQ(ENET_IRQn);
516  //Enable Ethernet PHY interrupts
517  interface->phyDriver->enableIrq(interface);
518 }
519 
520 
521 /**
522  * @brief Disable interrupts
523  * @param[in] interface Underlying network interface
524  **/
525 
527 {
528  //Disable Ethernet MAC interrupts
529  NVIC_DisableIRQ(ENET_IRQn);
530  //Disable Ethernet PHY interrupts
531  interface->phyDriver->disableIrq(interface);
532 }
533 
534 
535 /**
536  * @brief Ethernet MAC interrupt
537  **/
538 
539 void ENET_IRQHandler(void)
540 {
541  bool_t flag;
542  uint32_t events;
543 
544  //Interrupt service routine prologue
545  osEnterIsr();
546 
547  //This flag will be set if a higher priority task must be woken
548  flag = FALSE;
549  //Read interrupt event register
550  events = ENET->EIR;
551 
552  //A packet has been transmitted?
553  if(events & ENET_EIR_TXF_MASK)
554  {
555  //Clear TXF interrupt flag
556  ENET->EIR = ENET_EIR_TXF_MASK;
557 
558  //Check whether the TX buffer is available for writing
559  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
560  {
561  //Notify the TCP/IP stack that the transmitter is ready to send
562  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
563  }
564 
565  //Instruct the DMA to poll the transmit descriptor list
566  ENET->TDAR = ENET_TDAR_TDAR_MASK;
567  }
568 
569  //A packet has been received?
570  if(events & ENET_EIR_RXF_MASK)
571  {
572  //Disable RXF interrupt
573  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
574 
575  //Set event flag
576  nicDriverInterface->nicEvent = TRUE;
577  //Notify the TCP/IP stack of the event
578  flag = osSetEventFromIsr(&netEvent);
579  }
580 
581  //System bus error?
582  if(events & ENET_EIR_EBERR_MASK)
583  {
584  //Disable EBERR interrupt
585  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
586 
587  //Set event flag
588  nicDriverInterface->nicEvent = TRUE;
589  //Notify the TCP/IP stack of the event
590  flag |= osSetEventFromIsr(&netEvent);
591  }
592 
593  //Interrupt service routine epilogue
594  osExitIsr(flag);
595 }
596 
597 
598 /**
599  * @brief i.MX RT1060 Ethernet MAC event handler
600  * @param[in] interface Underlying network interface
601  **/
602 
604 {
605  error_t error;
606  uint32_t status;
607 
608  //Read interrupt event register
609  status = ENET->EIR;
610 
611  //Packet received?
612  if(status & ENET_EIR_RXF_MASK)
613  {
614  //Clear RXF interrupt flag
615  ENET->EIR = ENET_EIR_RXF_MASK;
616 
617  //Process all pending packets
618  do
619  {
620  //Read incoming packet
621  error = mimxrt1060EthReceivePacket(interface);
622 
623  //No more data in the receive buffer?
624  } while(error != ERROR_BUFFER_EMPTY);
625  }
626 
627  //System bus error?
628  if(status & ENET_EIR_EBERR_MASK)
629  {
630  //Clear EBERR interrupt flag
631  ENET->EIR = ENET_EIR_EBERR_MASK;
632 
633  //Disable Ethernet MAC
634  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
635  //Reset buffer descriptors
636  mimxrt1060EthInitBufferDesc(interface);
637  //Resume normal operation
638  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
639  //Instruct the DMA to poll the receive descriptor list
640  ENET->RDAR = ENET_RDAR_RDAR_MASK;
641  }
642 
643  //Re-enable Ethernet MAC interrupts
644  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
645 }
646 
647 
648 /**
649  * @brief Send a packet
650  * @param[in] interface Underlying network interface
651  * @param[in] buffer Multi-part buffer containing the data to send
652  * @param[in] offset Offset to the first data byte
653  * @return Error code
654  **/
655 
657  const NetBuffer *buffer, size_t offset)
658 {
659  static uint8_t temp[MIMXRT1060_ETH_TX_BUFFER_SIZE];
660  size_t length;
661 
662  //Retrieve the length of the packet
663  length = netBufferGetLength(buffer) - offset;
664 
665  //Check the frame length
667  {
668  //The transmitter can accept another packet
669  osSetEvent(&interface->nicTxEvent);
670  //Report an error
671  return ERROR_INVALID_LENGTH;
672  }
673 
674  //Make sure the current buffer is available for writing
675  if(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R)
676  return ERROR_FAILURE;
677 
678  //Copy user data to the transmit buffer
679  netBufferRead(temp, buffer, offset, length);
680  memcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
681 
682  //Clear BDU flag
683  txBufferDesc[txBufferIndex][4] = 0;
684 
685  //Check current index
686  if(txBufferIndex < (MIMXRT1060_ETH_TX_BUFFER_COUNT - 1))
687  {
688  //Give the ownership of the descriptor to the DMA engine
689  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
691 
692  //Point to the next buffer
693  txBufferIndex++;
694  }
695  else
696  {
697  //Give the ownership of the descriptor to the DMA engine
698  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
700 
701  //Wrap around
702  txBufferIndex = 0;
703  }
704 
705  //Data synchronization barrier
706  __DSB();
707 
708  //Instruct the DMA to poll the transmit descriptor list
709  ENET->TDAR = ENET_TDAR_TDAR_MASK;
710 
711  //Check whether the next buffer is available for writing
712  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
713  {
714  //The transmitter can accept another packet
715  osSetEvent(&interface->nicTxEvent);
716  }
717 
718  //Successful processing
719  return NO_ERROR;
720 }
721 
722 
723 /**
724  * @brief Receive a packet
725  * @param[in] interface Underlying network interface
726  * @return Error code
727  **/
728 
730 {
731  static uint8_t temp[MIMXRT1060_ETH_RX_BUFFER_SIZE];
732  error_t error;
733  size_t n;
734 
735  //Make sure the current buffer is available for reading
736  if(!(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E))
737  {
738  //The frame should not span multiple buffers
739  if(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L)
740  {
741  //Check whether an error occurred
742  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
744  {
745  //Retrieve the length of the frame
746  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
747  //Limit the number of data to read
749 
750  //Copy data from the receive buffer
751  memcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
752 
753  //Pass the packet to the upper layer
754  nicProcessPacket(interface, temp, n);
755 
756  //Valid packet received
757  error = NO_ERROR;
758  }
759  else
760  {
761  //The received packet contains an error
762  error = ERROR_INVALID_PACKET;
763  }
764  }
765  else
766  {
767  //The packet is not valid
768  error = ERROR_INVALID_PACKET;
769  }
770 
771  //Clear BDU flag
772  rxBufferDesc[rxBufferIndex][4] = 0;
773 
774  //Check current index
775  if(rxBufferIndex < (MIMXRT1060_ETH_RX_BUFFER_COUNT - 1))
776  {
777  //Give the ownership of the descriptor back to the DMA engine
778  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
779  //Point to the next buffer
780  rxBufferIndex++;
781  }
782  else
783  {
784  //Give the ownership of the descriptor back to the DMA engine
785  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
786  //Wrap around
787  rxBufferIndex = 0;
788  }
789 
790  //Instruct the DMA to poll the receive descriptor list
791  ENET->RDAR = ENET_RDAR_RDAR_MASK;
792  }
793  else
794  {
795  //No more data in the receive buffer
796  error = ERROR_BUFFER_EMPTY;
797  }
798 
799  //Return status code
800  return error;
801 }
802 
803 
804 /**
805  * @brief Configure MAC address filtering
806  * @param[in] interface Underlying network interface
807  * @return Error code
808  **/
809 
811 {
812  uint_t i;
813  uint_t k;
814  uint32_t crc;
815  uint32_t unicastHashTable[2];
816  uint32_t multicastHashTable[2];
817  MacFilterEntry *entry;
818 
819  //Debug message
820  TRACE_DEBUG("Updating MAC filter...\r\n");
821 
822  //Clear hash table (unicast address filtering)
823  unicastHashTable[0] = 0;
824  unicastHashTable[1] = 0;
825 
826  //Clear hash table (multicast address filtering)
827  multicastHashTable[0] = 0;
828  multicastHashTable[1] = 0;
829 
830  //The MAC address filter contains the list of MAC addresses to accept
831  //when receiving an Ethernet frame
832  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
833  {
834  //Point to the current entry
835  entry = &interface->macAddrFilter[i];
836 
837  //Valid entry?
838  if(entry->refCount > 0)
839  {
840  //Compute CRC over the current MAC address
841  crc = mimxrt1060EthCalcCrc(&entry->addr, sizeof(MacAddr));
842 
843  //The upper 6 bits in the CRC register are used to index the
844  //contents of the hash table
845  k = (crc >> 26) & 0x3F;
846 
847  //Multicast address?
848  if(macIsMulticastAddr(&entry->addr))
849  {
850  //Update the multicast hash table
851  multicastHashTable[k / 32] |= (1 << (k % 32));
852  }
853  else
854  {
855  //Update the unicast hash table
856  unicastHashTable[k / 32] |= (1 << (k % 32));
857  }
858  }
859  }
860 
861  //Write the hash table (unicast address filtering)
862  ENET->IALR = unicastHashTable[0];
863  ENET->IAUR = unicastHashTable[1];
864 
865  //Write the hash table (multicast address filtering)
866  ENET->GALR = multicastHashTable[0];
867  ENET->GAUR = multicastHashTable[1];
868 
869  //Debug message
870  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
871  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
872  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
873  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
874 
875  //Successful processing
876  return NO_ERROR;
877 }
878 
879 
880 /**
881  * @brief Adjust MAC configuration parameters for proper operation
882  * @param[in] interface Underlying network interface
883  * @return Error code
884  **/
885 
887 {
888  //Disable Ethernet MAC while modifying configuration registers
889  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
890 
891  //10BASE-T or 100BASE-TX operation mode?
892  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
893  {
894  //100 Mbps operation
895  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
896  }
897  else
898  {
899  //10 Mbps operation
900  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
901  }
902 
903  //Half-duplex or full-duplex mode?
904  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
905  {
906  //Full-duplex mode
907  ENET->TCR |= ENET_TCR_FDEN_MASK;
908  //Receive path operates independently of transmit
909  ENET->RCR &= ~ENET_RCR_DRT_MASK;
910  }
911  else
912  {
913  //Half-duplex mode
914  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
915  //Disable reception of frames while transmitting
916  ENET->RCR |= ENET_RCR_DRT_MASK;
917  }
918 
919  //Reset buffer descriptors
920  mimxrt1060EthInitBufferDesc(interface);
921 
922  //Re-enable Ethernet MAC
923  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
924  //Instruct the DMA to poll the receive descriptor list
925  ENET->RDAR = ENET_RDAR_RDAR_MASK;
926 
927  //Successful processing
928  return NO_ERROR;
929 }
930 
931 
932 /**
933  * @brief Write PHY register
934  * @param[in] opcode Access type (2 bits)
935  * @param[in] phyAddr PHY address (5 bits)
936  * @param[in] regAddr Register address (5 bits)
937  * @param[in] data Register value
938  **/
939 
940 void mimxrt1060EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
941  uint8_t regAddr, uint16_t data)
942 {
943  uint32_t temp;
944 
945  //Valid opcode?
946  if(opcode == SMI_OPCODE_WRITE)
947  {
948  //Set up a write operation
949  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
950  //PHY address
951  temp |= ENET_MMFR_PA(phyAddr);
952  //Register address
953  temp |= ENET_MMFR_RA(regAddr);
954  //Register value
955  temp |= ENET_MMFR_DATA(data);
956 
957  //Clear MII interrupt flag
958  ENET->EIR = ENET_EIR_MII_MASK;
959  //Start a write operation
960  ENET->MMFR = temp;
961 
962  //Wait for the write to complete
963  while(!(ENET->EIR & ENET_EIR_MII_MASK))
964  {
965  }
966  }
967  else
968  {
969  //The MAC peripheral only supports standard Clause 22 opcodes
970  }
971 }
972 
973 
974 /**
975  * @brief Read PHY register
976  * @param[in] opcode Access type (2 bits)
977  * @param[in] phyAddr PHY address (5 bits)
978  * @param[in] regAddr Register address (5 bits)
979  * @return Register value
980  **/
981 
982 uint16_t mimxrt1060EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
983  uint8_t regAddr)
984 {
985  uint16_t data;
986  uint32_t temp;
987 
988  //Valid opcode?
989  if(opcode == SMI_OPCODE_READ)
990  {
991  //Set up a read operation
992  temp = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
993  //PHY address
994  temp |= ENET_MMFR_PA(phyAddr);
995  //Register address
996  temp |= ENET_MMFR_RA(regAddr);
997 
998  //Clear MII interrupt flag
999  ENET->EIR = ENET_EIR_MII_MASK;
1000  //Start a read operation
1001  ENET->MMFR = temp;
1002 
1003  //Wait for the read to complete
1004  while(!(ENET->EIR & ENET_EIR_MII_MASK))
1005  {
1006  }
1007 
1008  //Get register value
1009  data = ENET->MMFR & ENET_MMFR_DATA_MASK;
1010  }
1011  else
1012  {
1013  //The MAC peripheral only supports standard Clause 22 opcodes
1014  data = 0;
1015  }
1016 
1017  //Return the value of the PHY register
1018  return data;
1019 }
1020 
1021 
1022 /**
1023  * @brief CRC calculation
1024  * @param[in] data Pointer to the data over which to calculate the CRC
1025  * @param[in] length Number of bytes to process
1026  * @return Resulting CRC value
1027  **/
1028 
1029 uint32_t mimxrt1060EthCalcCrc(const void *data, size_t length)
1030 {
1031  uint_t i;
1032  uint_t j;
1033 
1034  //Point to the data over which to calculate the CRC
1035  const uint8_t *p = (uint8_t *) data;
1036  //CRC preset value
1037  uint32_t crc = 0xFFFFFFFF;
1038 
1039  //Loop through data
1040  for(i = 0; i < length; i++)
1041  {
1042  //Update CRC value
1043  crc ^= p[i];
1044  //The message is processed bit by bit
1045  for(j = 0; j < 8; j++)
1046  {
1047  if(crc & 0x00000001)
1048  crc = (crc >> 1) ^ 0xEDB88320;
1049  else
1050  crc = crc >> 1;
1051  }
1052  }
1053 
1054  //Return CRC value
1055  return crc;
1056 }
MacAddr addr
MAC address.
Definition: ethernet.h:222
#define ENET_RBD0_L
#define ENET_RBD0_W
#define ENET_RBD0_OV
#define MIMXRT1060_ETH_IRQ_GROUP_PRIORITY
TCP/IP stack core.
Debugging facilities.
uint8_t p
Definition: ndp.h:298
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
void mimxrt1060EthInitGpio(NetInterface *interface)
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:110
#define ENET_TBD2_INT
#define txBuffer
#define sleep(delay)
Definition: os_port.h:128
#define SMI_OPCODE_READ
Definition: nic.h:63
#define MIMXRT1060_ETH_TX_BUFFER_COUNT
void mimxrt1060EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define MIMXRT1060_ETH_IRQ_SUB_PRIORITY
#define ENET_RBD0_LG
__start_packed struct @108 MacAddr
MAC address.
#define TRUE
Definition: os_port.h:50
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define SMI_OPCODE_WRITE
Definition: nic.h:62
void mimxrt1060EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define ENET_RBD0_E
#define ENET_TBD0_R
#define ENET_RBD0_NO
const NicDriver mimxrt1060EthDriver
i.MX RT1060 Ethernet MAC driver
uint8_t opcode
Definition: dns_common.h:172
uint16_t mimxrt1060EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t mimxrt1060EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t mimxrt1060EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define MIMXRT1060_ETH_IRQ_PRIORITY_GROUPING
#define ENET_TBD0_DATA_LENGTH
i.MX RT1060 Ethernet MAC controller
#define ENET_RBD0_CR
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
NIC driver.
Definition: nic.h:179
error_t mimxrt1060EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MIN(a, b)
Definition: os_port.h:62
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
error_t mimxrt1060EthInit(NetInterface *interface)
i.MX RT1060 Ethernet MAC initialization
#define TRACE_INFO(...)
Definition: debug.h:94
#define ENET_TBD0_TC
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
Ethernet interface.
Definition: nic.h:79
#define ENET_RBD2_INT
Success.
Definition: error.h:44
#define rxBuffer
Ipv6Addr address
void mimxrt1060EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
OsEvent netEvent
Definition: net.c:74
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:223
#define ENET_RBD0_DATA_LENGTH
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
#define MIMXRT1060_ETH_TX_BUFFER_SIZE
unsigned int uint_t
Definition: compiler_port.h:45
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
void ENET_IRQHandler(void)
Ethernet MAC interrupt.
void mimxrt1060EthEventHandler(NetInterface *interface)
i.MX RT1060 Ethernet MAC event handler
uint8_t value[]
Definition: dtls_misc.h:143
#define MIMXRT1060_ETH_RX_BUFFER_COUNT
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:395
void mimxrt1060EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define osExitIsr(flag)
error_t mimxrt1060EthReceivePacket(NetInterface *interface)
Receive a packet.
#define osEnterIsr()
#define ENET_TBD0_L
uint8_t length
Definition: dtls_misc.h:142
uint8_t n
#define ENET_TBD0_W
#define ENET_RBD0_TR
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
#define MIMXRT1060_ETH_RX_BUFFER_SIZE
uint32_t mimxrt1060EthCalcCrc(const void *data, size_t length)
CRC calculation.
void mimxrt1060EthTick(NetInterface *interface)
i.MX RT1060 Ethernet MAC timer handler
MAC filter table entry.
Definition: ethernet.h:220
#define TRACE_DEBUG(...)
Definition: debug.h:106