mimxrt1060_eth_driver.c
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1 /**
2  * @file mimxrt1060_eth_driver.c
3  * @brief i.MX RT1060 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.2
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "fsl_device_registers.h"
36 #include "fsl_gpio.h"
37 #include "fsl_iomuxc.h"
38 #include "core/net.h"
40 #include "debug.h"
41 
42 //Underlying network interface
43 static NetInterface *nicDriverInterface;
44 
45 //IAR EWARM compiler?
46 #if defined(__ICCARM__)
47 
48 //TX buffer
49 #pragma data_alignment = 16
50 #pragma location = ".ram_no_cache"
52 //RX buffer
53 #pragma data_alignment = 16
54 #pragma location = ".ram_no_cache"
56 //TX buffer descriptors
57 #pragma data_alignment = 16
58 #pragma location = ".ram_no_cache"
59 static uint32_t txBufferDesc[MIMXRT1060_ETH_TX_BUFFER_COUNT][8];
60 //RX buffer descriptors
61 #pragma data_alignment = 16
62 #pragma location = ".ram_no_cache"
63 static uint32_t rxBufferDesc[MIMXRT1060_ETH_RX_BUFFER_COUNT][8];
64 
65 //ARM or GCC compiler?
66 #else
67 
68 //TX buffer
70  __attribute__((aligned(16), __section__(".ram_no_cache")));
71 //RX buffer
73  __attribute__((aligned(16), __section__(".ram_no_cache")));
74 //TX buffer descriptors
75 static uint32_t txBufferDesc[MIMXRT1060_ETH_TX_BUFFER_COUNT][8]
76  __attribute__((aligned(16), __section__(".ram_no_cache")));
77 //RX buffer descriptors
78 static uint32_t rxBufferDesc[MIMXRT1060_ETH_RX_BUFFER_COUNT][8]
79  __attribute__((aligned(16), __section__(".ram_no_cache")));
80 
81 #endif
82 
83 //TX buffer index
84 static uint_t txBufferIndex;
85 //RX buffer index
86 static uint_t rxBufferIndex;
87 
88 
89 /**
90  * @brief i.MX RT1060 Ethernet MAC driver
91  **/
92 
94 {
96  ETH_MTU,
107  TRUE,
108  TRUE,
109  TRUE,
110  FALSE
111 };
112 
113 
114 /**
115  * @brief i.MX RT1060 Ethernet MAC initialization
116  * @param[in] interface Underlying network interface
117  * @return Error code
118  **/
119 
121 {
122  error_t error;
123  uint32_t value;
124 
125  //Debug message
126  TRACE_INFO("Initializing i.MX RT1060 Ethernet MAC...\r\n");
127 
128  //Save underlying network interface
129  nicDriverInterface = interface;
130 
131  //Enable ENET peripheral clock
132  CLOCK_EnableClock(kCLOCK_Enet);
133 
134  //GPIO configuration
135  mimxrt1060EthInitGpio(interface);
136 
137  //Reset ENET module
138  ENET->ECR = ENET_ECR_RESET_MASK;
139  //Wait for the reset to complete
140  while(ENET->ECR & ENET_ECR_RESET_MASK);
141 
142  //Receive control register
143  ENET->RCR = ENET_RCR_MAX_FL(MIMXRT1060_ETH_RX_BUFFER_SIZE) |
144  ENET_RCR_RMII_MODE_MASK | ENET_RCR_MII_MODE_MASK;
145 
146  //Transmit control register
147  ENET->TCR = 0;
148  //Configure MDC clock frequency
149  ENET->MSCR = ENET_MSCR_HOLDTIME(10) | ENET_MSCR_MII_SPEED(120);
150 
151  //PHY transceiver initialization
152  error = interface->phyDriver->init(interface);
153  //Failed to initialize PHY transceiver?
154  if(error)
155  return error;
156 
157  //Set the MAC address of the station (upper 16 bits)
158  value = interface->macAddr.b[5];
159  value |= (interface->macAddr.b[4] << 8);
160  ENET->PAUR = ENET_PAUR_PADDR2(value) | ENET_PAUR_TYPE(0x8808);
161 
162  //Set the MAC address of the station (lower 32 bits)
163  value = interface->macAddr.b[3];
164  value |= (interface->macAddr.b[2] << 8);
165  value |= (interface->macAddr.b[1] << 16);
166  value |= (interface->macAddr.b[0] << 24);
167  ENET->PALR = ENET_PALR_PADDR1(value);
168 
169  //Hash table for unicast address filtering
170  ENET->IALR = 0;
171  ENET->IAUR = 0;
172  //Hash table for multicast address filtering
173  ENET->GALR = 0;
174  ENET->GAUR = 0;
175 
176  //Disable transmit accelerator functions
177  ENET->TACC = 0;
178  //Disable receive accelerator functions
179  ENET->RACC = 0;
180 
181  //Use enhanced buffer descriptors
182  ENET->ECR = ENET_ECR_DBSWP_MASK | ENET_ECR_EN1588_MASK;
183  //Clear MIC counters
184  ENET->MIBC = ENET_MIBC_MIB_CLEAR_MASK;
185 
186  //Initialize buffer descriptors
187  mimxrt1060EthInitBufferDesc(interface);
188 
189  //Clear any pending interrupts
190  ENET->EIR = 0xFFFFFFFF;
191  //Enable desired interrupts
192  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
193 
194  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
195  NVIC_SetPriorityGrouping(MIMXRT1060_ETH_IRQ_PRIORITY_GROUPING);
196 
197  //Configure ENET interrupt priority
198  NVIC_SetPriority(ENET_IRQn, NVIC_EncodePriority(MIMXRT1060_ETH_IRQ_PRIORITY_GROUPING,
200 
201  //Enable Ethernet MAC
202  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
203  //Instruct the DMA to poll the receive descriptor list
204  ENET->RDAR = ENET_RDAR_RDAR_MASK;
205 
206  //Accept any packets from the upper layer
207  osSetEvent(&interface->nicTxEvent);
208 
209  //Successful initialization
210  return NO_ERROR;
211 }
212 
213 
214 //MIMXRT1060-EVK or MIMXRT1064-EVK evaluation board?
215 #if defined(USE_MIMXRT1060_EVK) || defined(USE_MIMXRT1064_EVK)
216 
217 /**
218  * @brief GPIO configuration
219  * @param[in] interface Underlying network interface
220  **/
221 
222 void mimxrt1060EthInitGpio(NetInterface *interface)
223 {
224  gpio_pin_config_t pinConfig;
225  clock_enet_pll_config_t pllConfig;
226 
227  //Configure ENET PLL (50MHz)
228  pllConfig.enableClkOutput = true;
229  pllConfig.enableClkOutput25M = false;
230  pllConfig.loopDivider = 1;
231  pllConfig.src = 0;
232  pllConfig.enableClkOutput1 = true;
233  pllConfig.loopDivider1 = 1;
234  CLOCK_InitEnetPll(&pllConfig);
235 
236  //Enable ENET1_TX_CLK output driver
237  IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
238 
239  //Enable IOMUXC clock
240  CLOCK_EnableClock(kCLOCK_Iomuxc);
241 
242  //Configure GPIO_B1_04 pin as ENET_RX_DATA00
243  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
244 
245  //Set GPIO_B1_04 pad properties
246  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00,
247  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
248  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
249  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
250  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
251  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
252  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
253  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
254  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
255 
256  //Configure GPIO_B1_05 pin as ENET_RX_DATA01
257  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
258 
259  //Set GPIO_B1_05 pad properties
260  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01,
261  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
262  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
263  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
264  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
265  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
266  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
267  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
268  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
269 
270  //Configure GPIO_B1_06 pin as ENET_RX_EN
271  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
272 
273  //Set GPIO_B1_06 pad properties
274  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN,
275  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
276  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
277  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
278  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
279  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
280  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
281  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
282  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
283 
284  //Configure GPIO_B1_07 pin as ENET_TX_DATA00
285  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
286 
287  //Set GPIO_B1_07 pad properties
288  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00,
289  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
290  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
291  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
292  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
293  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
294  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
295  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
296  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
297 
298  //Configure GPIO_B1_08 pin as ENET_TX_DATA01
299  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
300 
301  //Set GPIO_B1_08 pad properties
302  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01,
303  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
304  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
305  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
306  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
307  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
308  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
309  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
310  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
311 
312  //Configure GPIO_B1_09 pin as ENET_TX_EN
313  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
314 
315  //Set GPIO_B1_09 pad properties
316  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN,
317  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
318  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
319  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
320  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
321  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
322  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
323  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
324  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
325 
326  //Configure GPIO_B1_10 pin as ENET_REF_CLK
327  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
328 
329  //Set GPIO_B1_10 pad properties
330  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK,
331  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
332  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
333  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
334  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
335  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
336  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
337  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
338  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
339 
340  //Configure GPIO_B1_11 pin as ENET_RX_ER
341  IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
342 
343  //Set GPIO_B1_11 pad properties
344  IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER,
345  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
346  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
347  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
348  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
349  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
350  IOMUXC_SW_PAD_CTL_PAD_SPEED(3) |
351  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
352  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
353 
354  //Configure GPIO_EMC_40 pin as ENET_MDC
355  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
356 
357  //Set GPIO_EMC_40 pad properties
358  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC,
359  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
360  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
361  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
362  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
363  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
364  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
365  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
366  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
367 
368  //Configure GPIO_EMC_41 pin as ENET_MDIO
369  IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
370 
371  //Set GPIO_EMC_41 pad properties
372  IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO,
373  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
374  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
375  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
376  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
377  IOMUXC_SW_PAD_CTL_PAD_ODE(1) |
378  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
379  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
380  IOMUXC_SW_PAD_CTL_PAD_SRE(1));
381 
382  //Configure GPIO_AD_B0_09 pin as GPIO1_IO09
383  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
384 
385  //Set GPIO_AD_B0_09 pad properties
386  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,
387  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
388  IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
389  IOMUXC_SW_PAD_CTL_PAD_PUE(0) |
390  IOMUXC_SW_PAD_CTL_PAD_PKE(0) |
391  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
392  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
393  IOMUXC_SW_PAD_CTL_PAD_DSE(5) |
394  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
395 
396  //Configure GPIO_AD_B0_10 pin as GPIO1_IO10
397  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0);
398 
399  //Set GPIO_AD_B0_10 pad properties
400  IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,
401  IOMUXC_SW_PAD_CTL_PAD_HYS(0) |
402  IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
403  IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
404  IOMUXC_SW_PAD_CTL_PAD_PKE(1) |
405  IOMUXC_SW_PAD_CTL_PAD_ODE(0) |
406  IOMUXC_SW_PAD_CTL_PAD_SPEED(0) |
407  IOMUXC_SW_PAD_CTL_PAD_DSE(0) |
408  IOMUXC_SW_PAD_CTL_PAD_SRE(0));
409 
410  //Configure ENET_RST as an output
411  pinConfig.direction = kGPIO_DigitalOutput;
412  pinConfig.outputLogic = 0;
413  pinConfig.interruptMode = kGPIO_NoIntmode;
414  GPIO_PinInit(GPIO1, 9, &pinConfig);
415 
416  //Configure ENET_INT as an input
417  pinConfig.direction = kGPIO_DigitalInput;
418  pinConfig.outputLogic = 0;
419  pinConfig.interruptMode = kGPIO_NoIntmode;
420  GPIO_PinInit(GPIO1, 10, &pinConfig);
421 
422  //Reset PHY transceiver (hard reset)
423  GPIO_PinWrite(GPIO1, 9, 0);
424  sleep(10);
425  GPIO_PinWrite(GPIO1, 9, 1);
426  sleep(10);
427 }
428 
429 #endif
430 
431 
432 /**
433  * @brief Initialize buffer descriptors
434  * @param[in] interface Underlying network interface
435  **/
436 
438 {
439  uint_t i;
440  uint32_t address;
441 
442  //Clear TX and RX buffer descriptors
443  memset(txBufferDesc, 0, sizeof(txBufferDesc));
444  memset(rxBufferDesc, 0, sizeof(rxBufferDesc));
445 
446  //Initialize TX buffer descriptors
447  for(i = 0; i < MIMXRT1060_ETH_TX_BUFFER_COUNT; i++)
448  {
449  //Calculate the address of the current TX buffer
450  address = (uint32_t) txBuffer[i];
451  //Transmit buffer address
452  txBufferDesc[i][1] = address;
453  //Generate interrupts
454  txBufferDesc[i][2] = ENET_TBD2_INT;
455  }
456 
457  //Mark the last descriptor entry with the wrap flag
458  txBufferDesc[i - 1][0] |= ENET_TBD0_W;
459  //Initialize TX buffer index
460  txBufferIndex = 0;
461 
462  //Initialize RX buffer descriptors
463  for(i = 0; i < MIMXRT1060_ETH_RX_BUFFER_COUNT; i++)
464  {
465  //Calculate the address of the current RX buffer
466  address = (uint32_t) rxBuffer[i];
467  //The descriptor is initially owned by the DMA
468  rxBufferDesc[i][0] = ENET_RBD0_E;
469  //Receive buffer address
470  rxBufferDesc[i][1] = address;
471  //Generate interrupts
472  rxBufferDesc[i][2] = ENET_RBD2_INT;
473  }
474 
475  //Mark the last descriptor entry with the wrap flag
476  rxBufferDesc[i - 1][0] |= ENET_RBD0_W;
477  //Initialize RX buffer index
478  rxBufferIndex = 0;
479 
480  //Start location of the TX descriptor list
481  ENET->TDSR = (uint32_t) txBufferDesc;
482  //Start location of the RX descriptor list
483  ENET->RDSR = (uint32_t) rxBufferDesc;
484  //Maximum receive buffer size
485  ENET->MRBR = MIMXRT1060_ETH_RX_BUFFER_SIZE;
486 }
487 
488 
489 /**
490  * @brief i.MX RT1060 Ethernet MAC timer handler
491  *
492  * This routine is periodically called by the TCP/IP stack to
493  * handle periodic operations such as polling the link state
494  *
495  * @param[in] interface Underlying network interface
496  **/
497 
499 {
500  //Handle periodic operations
501  interface->phyDriver->tick(interface);
502 }
503 
504 
505 /**
506  * @brief Enable interrupts
507  * @param[in] interface Underlying network interface
508  **/
509 
511 {
512  //Enable Ethernet MAC interrupts
513  NVIC_EnableIRQ(ENET_IRQn);
514  //Enable Ethernet PHY interrupts
515  interface->phyDriver->enableIrq(interface);
516 }
517 
518 
519 /**
520  * @brief Disable interrupts
521  * @param[in] interface Underlying network interface
522  **/
523 
525 {
526  //Disable Ethernet MAC interrupts
527  NVIC_DisableIRQ(ENET_IRQn);
528  //Disable Ethernet PHY interrupts
529  interface->phyDriver->disableIrq(interface);
530 }
531 
532 
533 /**
534  * @brief Ethernet MAC interrupt
535  **/
536 
537 void ENET_IRQHandler(void)
538 {
539  bool_t flag;
540  uint32_t events;
541 
542  //Enter interrupt service routine
543  osEnterIsr();
544 
545  //This flag will be set if a higher priority task must be woken
546  flag = FALSE;
547  //Read interrupt event register
548  events = ENET->EIR;
549 
550  //A packet has been transmitted?
551  if(events & ENET_EIR_TXF_MASK)
552  {
553  //Clear TXF interrupt flag
554  ENET->EIR = ENET_EIR_TXF_MASK;
555 
556  //Check whether the TX buffer is available for writing
557  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
558  {
559  //Notify the TCP/IP stack that the transmitter is ready to send
560  flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
561  }
562 
563  //Instruct the DMA to poll the transmit descriptor list
564  ENET->TDAR = ENET_TDAR_TDAR_MASK;
565  }
566 
567  //A packet has been received?
568  if(events & ENET_EIR_RXF_MASK)
569  {
570  //Disable RXF interrupt
571  ENET->EIMR &= ~ENET_EIMR_RXF_MASK;
572 
573  //Set event flag
574  nicDriverInterface->nicEvent = TRUE;
575  //Notify the TCP/IP stack of the event
576  flag = osSetEventFromIsr(&netEvent);
577  }
578 
579  //System bus error?
580  if(events & ENET_EIR_EBERR_MASK)
581  {
582  //Disable EBERR interrupt
583  ENET->EIMR &= ~ENET_EIMR_EBERR_MASK;
584 
585  //Set event flag
586  nicDriverInterface->nicEvent = TRUE;
587  //Notify the TCP/IP stack of the event
588  flag |= osSetEventFromIsr(&netEvent);
589  }
590 
591  //Leave interrupt service routine
592  osExitIsr(flag);
593 }
594 
595 
596 /**
597  * @brief i.MX RT1060 Ethernet MAC event handler
598  * @param[in] interface Underlying network interface
599  **/
600 
602 {
603  error_t error;
604  uint32_t status;
605 
606  //Read interrupt event register
607  status = ENET->EIR;
608 
609  //Packet received?
610  if(status & ENET_EIR_RXF_MASK)
611  {
612  //Clear RXF interrupt flag
613  ENET->EIR = ENET_EIR_RXF_MASK;
614 
615  //Process all pending packets
616  do
617  {
618  //Read incoming packet
619  error = mimxrt1060EthReceivePacket(interface);
620 
621  //No more data in the receive buffer?
622  } while(error != ERROR_BUFFER_EMPTY);
623  }
624 
625  //System bus error?
626  if(status & ENET_EIR_EBERR_MASK)
627  {
628  //Clear EBERR interrupt flag
629  ENET->EIR = ENET_EIR_EBERR_MASK;
630 
631  //Disable Ethernet MAC
632  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
633  //Reset buffer descriptors
634  mimxrt1060EthInitBufferDesc(interface);
635  //Resume normal operation
636  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
637  //Instruct the DMA to poll the receive descriptor list
638  ENET->RDAR = ENET_RDAR_RDAR_MASK;
639  }
640 
641  //Re-enable Ethernet MAC interrupts
642  ENET->EIMR = ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK;
643 }
644 
645 
646 /**
647  * @brief Send a packet
648  * @param[in] interface Underlying network interface
649  * @param[in] buffer Multi-part buffer containing the data to send
650  * @param[in] offset Offset to the first data byte
651  * @return Error code
652  **/
653 
655  const NetBuffer *buffer, size_t offset)
656 {
657  static uint8_t temp[MIMXRT1060_ETH_TX_BUFFER_SIZE];
658  size_t length;
659 
660  //Retrieve the length of the packet
661  length = netBufferGetLength(buffer) - offset;
662 
663  //Check the frame length
665  {
666  //The transmitter can accept another packet
667  osSetEvent(&interface->nicTxEvent);
668  //Report an error
669  return ERROR_INVALID_LENGTH;
670  }
671 
672  //Make sure the current buffer is available for writing
673  if(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R)
674  return ERROR_FAILURE;
675 
676  //Copy user data to the transmit buffer
677  netBufferRead(temp, buffer, offset, length);
678  memcpy(txBuffer[txBufferIndex], temp, (length + 3) & ~3UL);
679 
680  //Clear BDU flag
681  txBufferDesc[txBufferIndex][4] = 0;
682 
683  //Check current index
684  if(txBufferIndex < (MIMXRT1060_ETH_TX_BUFFER_COUNT - 1))
685  {
686  //Give the ownership of the descriptor to the DMA engine
687  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_L |
689 
690  //Point to the next buffer
691  txBufferIndex++;
692  }
693  else
694  {
695  //Give the ownership of the descriptor to the DMA engine
696  txBufferDesc[txBufferIndex][0] = ENET_TBD0_R | ENET_TBD0_W |
698 
699  //Wrap around
700  txBufferIndex = 0;
701  }
702 
703  //Data synchronization barrier
704  __DSB();
705 
706  //Instruct the DMA to poll the transmit descriptor list
707  ENET->TDAR = ENET_TDAR_TDAR_MASK;
708 
709  //Check whether the next buffer is available for writing
710  if(!(txBufferDesc[txBufferIndex][0] & ENET_TBD0_R))
711  {
712  //The transmitter can accept another packet
713  osSetEvent(&interface->nicTxEvent);
714  }
715 
716  //Successful processing
717  return NO_ERROR;
718 }
719 
720 
721 /**
722  * @brief Receive a packet
723  * @param[in] interface Underlying network interface
724  * @return Error code
725  **/
726 
728 {
729  static uint8_t temp[MIMXRT1060_ETH_RX_BUFFER_SIZE];
730  error_t error;
731  size_t n;
732 
733  //Make sure the current buffer is available for reading
734  if(!(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_E))
735  {
736  //The frame should not span multiple buffers
737  if(rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_L)
738  {
739  //Check whether an error occurred
740  if(!(rxBufferDesc[rxBufferIndex][0] & (ENET_RBD0_LG |
742  {
743  //Retrieve the length of the frame
744  n = rxBufferDesc[rxBufferIndex][0] & ENET_RBD0_DATA_LENGTH;
745  //Limit the number of data to read
747 
748  //Copy data from the receive buffer
749  memcpy(temp, rxBuffer[rxBufferIndex], (n + 3) & ~3UL);
750 
751  //Pass the packet to the upper layer
752  nicProcessPacket(interface, temp, n);
753 
754  //Valid packet received
755  error = NO_ERROR;
756  }
757  else
758  {
759  //The received packet contains an error
760  error = ERROR_INVALID_PACKET;
761  }
762  }
763  else
764  {
765  //The packet is not valid
766  error = ERROR_INVALID_PACKET;
767  }
768 
769  //Clear BDU flag
770  rxBufferDesc[rxBufferIndex][4] = 0;
771 
772  //Check current index
773  if(rxBufferIndex < (MIMXRT1060_ETH_RX_BUFFER_COUNT - 1))
774  {
775  //Give the ownership of the descriptor back to the DMA engine
776  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E;
777  //Point to the next buffer
778  rxBufferIndex++;
779  }
780  else
781  {
782  //Give the ownership of the descriptor back to the DMA engine
783  rxBufferDesc[rxBufferIndex][0] = ENET_RBD0_E | ENET_RBD0_W;
784  //Wrap around
785  rxBufferIndex = 0;
786  }
787 
788  //Instruct the DMA to poll the receive descriptor list
789  ENET->RDAR = ENET_RDAR_RDAR_MASK;
790  }
791  else
792  {
793  //No more data in the receive buffer
794  error = ERROR_BUFFER_EMPTY;
795  }
796 
797  //Return status code
798  return error;
799 }
800 
801 
802 /**
803  * @brief Configure MAC address filtering
804  * @param[in] interface Underlying network interface
805  * @return Error code
806  **/
807 
809 {
810  uint_t i;
811  uint_t k;
812  uint32_t crc;
813  uint32_t unicastHashTable[2];
814  uint32_t multicastHashTable[2];
815  MacFilterEntry *entry;
816 
817  //Debug message
818  TRACE_DEBUG("Updating MAC filter...\r\n");
819 
820  //Clear hash table (unicast address filtering)
821  unicastHashTable[0] = 0;
822  unicastHashTable[1] = 0;
823 
824  //Clear hash table (multicast address filtering)
825  multicastHashTable[0] = 0;
826  multicastHashTable[1] = 0;
827 
828  //The MAC address filter contains the list of MAC addresses to accept
829  //when receiving an Ethernet frame
830  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
831  {
832  //Point to the current entry
833  entry = &interface->macAddrFilter[i];
834 
835  //Valid entry?
836  if(entry->refCount > 0)
837  {
838  //Compute CRC over the current MAC address
839  crc = mimxrt1060EthCalcCrc(&entry->addr, sizeof(MacAddr));
840 
841  //The upper 6 bits in the CRC register are used to index the
842  //contents of the hash table
843  k = (crc >> 26) & 0x3F;
844 
845  //Multicast address?
846  if(macIsMulticastAddr(&entry->addr))
847  {
848  //Update the multicast hash table
849  multicastHashTable[k / 32] |= (1 << (k % 32));
850  }
851  else
852  {
853  //Update the unicast hash table
854  unicastHashTable[k / 32] |= (1 << (k % 32));
855  }
856  }
857  }
858 
859  //Write the hash table (unicast address filtering)
860  ENET->IALR = unicastHashTable[0];
861  ENET->IAUR = unicastHashTable[1];
862 
863  //Write the hash table (multicast address filtering)
864  ENET->GALR = multicastHashTable[0];
865  ENET->GAUR = multicastHashTable[1];
866 
867  //Debug message
868  TRACE_DEBUG(" IALR = %08" PRIX32 "\r\n", ENET->IALR);
869  TRACE_DEBUG(" IAUR = %08" PRIX32 "\r\n", ENET->IAUR);
870  TRACE_DEBUG(" GALR = %08" PRIX32 "\r\n", ENET->GALR);
871  TRACE_DEBUG(" GAUR = %08" PRIX32 "\r\n", ENET->GAUR);
872 
873  //Successful processing
874  return NO_ERROR;
875 }
876 
877 
878 /**
879  * @brief Adjust MAC configuration parameters for proper operation
880  * @param[in] interface Underlying network interface
881  * @return Error code
882  **/
883 
885 {
886  //Disable Ethernet MAC while modifying configuration registers
887  ENET->ECR &= ~ENET_ECR_ETHEREN_MASK;
888 
889  //10BASE-T or 100BASE-TX operation mode?
890  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
891  {
892  //100 Mbps operation
893  ENET->RCR &= ~ENET_RCR_RMII_10T_MASK;
894  }
895  else
896  {
897  //10 Mbps operation
898  ENET->RCR |= ENET_RCR_RMII_10T_MASK;
899  }
900 
901  //Half-duplex or full-duplex mode?
902  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
903  {
904  //Full-duplex mode
905  ENET->TCR |= ENET_TCR_FDEN_MASK;
906  //Receive path operates independently of transmit
907  ENET->RCR &= ~ENET_RCR_DRT_MASK;
908  }
909  else
910  {
911  //Half-duplex mode
912  ENET->TCR &= ~ENET_TCR_FDEN_MASK;
913  //Disable reception of frames while transmitting
914  ENET->RCR |= ENET_RCR_DRT_MASK;
915  }
916 
917  //Reset buffer descriptors
918  mimxrt1060EthInitBufferDesc(interface);
919 
920  //Re-enable Ethernet MAC
921  ENET->ECR |= ENET_ECR_ETHEREN_MASK;
922  //Instruct the DMA to poll the receive descriptor list
923  ENET->RDAR = ENET_RDAR_RDAR_MASK;
924 
925  //Successful processing
926  return NO_ERROR;
927 }
928 
929 
930 /**
931  * @brief Write PHY register
932  * @param[in] phyAddr PHY address
933  * @param[in] regAddr Register address
934  * @param[in] data Register value
935  **/
936 
937 void mimxrt1060EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
938 {
939  uint32_t value;
940 
941  //Set up a write operation
942  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(1) | ENET_MMFR_TA(2);
943  //PHY address
944  value |= ENET_MMFR_PA(phyAddr);
945  //Register address
946  value |= ENET_MMFR_RA(regAddr);
947  //Register value
948  value |= ENET_MMFR_DATA(data);
949 
950  //Clear MII interrupt flag
951  ENET->EIR = ENET_EIR_MII_MASK;
952  //Start a write operation
953  ENET->MMFR = value;
954  //Wait for the write to complete
955  while(!(ENET->EIR & ENET_EIR_MII_MASK));
956 }
957 
958 
959 /**
960  * @brief Read PHY register
961  * @param[in] phyAddr PHY address
962  * @param[in] regAddr Register address
963  * @return Register value
964  **/
965 
966 uint16_t mimxrt1060EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
967 {
968  uint32_t value;
969 
970  //Set up a read operation
971  value = ENET_MMFR_ST(1) | ENET_MMFR_OP(2) | ENET_MMFR_TA(2);
972  //PHY address
973  value |= ENET_MMFR_PA(phyAddr);
974  //Register address
975  value |= ENET_MMFR_RA(regAddr);
976 
977  //Clear MII interrupt flag
978  ENET->EIR = ENET_EIR_MII_MASK;
979  //Start a read operation
980  ENET->MMFR = value;
981  //Wait for the read to complete
982  while(!(ENET->EIR & ENET_EIR_MII_MASK));
983 
984  //Return PHY register contents
985  return ENET->MMFR & ENET_MMFR_DATA_MASK;
986 }
987 
988 
989 /**
990  * @brief CRC calculation
991  * @param[in] data Pointer to the data over which to calculate the CRC
992  * @param[in] length Number of bytes to process
993  * @return Resulting CRC value
994  **/
995 
996 uint32_t mimxrt1060EthCalcCrc(const void *data, size_t length)
997 {
998  uint_t i;
999  uint_t j;
1000 
1001  //Point to the data over which to calculate the CRC
1002  const uint8_t *p = (uint8_t *) data;
1003  //CRC preset value
1004  uint32_t crc = 0xFFFFFFFF;
1005 
1006  //Loop through data
1007  for(i = 0; i < length; i++)
1008  {
1009  //Update CRC value
1010  crc ^= p[i];
1011  //The message is processed bit by bit
1012  for(j = 0; j < 8; j++)
1013  {
1014  if(crc & 0x00000001)
1015  crc = (crc >> 1) ^ 0xEDB88320;
1016  else
1017  crc = crc >> 1;
1018  }
1019  }
1020 
1021  //Return CRC value
1022  return crc;
1023 }
MacAddr addr
MAC address.
Definition: ethernet.h:219
#define ENET_RBD0_L
#define ENET_RBD0_W
#define ENET_RBD0_OV
#define MIMXRT1060_ETH_IRQ_GROUP_PRIORITY
TCP/IP stack core.
void mimxrt1060EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Debugging facilities.
uint8_t p
Definition: ndp.h:297
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
void mimxrt1060EthInitGpio(NetInterface *interface)
Generic error code.
Definition: error.h:45
#define macIsMulticastAddr(macAddr)
Definition: ethernet.h:107
#define ENET_TBD2_INT
#define txBuffer
uint16_t mimxrt1060EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define sleep(delay)
Definition: os_port.h:128
#define MIMXRT1060_ETH_TX_BUFFER_COUNT
#define MIMXRT1060_ETH_IRQ_SUB_PRIORITY
#define ENET_RBD0_LG
#define TRUE
Definition: os_port.h:50
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
void mimxrt1060EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define ENET_RBD0_E
#define ENET_TBD0_R
#define ENET_RBD0_NO
const NicDriver mimxrt1060EthDriver
i.MX RT1060 Ethernet MAC driver
error_t mimxrt1060EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t mimxrt1060EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define MIMXRT1060_ETH_IRQ_PRIORITY_GROUPING
#define ENET_TBD0_DATA_LENGTH
i.MX RT1060 Ethernet MAC controller
#define ENET_RBD0_CR
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
NIC driver.
Definition: nic.h:164
error_t mimxrt1060EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define MIN(a, b)
Definition: os_port.h:62
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
error_t mimxrt1060EthInit(NetInterface *interface)
i.MX RT1060 Ethernet MAC initialization
#define TRACE_INFO(...)
Definition: debug.h:94
#define ENET_TBD0_TC
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:91
Ethernet interface.
Definition: nic.h:71
#define ENET_RBD2_INT
Success.
Definition: error.h:44
#define rxBuffer
Ipv6Addr address
void mimxrt1060EthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
OsEvent netEvent
Definition: net.c:73
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:220
#define ENET_RBD0_DATA_LENGTH
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
#define MIMXRT1060_ETH_TX_BUFFER_SIZE
unsigned int uint_t
Definition: compiler_port.h:45
__start_packed struct @112 MacAddr
MAC address.
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
void ENET_IRQHandler(void)
Ethernet MAC interrupt.
void mimxrt1060EthEventHandler(NetInterface *interface)
i.MX RT1060 Ethernet MAC event handler
uint8_t value[]
Definition: dtls_misc.h:143
#define MIMXRT1060_ETH_RX_BUFFER_COUNT
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:395
void mimxrt1060EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define osExitIsr(flag)
error_t mimxrt1060EthReceivePacket(NetInterface *interface)
Receive a packet.
#define osEnterIsr()
#define ENET_TBD0_L
uint8_t length
Definition: dtls_misc.h:142
uint8_t n
#define ENET_TBD0_W
#define ENET_RBD0_TR
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
#define MIMXRT1060_ETH_RX_BUFFER_SIZE
uint32_t mimxrt1060EthCalcCrc(const void *data, size_t length)
CRC calculation.
void mimxrt1060EthTick(NetInterface *interface)
i.MX RT1060 Ethernet MAC timer handler
MAC filter table entry.
Definition: ethernet.h:217
#define TRACE_DEBUG(...)
Definition: debug.h:106