rtl8211_driver.h
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1 /**
2  * @file rtl8211_driver.h
3  * @brief RTL8211 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _RTL8211_DRIVER_H
30 #define _RTL8211_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef RTL8211_PHY_ADDR
37  #define RTL8211_PHY_ADDR 1
38 #elif (RTL8211_PHY_ADDR < 0 || RTL8211_PHY_ADDR > 31)
39  #error RTL8211_PHY_ADDR parameter is not valid
40 #endif
41 
42 //RTL8211 registers
43 #define RTL8211_PHY_REG_BMCR 0x00
44 #define RTL8211_PHY_REG_BMSR 0x01
45 #define RTL8211_PHY_REG_PHYIDR1 0x02
46 #define RTL8211_PHY_REG_PHYIDR2 0x03
47 #define RTL8211_PHY_REG_ANAR 0x04
48 #define RTL8211_PHY_REG_ANLPAR 0x05
49 #define RTL8211_PHY_REG_ANER 0x06
50 #define RTL8211_PHY_REG_ANNPRR 0x07
51 #define RTL8211_PHY_REG_LPNPAR 0x08
52 #define RTL8211_PHY_REG_GBCR 0x09
53 #define RTL8211_PHY_REG_GBSR 0x0A
54 #define RTL8211_PHY_REG_MACR 0x0D
55 #define RTL8211_PHY_REG_MAADR 0x0E
56 #define RTL8211_PHY_REG_GBESR 0x0F
57 #define RTL8211_PHY_REG_PHYCR 0x10
58 #define RTL8211_PHY_REG_PHYSR 0x11
59 #define RTL8211_PHY_REG_INER 0x12
60 #define RTL8211_PHY_REG_INSR 0x13
61 #define RTL8211_PHY_REG_RXERC 0x18
62 #define RTL8211_PHY_REG_LDPSR 0x1B
63 #define RTL8211_PHY_REG_EPAGSR 0x1E
64 #define RTL8211_PHY_REG_PAGSEL 0x1F
65 
66 //BMCR register
67 #define BMCR_RESET (1 << 15)
68 #define BMCR_LOOPBACK (1 << 14)
69 #define BMCR_SPEED_SEL (1 << 13)
70 #define BMCR_AN_EN (1 << 12)
71 #define BMCR_POWER_DOWN (1 << 11)
72 #define BMCR_ISOLATE (1 << 10)
73 #define BMCR_RESTART_AN (1 << 9)
74 #define BMCR_DUPLEX_MODE (1 << 8)
75 #define BMCR_COL_TEST (1 << 7)
76 
77 //BMSR register
78 #define BMSR_100BT4 (1 << 15)
79 #define BMSR_100BTX_FD (1 << 14)
80 #define BMSR_100BTX (1 << 13)
81 #define BMSR_10BT_FD (1 << 12)
82 #define BMSR_10BT (1 << 11)
83 #define BMSR_NO_PREAMBLE (1 << 6)
84 #define BMSR_AN_COMPLETE (1 << 5)
85 #define BMSR_REMOTE_FAULT (1 << 4)
86 #define BMSR_AN_ABLE (1 << 3)
87 #define BMSR_LINK_STATUS (1 << 2)
88 #define BMSR_JABBER_DETECT (1 << 1)
89 #define BMSR_EXTENDED_CAP (1 << 0)
90 
91 //ANAR register
92 #define ANAR_NEXT_PAGE (1 << 15)
93 #define ANAR_REMOTE_FAULT (1 << 13)
94 #define ANAR_PAUSE1 (1 << 11)
95 #define ANAR_PAUSE0 (1 << 10)
96 #define ANAR_100BT4 (1 << 9)
97 #define ANAR_100BTX_FD (1 << 8)
98 #define ANAR_100BTX (1 << 7)
99 #define ANAR_10BT_FD (1 << 6)
100 #define ANAR_10BT (1 << 5)
101 #define ANAR_SELECTOR4 (1 << 4)
102 #define ANAR_SELECTOR3 (1 << 3)
103 #define ANAR_SELECTOR2 (1 << 2)
104 #define ANAR_SELECTOR1 (1 << 1)
105 #define ANAR_SELECTOR0 (1 << 0)
106 
107 //ANLPAR register
108 #define ANLPAR_NEXT_PAGE (1 << 15)
109 #define ANLPAR_LP_ACK (1 << 14)
110 #define ANLPAR_REMOTE_FAULT (1 << 13)
111 #define ANLPAR_PAUSE1 (1 << 11)
112 #define ANLPAR_PAUSE0 (1 << 10)
113 #define ANLPAR_100BT4 (1 << 9)
114 #define ANLPAR_100BTX_FD (1 << 8)
115 #define ANLPAR_100BTX (1 << 7)
116 #define ANLPAR_10BT_FD (1 << 6)
117 #define ANLPAR_10BT (1 << 5)
118 #define ANLPAR_SELECTOR4 (1 << 4)
119 #define ANLPAR_SELECTOR3 (1 << 3)
120 #define ANLPAR_SELECTOR2 (1 << 2)
121 #define ANLPAR_SELECTOR1 (1 << 1)
122 #define ANLPAR_SELECTOR0 (1 << 0)
123 
124 //ANER register
125 #define ANER_PAR_DET_FAULT (1 << 4)
126 #define ANER_LP_NEXT_PAGE_ABLE (1 << 3)
127 #define ANER_NEXT_PAGE_ABLE (1 << 2)
128 #define ANER_PAGE_RECEIVED (1 << 1)
129 #define ANER_LP_AN_ABLE (1 << 0)
130 
131 //ANNPTR register
132 #define ANNPTR_NEXT_PAGE (1 << 15)
133 #define ANNPTR_MSG_PAGE (1 << 13)
134 #define ANNPTR_ACK2 (1 << 12)
135 #define ANNPTR_TOGGLE (1 << 11)
136 #define ANNPTR_MESSAGE10 (1 << 10)
137 #define ANNPTR_MESSAGE9 (1 << 9)
138 #define ANNPTR_MESSAGE8 (1 << 8)
139 #define ANNPTR_MESSAGE7 (1 << 7)
140 #define ANNPTR_MESSAGE6 (1 << 6)
141 #define ANNPTR_MESSAGE5 (1 << 5)
142 #define ANNPTR_MESSAGE4 (1 << 4)
143 #define ANNPTR_MESSAGE3 (1 << 3)
144 #define ANNPTR_MESSAGE2 (1 << 2)
145 #define ANNPTR_MESSAGE1 (1 << 1)
146 #define ANNPTR_MESSAGE0 (1 << 0)
147 
148 //ANNPRR register
149 #define ANNPRR_NEXT_PAGE (1 << 15)
150 #define ANNPRR_ACK (1 << 14)
151 #define ANNPRR_MSG_PAGE (1 << 13)
152 #define ANNPRR_ACK2 (1 << 12)
153 #define ANNPRR_TOGGLE (1 << 11)
154 #define ANNPRR_MESSAGE10 (1 << 10)
155 #define ANNPRR_MESSAGE9 (1 << 9)
156 #define ANNPRR_MESSAGE8 (1 << 8)
157 #define ANNPRR_MESSAGE7 (1 << 7)
158 #define ANNPRR_MESSAGE6 (1 << 6)
159 #define ANNPRR_MESSAGE5 (1 << 5)
160 #define ANNPRR_MESSAGE4 (1 << 4)
161 #define ANNPRR_MESSAGE3 (1 << 3)
162 #define ANNPRR_MESSAGE2 (1 << 2)
163 #define ANNPRR_MESSAGE1 (1 << 1)
164 #define ANNPRR_MESSAGE0 (1 << 0)
165 
166 //GBCR register
167 #define GBCR_TEST_MODE2 (1 << 15)
168 #define GBCR_TEST_MODE1 (1 << 14)
169 #define GBCR_TEST_MODE0 (1 << 13)
170 #define GBCR_MS_MAN_CONF_EN (1 << 12)
171 #define GBCR_MS_MAN_CONF_VAL (1 << 11)
172 #define GBCR_PORT_TYPE (1 << 10)
173 #define GBCR_1000BT_FD (1 << 9)
174 #define GBCR_1000BT_HD (1 << 8)
175 
176 //GBSR register
177 #define GBSR_MS_CONF_FAULT (1 << 15)
178 #define GBSR_MS_CONF_RES (1 << 14)
179 #define GBSR_LOC_REC_STATUS (1 << 13)
180 #define GBSR_REM_REC_STATUS (1 << 12)
181 #define GBSR_LP_1000BT_FD (1 << 11)
182 #define GBSR_LP_1000BT_HD (1 << 10)
183 #define GBSR_IDLE_ERR_CTR7 (1 << 7)
184 #define GBSR_IDLE_ERR_CTR6 (1 << 6)
185 #define GBSR_IDLE_ERR_CTR5 (1 << 5)
186 #define GBSR_IDLE_ERR_CTR4 (1 << 4)
187 #define GBSR_IDLE_ERR_CTR3 (1 << 3)
188 #define GBSR_IDLE_ERR_CTR2 (1 << 2)
189 #define GBSR_IDLE_ERR_CTR1 (1 << 1)
190 #define GBSR_IDLE_ERR_CTR0 (1 << 0)
191 
192 //MACR register
193 #define MACR_FUNCTION1 (1 << 15)
194 #define MACR_FUNCTION0 (1 << 14)
195 #define MACR_DEVAD4 (1 << 4)
196 #define MACR_DEVAD3 (1 << 3)
197 #define MACR_DEVAD2 (1 << 2)
198 #define MACR_DEVAD1 (1 << 1)
199 #define MACR_DEVAD0 (1 << 0)
200 
201 //GBESR register
202 #define GBESR_1000BX_FD (1 << 15)
203 #define GBESR_1000BX_HD (1 << 14)
204 #define GBESR_1000BT_FD (1 << 13)
205 #define GBESR_1000BT_HD (1 << 12)
206 
207 //PHYCR register
208 #define PHYCR_DISABLE_RXC (1 << 15)
209 #define PHYCR_FPR_FAIL_SEL2 (1 << 14)
210 #define PHYCR_FPR_FAIL_SEL1 (1 << 13)
211 #define PHYCR_FPR_FAIL_SEL0 (1 << 12)
212 #define PHYCR_ASSERT_CRS_ON_TX (1 << 11)
213 #define PHYCR_FORCE_LINK_GOOD (1 << 10)
214 #define PHYCR_ENABLE_CROSSOVER (1 << 6)
215 #define PHYCR_MDI_MODE (1 << 5)
216 #define PHYCR_DISABLE CLK125 (1 << 4)
217 #define PHYCR_DISABLE_JABBER (1 << 0)
218 
219 //PHYSR register
220 #define PHYSR_SPEED1 (1 << 15)
221 #define PHYSR_SPEED0 (1 << 14)
222 #define PHYSR_DUPLEX (1 << 13)
223 #define PHYSR_PAGE_RECEIVED (1 << 12)
224 #define PHYSR_SPEED_DUPLEX_RESOLVED (1 << 11)
225 #define PHYSR_LINK (1 << 10)
226 #define PHYSR_MDI_CROSSOVER_STATUS (1 << 6)
227 #define PHYSR_RE_LINK_OK (1 << 1)
228 #define PHYSR_JABBER (1 << 0)
229 
230 //Speed
231 #define PHYSR_SPEED_MASK (3 << 14)
232 #define PHYSR_SPEED_10 (0 << 14)
233 #define PHYSR_SPEED_100 (1 << 14)
234 #define PHYSR_SPEED_1000 (2 << 14)
235 
236 //INER register
237 #define INER_AN_ERROR (1 << 15)
238 #define INER_PAGE_RECEIVED (1 << 12)
239 #define INER_AN_COMPLETE (1 << 11)
240 #define INER_LINK_STATUS (1 << 10)
241 #define INER_SYMBOL_ERROR (1 << 9)
242 #define INER_FALSE_CARRIER (1 << 8)
243 #define INER_JABBER (1 << 0)
244 
245 //INSR register
246 #define INSR_AN_ERROR (1 << 15)
247 #define INSR_PAGE_RECEIVED (1 << 12)
248 #define INSR_AN_COMPLETE (1 << 11)
249 #define INSR_LINK_STATUS (1 << 10)
250 #define INSR_SYMBOL_ERROR (1 << 9)
251 #define INSR_FALSE_CARRIER (1 << 8)
252 #define INSR_JABBER (1 << 0)
253 
254 //LDPSR register
255 #define LDPSR_POWER_SAVE_MODE (1 << 0)
256 
257 //EPAGSR register
258 #define EPAGSR_EXT_PAGE_SEL7 (1 << 7)
259 #define EPAGSR_EXT_PAGE_SEL6 (1 << 6)
260 #define EPAGSR_EXT_PAGE_SEL5 (1 << 5)
261 #define EPAGSR_EXT_PAGE_SEL4 (1 << 4)
262 #define EPAGSR_EXT_PAGE_SEL3 (1 << 3)
263 #define EPAGSR_EXT_PAGE_SEL2 (1 << 2)
264 #define EPAGSR_EXT_PAGE_SEL1 (1 << 1)
265 #define EPAGSR_EXT_PAGE_SEL0 (1 << 0)
266 
267 //PAGSEL register
268 #define PAGSEL_PAGE_SEL2 (1 << 2)
269 #define PAGSEL_PAGE_SEL1 (1 << 1)
270 #define PAGSEL_PAGE_SEL0 (1 << 0)
271 
272 //C++ guard
273 #ifdef __cplusplus
274  extern "C" {
275 #endif
276 
277 //RTL8211 Ethernet PHY driver
278 extern const PhyDriver rtl8211PhyDriver;
279 
280 //RTL8211 related functions
281 error_t rtl8211Init(NetInterface *interface);
282 
283 void rtl8211Tick(NetInterface *interface);
284 
285 void rtl8211EnableIrq(NetInterface *interface);
286 void rtl8211DisableIrq(NetInterface *interface);
287 
288 void rtl8211EventHandler(NetInterface *interface);
289 
290 void rtl8211WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
291 uint16_t rtl8211ReadPhyReg(NetInterface *interface, uint8_t address);
292 
293 void rtl8211DumpPhyReg(NetInterface *interface);
294 
295 //C++ guard
296 #ifdef __cplusplus
297  }
298 #endif
299 
300 #endif
void rtl8211WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
void rtl8211EventHandler(NetInterface *interface)
RTL8211 event handler.
error_t rtl8211Init(NetInterface *interface)
RTL8211 PHY transceiver initialization.
const PhyDriver rtl8211PhyDriver
RTL8211 Ethernet PHY driver.
void rtl8211DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
PHY driver.
Definition: nic.h:196
void rtl8211EnableIrq(NetInterface *interface)
Enable interrupts.
void rtl8211DisableIrq(NetInterface *interface)
Disable interrupts.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void rtl8211Tick(NetInterface *interface)
RTL8211 timer handler.
uint16_t rtl8211ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
Network interface controller abstraction layer.