s7g2_eth_driver.c
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1 /**
2  * @file s7g2_eth_driver.c
3  * @brief Renesas Synergy S7G2 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "bsp_irq_cfg.h"
36 #include "s7g2.h"
37 #include "core/net.h"
39 #include "debug.h"
40 
41 //Underlying network interface
42 static NetInterface *nicDriverInterface;
43 
44 //IAR EWARM compiler?
45 #if defined(__ICCARM__)
46 
47 //Transmit buffer
48 #pragma data_alignment = 32
50 //Receive buffer
51 #pragma data_alignment = 32
53 //Transmit DMA descriptors
54 #pragma data_alignment = 32
56 //Receive DMA descriptors
57 #pragma data_alignment = 32
59 
60 //ARM or GCC compiler?
61 #else
62 
63 //Transmit buffer
65  __attribute__((aligned(32)));
66 //Receive buffer
68  __attribute__((aligned(32)));
69 //Transmit DMA descriptors
71  __attribute__((aligned(32)));
72 //Receive DMA descriptors
74  __attribute__((aligned(32)));
75 
76 #endif
77 
78 //Current transmit descriptor
79 static uint_t txIndex;
80 //Current receive descriptor
81 static uint_t rxIndex;
82 
83 
84 /**
85  * @brief S7G2 Ethernet MAC driver
86  **/
87 
89 {
91  ETH_MTU,
102  TRUE,
103  TRUE,
104  TRUE,
105  TRUE
106 };
107 
108 
109 /**
110  * @brief S7G2 Ethernet MAC initialization
111  * @param[in] interface Underlying network interface
112  * @return Error code
113  **/
114 
116 {
117  error_t error;
118 
119  //Debug message
120  TRACE_INFO("Initializing S7G2 Ethernet MAC...\r\n");
121 
122  //Save underlying network interface
123  nicDriverInterface = interface;
124 
125  //Disable protection
126  R_SYSTEM->PRCR = 0xA50B;
127  //Cancel EDMAC1 module stop state
128  R_MSTP->MSTPCRB_b.MSTPB14 = 0;
129  //Enable protection
130  R_SYSTEM->PRCR = 0xA500;
131 
132  //GPIO configuration
133  s7g2EthInitGpio(interface);
134 
135  //Reset EDMAC1 module
136  R_EDMAC1->EDMR_b.SWR = 1;
137  sleep(10);
138 
139  //PHY transceiver initialization
140  error = interface->phyDriver->init(interface);
141  //Failed to initialize PHY transceiver?
142  if(error)
143  return error;
144 
145  //Initialize DMA descriptor lists
146  s7g2EthInitDmaDesc(interface);
147 
148  //Maximum frame length that can be accepted
149  R_ETHERC1->RFLR = S7G2_ETH_RX_BUFFER_SIZE;
150  //Set default inter packet gap (96-bit time)
151  R_ETHERC1->IPGR = 0x14;
152 
153  //Set the upper 32 bits of the MAC address
154  R_ETHERC1->MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
155  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
156 
157  //Set the lower 16 bits of the MAC address
158  R_ETHERC1->MALR_b.MALR = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
159 
160  //Set descriptor length (16 bytes)
161  R_EDMAC1->EDMR_b.DL = 0;
162  //Select little endian mode
163  R_EDMAC1->EDMR_b.DE = 1;
164  //Use store and forward mode
165  R_EDMAC1->TFTR_b.TFT = 0;
166 
167  //Set transmit FIFO size (2048 bytes)
168  R_EDMAC1->FDR_b.TFD = 7;
169  //Set receive FIFO size (2048 bytes)
170  R_EDMAC1->FDR_b.RFD = 7;
171 
172  //Enable continuous reception of multiple frames
173  R_EDMAC1->RMCR_b.RNR = 1;
174 
175  //Accept transmit interrupt notifications
176  R_EDMAC1->TRIMD_b.TIM = 0;
177  R_EDMAC1->TRIMD_b.TIS = 1;
178 
179  //Disable all EDMAC interrupts
180  R_EDMAC1->EESIPR = 0;
181  //Enable only the desired EDMAC interrupts
182  R_EDMAC1->EESIPR_b.TWBIP = 1;
183  R_EDMAC1->EESIPR_b.FRIP = 1;
184 
185  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
186  NVIC_SetPriorityGrouping(S7G2_ETH_IRQ_PRIORITY_GROUPING);
187 
188  //Configure EDMAC interrupt priority
189  NVIC_SetPriority(ETHER_EINT1_IRQn, NVIC_EncodePriority(S7G2_ETH_IRQ_PRIORITY_GROUPING,
191 
192  //Enable transmission and reception
193  R_ETHERC1->ECMR_b.TE = 1;
194  R_ETHERC1->ECMR_b.RE = 1;
195 
196  //Instruct the DMA to poll the receive descriptor list
197  R_EDMAC1->EDRRR_b.RR = 1;
198 
199  //Accept any packets from the upper layer
200  osSetEvent(&interface->nicTxEvent);
201 
202  //Successful initialization
203  return NO_ERROR;
204 }
205 
206 
207 //SK-S7G2 evaluation board?
208 #if defined(USE_SK_S7G2)
209 
210 /**
211  * @brief GPIO configuration
212  * @param[in] interface Underlying network interface
213  **/
214 
215 void s7g2EthInitGpio(NetInterface *interface)
216 {
217  //Unlock PFS registers
218  R_PMISC->PWPR_b.BOWI = 0;
219  R_PMISC->PWPR_b.PFSWE = 1;
220 
221  //Select RMII interface mode
222  R_PMISC->PFENET_b.PHYMODE1 = 0;
223 
224  //Configure ET1_MDC (P4_3)
225  R_PFS->P403PFS_b.PMR = 1;
226  R_PFS->P403PFS_b.PSEL = 23;
227 
228  //Configure ET1_MDIO (P4_4)
229  R_PFS->P404PFS_b.PMR = 1;
230  R_PFS->P404PFS_b.PSEL = 23;
231 
232  //Configure RMII1_TXD_EN (P4_5)
233  R_PFS->P405PFS_b.PMR = 1;
234  R_PFS->P405PFS_b.PSEL = 23;
235 
236  //Configure RMII1_TXD1 (P4_6)
237  R_PFS->P406PFS_b.PMR = 1;
238  R_PFS->P406PFS_b.PSEL = 23;
239 
240  //Configure RMII1_TXD0 (P7_0)
241  R_PFS->P700PFS_b.PMR = 1;
242  R_PFS->P700PFS_b.PSEL = 23;
243 
244  //Configure REF50CK1 (P7_1)
245  R_PFS->P701PFS_b.PMR = 1;
246  R_PFS->P701PFS_b.PSEL = 23;
247 
248  //Configure RMII1_RXD0 (P7_2)
249  R_PFS->P702PFS_b.PMR = 1;
250  R_PFS->P702PFS_b.PSEL = 23;
251 
252  //Configure RMII1_RXD1 (P7_3)
253  R_PFS->P703PFS_b.PMR = 1;
254  R_PFS->P703PFS_b.PSEL = 23;
255 
256  //Configure RMII1_RX_ER (P7_4)
257  R_PFS->P704PFS_b.PMR = 1;
258  R_PFS->P704PFS_b.PSEL = 23;
259 
260  //Configure RMII1_CRS_DV (P7_5)
261  R_PFS->P705PFS_b.PMR = 1;
262  R_PFS->P705PFS_b.PSEL = 23;
263 
264  //Lock PFS registers
265  R_PMISC->PWPR_b.PFSWE = 0;
266  R_PMISC->PWPR_b.BOWI = 1;
267 }
268 
269 #endif
270 
271 
272 /**
273  * @brief Initialize DMA descriptor lists
274  * @param[in] interface Underlying network interface
275  **/
276 
278 {
279  uint_t i;
280 
281  //Initialize TX descriptors
282  for(i = 0; i < S7G2_ETH_TX_BUFFER_COUNT; i++)
283  {
284  //The descriptor is initially owned by the application
285  txDmaDesc[i].td0 = 0;
286  //Transmit buffer length
287  txDmaDesc[i].td1 = 0;
288  //Transmit buffer address
289  txDmaDesc[i].td2 = (uint32_t) txBuffer[i];
290  //Clear padding field
291  txDmaDesc[i].padding = 0;
292  }
293 
294  //Mark the last descriptor entry with the TDLE flag
295  txDmaDesc[i - 1].td0 |= EDMAC_TD0_TDLE;
296  //Initialize TX descriptor index
297  txIndex = 0;
298 
299  //Initialize RX descriptors
300  for(i = 0; i < S7G2_ETH_RX_BUFFER_COUNT; i++)
301  {
302  //The descriptor is initially owned by the DMA
303  rxDmaDesc[i].rd0 = EDMAC_RD0_RACT;
304  //Receive buffer length
306  //Receive buffer address
307  rxDmaDesc[i].rd2 = (uint32_t) rxBuffer[i];
308  //Clear padding field
309  rxDmaDesc[i].padding = 0;
310  }
311 
312  //Mark the last descriptor entry with the RDLE flag
313  rxDmaDesc[i - 1].rd0 |= EDMAC_RD0_RDLE;
314  //Initialize RX descriptor index
315  rxIndex = 0;
316 
317  //Start address of the TX descriptor list
318  R_EDMAC1->TDLAR = (uint32_t) txDmaDesc;
319  //Start address of the RX descriptor list
320  R_EDMAC1->RDLAR = (uint32_t) rxDmaDesc;
321 }
322 
323 
324 /**
325  * @brief S7G2 Ethernet MAC timer handler
326  *
327  * This routine is periodically called by the TCP/IP stack to
328  * handle periodic operations such as polling the link state
329  *
330  * @param[in] interface Underlying network interface
331  **/
332 
333 void s7g2EthTick(NetInterface *interface)
334 {
335  //Handle periodic operations
336  interface->phyDriver->tick(interface);
337 }
338 
339 
340 /**
341  * @brief Enable interrupts
342  * @param[in] interface Underlying network interface
343  **/
344 
346 {
347  //Enable Ethernet MAC interrupts
348  NVIC_EnableIRQ(ETHER_EINT1_IRQn);
349  //Enable Ethernet PHY interrupts
350  interface->phyDriver->enableIrq(interface);
351 }
352 
353 
354 /**
355  * @brief Disable interrupts
356  * @param[in] interface Underlying network interface
357  **/
358 
360 {
361  //Disable Ethernet MAC interrupts
362  NVIC_DisableIRQ(ETHER_EINT1_IRQn);
363  //Disable Ethernet PHY interrupts
364  interface->phyDriver->disableIrq(interface);
365 }
366 
367 
368 /**
369  * @brief S7G2 Ethernet MAC interrupt service routine
370  **/
371 
373 {
374  bool_t flag;
375  uint32_t status;
376 
377  //Interrupt service routine prologue
378  osEnterIsr();
379 
380  //This flag will be set if a higher priority task must be woken
381  flag = FALSE;
382 
383  //Read interrupt status register
384  status = R_EDMAC1->EESR;
385 
386  //A packet has been transmitted?
387  if(status & EDMAC_EESR_TWB)
388  {
389  //Clear TWB interrupt flag
390  R_EDMAC1->EESR = EDMAC_EESR_TWB;
391 
392  //Check whether the TX buffer is available for writing
393  if(!(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT))
394  {
395  //Notify the TCP/IP stack that the transmitter is ready to send
396  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
397  }
398  }
399 
400  //A packet has been received?
401  if(status & EDMAC_EESR_FR)
402  {
403  //Disable FR interrupts
404  R_EDMAC1->EESIPR_b.FRIP = 0;
405 
406  //Set event flag
407  nicDriverInterface->nicEvent = TRUE;
408  //Notify the TCP/IP stack of the event
409  flag |= osSetEventFromIsr(&netEvent);
410  }
411 
412  //Clear IR flag
413  R_ICU->IELSRn_b[ETHER_EINT1_IRQn].IR = 0;
414 
415  //Interrupt service routine epilogue
416  osExitIsr(flag);
417 }
418 
419 
420 /**
421  * @brief S7G2 Ethernet MAC event handler
422  * @param[in] interface Underlying network interface
423  **/
424 
426 {
427  error_t error;
428 
429  //Packet received?
430  if(R_EDMAC1->EESR & EDMAC_EESR_FR)
431  {
432  //Clear FR interrupt flag
433  R_EDMAC1->EESR = EDMAC_EESR_FR;
434 
435  //Process all pending packets
436  do
437  {
438  //Read incoming packet
439  error = s7g2EthReceivePacket(interface);
440 
441  //No more data in the receive buffer?
442  } while(error != ERROR_BUFFER_EMPTY);
443  }
444 
445  //Re-enable EDMAC interrupts
446  R_EDMAC1->EESIPR_b.TWBIP = 1;
447  R_EDMAC1->EESIPR_b.FRIP = 1;
448 }
449 
450 
451 /**
452  * @brief Send a packet
453  * @param[in] interface Underlying network interface
454  * @param[in] buffer Multi-part buffer containing the data to send
455  * @param[in] offset Offset to the first data byte
456  * @return Error code
457  **/
458 
460  const NetBuffer *buffer, size_t offset)
461 {
462  //Retrieve the length of the packet
463  size_t length = netBufferGetLength(buffer) - offset;
464 
465  //Check the frame length
467  {
468  //The transmitter can accept another packet
469  osSetEvent(&interface->nicTxEvent);
470  //Report an error
471  return ERROR_INVALID_LENGTH;
472  }
473 
474  //Make sure the current buffer is available for writing
475  if(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT)
476  return ERROR_FAILURE;
477 
478  //Copy user data to the transmit buffer
479  netBufferRead(txBuffer[txIndex], buffer, offset, length);
480 
481  //Write the number of bytes to send
482  txDmaDesc[txIndex].td1 = (length << 16) & EDMAC_TD1_TBL;
483 
484  //Check current index
485  if(txIndex < (S7G2_ETH_TX_BUFFER_COUNT - 1))
486  {
487  //Give the ownership of the descriptor to the DMA engine
488  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TFP_SOF |
490 
491  //Point to the next descriptor
492  txIndex++;
493  }
494  else
495  {
496  //Give the ownership of the descriptor to the DMA engine
497  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TDLE |
499 
500  //Wrap around
501  txIndex = 0;
502  }
503 
504  //Instruct the DMA to poll the transmit descriptor list
505  R_EDMAC1->EDTRR_b.TR = 1;
506 
507  //Check whether the next buffer is available for writing
508  if(!(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT))
509  {
510  //The transmitter can accept another packet
511  osSetEvent(&interface->nicTxEvent);
512  }
513 
514  //Successful write operation
515  return NO_ERROR;
516 }
517 
518 
519 /**
520  * @brief Receive a packet
521  * @param[in] interface Underlying network interface
522  * @return Error code
523  **/
524 
526 {
527  error_t error;
528  size_t n;
529 
530  //The current buffer is available for reading?
531  if(!(rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RACT))
532  {
533  //SOF and EOF flags should be set
534  if((rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_SOF) &&
535  (rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_EOF))
536  {
537  //Make sure no error occurred
538  if(!(rxDmaDesc[rxIndex].rd0 & (EDMAC_RD0_RFS_MASK & ~EDMAC_RD0_RFS_RMAF)))
539  {
540  //Retrieve the length of the frame
541  n = rxDmaDesc[rxIndex].rd1 & EDMAC_RD1_RFL;
542  //Limit the number of data to read
544 
545  //Pass the packet to the upper layer
546  nicProcessPacket(interface, rxBuffer[rxIndex], n);
547 
548  //Valid packet received
549  error = NO_ERROR;
550  }
551  else
552  {
553  //The received packet contains an error
554  error = ERROR_INVALID_PACKET;
555  }
556  }
557  else
558  {
559  //The packet is not valid
560  error = ERROR_INVALID_PACKET;
561  }
562 
563  //Check current index
564  if(rxIndex < (S7G2_ETH_RX_BUFFER_COUNT - 1))
565  {
566  //Give the ownership of the descriptor back to the DMA
567  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT;
568  //Point to the next descriptor
569  rxIndex++;
570  }
571  else
572  {
573  //Give the ownership of the descriptor back to the DMA
574  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT | EDMAC_RD0_RDLE;
575  //Wrap around
576  rxIndex = 0;
577  }
578 
579  //Instruct the DMA to poll the receive descriptor list
580  R_EDMAC1->EDRRR_b.RR = 1;
581  }
582  else
583  {
584  //No more data in the receive buffer
585  error = ERROR_BUFFER_EMPTY;
586  }
587 
588  //Return status code
589  return error;
590 }
591 
592 
593 /**
594  * @brief Configure MAC address filtering
595  * @param[in] interface Underlying network interface
596  * @return Error code
597  **/
598 
600 {
601  uint_t i;
602  bool_t acceptMulticast;
603 
604  //Debug message
605  TRACE_DEBUG("Updating MAC filter...\r\n");
606 
607  //Set the upper 32 bits of the MAC address
608  R_ETHERC1->MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
609  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
610 
611  //Set the lower 16 bits of the MAC address
612  R_ETHERC1->MALR_b.MALR = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
613 
614  //This flag will be set if multicast addresses should be accepted
615  acceptMulticast = FALSE;
616 
617  //The MAC address filter contains the list of MAC addresses to accept
618  //when receiving an Ethernet frame
619  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
620  {
621  //Valid entry?
622  if(interface->macAddrFilter[i].refCount > 0)
623  {
624  //Accept multicast addresses
625  acceptMulticast = TRUE;
626  //We are done
627  break;
628  }
629  }
630 
631  //Enable the reception of multicast frames if necessary
632  if(acceptMulticast)
633  R_EDMAC1->EESR_b.RMAF = 1;
634  else
635  R_EDMAC1->EESR_b.RMAF = 0;
636 
637  //Successful processing
638  return NO_ERROR;
639 }
640 
641 
642 /**
643  * @brief Adjust MAC configuration parameters for proper operation
644  * @param[in] interface Underlying network interface
645  * @return Error code
646  **/
647 
649 {
650  //10BASE-T or 100BASE-TX operation mode?
651  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
652  R_ETHERC1->ECMR_b.RTM = 1;
653  else
654  R_ETHERC1->ECMR_b.RTM = 0;
655 
656  //Half-duplex or full-duplex mode?
657  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
658  R_ETHERC1->ECMR_b.DM = 1;
659  else
660  R_ETHERC1->ECMR_b.DM = 0;
661 
662  //Successful processing
663  return NO_ERROR;
664 }
665 
666 
667 /**
668  * @brief Write PHY register
669  * @param[in] opcode Access type (2 bits)
670  * @param[in] phyAddr PHY address (5 bits)
671  * @param[in] regAddr Register address (5 bits)
672  * @param[in] data Register value
673  **/
674 
675 void s7g2EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
676  uint8_t regAddr, uint16_t data)
677 {
678  //Synchronization pattern
680  //Start of frame
682  //Set up a write operation
684  //Write PHY address
685  s7g2EthWriteSmi(phyAddr, 5);
686  //Write register address
688  //Turnaround
690  //Write register value
691  s7g2EthWriteSmi(data, 16);
692  //Release MDIO
693  s7g2EthReadSmi(1);
694 }
695 
696 
697 /**
698  * @brief Read PHY register
699  * @param[in] opcode Access type (2 bits)
700  * @param[in] phyAddr PHY address (5 bits)
701  * @param[in] regAddr Register address (5 bits)
702  * @return Register value
703  **/
704 
705 uint16_t s7g2EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
706  uint8_t regAddr)
707 {
708  uint16_t data;
709 
710  //Synchronization pattern
712  //Start of frame
714  //Set up a read operation
716  //Write PHY address
717  s7g2EthWriteSmi(phyAddr, 5);
718  //Write register address
720  //Turnaround to avoid contention
721  s7g2EthReadSmi(1);
722  //Read register value
723  data = s7g2EthReadSmi(16);
724  //Force the PHY to release the MDIO pin
725  s7g2EthReadSmi(1);
726 
727  //Return PHY register contents
728  return data;
729 }
730 
731 
732 /**
733  * @brief SMI write operation
734  * @param[in] data Raw data to be written
735  * @param[in] length Number of bits to be written
736  **/
737 
739 {
740  //Skip the most significant bits since they are meaningless
741  data <<= 32 - length;
742 
743  //Configure MDIO as an output
744  R_ETHERC1->PIR_b.MMD = 1;
745 
746  //Write the specified number of bits
747  while(length--)
748  {
749  //Write MDIO
750  if(data & 0x80000000)
751  R_ETHERC1->PIR_b.MDO = 1;
752  else
753  R_ETHERC1->PIR_b.MDO = 0;
754 
755  //Assert MDC
756  usleep(1);
757  R_ETHERC1->PIR_b.MDC = 1;
758  //Deassert MDC
759  usleep(1);
760  R_ETHERC1->PIR_b.MDC = 0;
761 
762  //Rotate data
763  data <<= 1;
764  }
765 }
766 
767 
768 /**
769  * @brief SMI read operation
770  * @param[in] length Number of bits to be read
771  * @return Data resulting from the MDIO read operation
772  **/
773 
775 {
776  uint32_t data = 0;
777 
778  //Configure MDIO as an input
779  R_ETHERC1->PIR_b.MMD = 0;
780 
781  //Read the specified number of bits
782  while(length--)
783  {
784  //Rotate data
785  data <<= 1;
786 
787  //Assert MDC
788  R_ETHERC1->PIR_b.MDC = 1;
789  usleep(1);
790  //Deassert MDC
791  R_ETHERC1->PIR_b.MDC = 0;
792  usleep(1);
793 
794  //Check MDIO state
795  if(R_ETHERC1->PIR_b.MDI)
796  data |= 0x00000001;
797  }
798 
799  //Return the received data
800  return data;
801 }
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
uint16_t s7g2EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define usleep(delay)
Definition: os_port.h:127
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
int bool_t
Definition: compiler_port.h:49
#define EDMAC_EESR_TWB
#define EDMAC_RD0_RFS_MASK
void s7g2EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define EDMAC_RD0_RDLE
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:672
#define EDMAC_RD1_RFL
#define EDMAC_TD0_TACT
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:383
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
#define EDMAC_TD0_TFP_SOF
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:74
#define TRUE
Definition: os_port.h:50
#define S7G2_ETH_RX_BUFFER_SIZE
#define sleep(delay)
Definition: os_port.h:131
void ETHER_EINT1_IRQHandler(void)
S7G2 Ethernet MAC interrupt service routine.
uint32_t s7g2EthReadSmi(uint_t length)
SMI read operation.
#define SMI_TA
Definition: nic.h:64
const NicDriver s7g2EthDriver
S7G2 Ethernet MAC driver.
#define SMI_START
Definition: nic.h:60
void s7g2EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
error_t s7g2EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define osExitIsr(flag)
Renesas Synergy S7G2 Ethernet MAC controller.
#define S7G2_ETH_IRQ_SUB_PRIORITY
#define EDMAC_RD0_RFP_EOF
void s7g2EthInitGpio(NetInterface *interface)
#define FALSE
Definition: os_port.h:46
error_t
Error codes.
Definition: error.h:42
#define EDMAC_TD0_TFP_EOF
Generic error code.
Definition: error.h:45
#define txBuffer
#define NetInterface
Definition: net.h:36
error_t s7g2EthInit(NetInterface *interface)
S7G2 Ethernet MAC initialization.
#define S7G2_ETH_RX_BUFFER_COUNT
void s7g2EthEventHandler(NetInterface *interface)
S7G2 Ethernet MAC event handler.
OsEvent netEvent
Definition: net.c:77
Receive DMA descriptor.
#define S7G2_ETH_IRQ_PRIORITY_GROUPING
#define TRACE_INFO(...)
Definition: debug.h:94
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define MIN(a, b)
Definition: os_port.h:62
#define EDMAC_RD0_RACT
#define rxBuffer
#define EDMAC_RD0_RFS_RMAF
error_t s7g2EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define EDMAC_RD0_RFP_SOF
#define TRACE_DEBUG(...)
Definition: debug.h:106
void s7g2EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define S7G2_ETH_IRQ_GROUP_PRIORITY
uint16_t regAddr
#define EDMAC_RD1_RBL
#define ETH_MTU
Definition: ethernet.h:91
uint8_t n
Transmit DMA descriptor.
error_t s7g2EthReceivePacket(NetInterface *interface)
Receive a packet.
void s7g2EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define S7G2_ETH_TX_BUFFER_COUNT
#define EDMAC_TD0_TWBI
error_t s7g2EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define osEnterIsr()
#define EDMAC_EESR_FR
#define rxDmaDesc
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define EDMAC_TD1_TBL
#define txDmaDesc
#define SMI_SYNC
Definition: nic.h:59
unsigned int uint_t
Definition: compiler_port.h:45
TCP/IP stack core.
uint8_t data[]
Definition: dtls_misc.h:176
void s7g2EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
NIC driver.
Definition: nic.h:179
#define EDMAC_TD0_TDLE
void s7g2EthTick(NetInterface *interface)
S7G2 Ethernet MAC timer handler.
Success.
Definition: error.h:44
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
Debugging facilities.
#define S7G2_ETH_TX_BUFFER_SIZE
Ethernet interface.
Definition: nic.h:79