s7g2_eth_driver.c
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1 /**
2  * @file s7g2_eth_driver.c
3  * @brief Renesas Synergy S7G2 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include "bsp_irq_cfg.h"
34 #include "r7fs7g2x.h"
35 #include "core/net.h"
37 #include "debug.h"
38 
39 //Underlying network interface
40 static NetInterface *nicDriverInterface;
41 
42 //IAR EWARM compiler?
43 #if defined(__ICCARM__)
44 
45 //Transmit buffer
46 #pragma data_alignment = 32
48 //Receive buffer
49 #pragma data_alignment = 32
51 //Transmit DMA descriptors
52 #pragma data_alignment = 32
54 //Receive DMA descriptors
55 #pragma data_alignment = 32
57 
58 //ARM or GCC compiler?
59 #else
60 
61 //Transmit buffer
63  __attribute__((aligned(32)));
64 //Receive buffer
66  __attribute__((aligned(32)));
67 //Transmit DMA descriptors
69  __attribute__((aligned(32)));
70 //Receive DMA descriptors
72  __attribute__((aligned(32)));
73 
74 #endif
75 
76 //Current transmit descriptor
77 static uint_t txIndex;
78 //Current receive descriptor
79 static uint_t rxIndex;
80 
81 
82 /**
83  * @brief S7G2 Ethernet MAC driver
84  **/
85 
87 {
89  ETH_MTU,
100  TRUE,
101  TRUE,
102  TRUE,
103  TRUE
104 };
105 
106 
107 /**
108  * @brief S7G2 Ethernet MAC initialization
109  * @param[in] interface Underlying network interface
110  * @return Error code
111  **/
112 
114 {
115  error_t error;
116 
117  //Debug message
118  TRACE_INFO("Initializing S7G2 Ethernet MAC...\r\n");
119 
120  //Save underlying network interface
121  nicDriverInterface = interface;
122 
123  //Disable protection
124  R_SYSTEM->PRCR = 0xA50B;
125  //Cancel EDMAC1 module stop state
126  R_MSTP->MSTPCRB_b.MSTPB14 = 0;
127  //Enable protection
128  R_SYSTEM->PRCR = 0xA500;
129 
130  //GPIO configuration
131  s7g2EthInitGpio(interface);
132 
133  //Reset EDMAC1 module
134  R_EDMAC1->EDMR_b.SWR = 1;
135  sleep(10);
136 
137  //PHY transceiver initialization
138  error = interface->phyDriver->init(interface);
139  //Failed to initialize PHY transceiver?
140  if(error)
141  return error;
142 
143  //Initialize DMA descriptor lists
144  s7g2EthInitDmaDesc(interface);
145 
146  //Maximum frame length that can be accepted
147  R_ETHERC1->RFLR = 1518;
148  //Set default inter packet gap (96-bit time)
149  R_ETHERC1->IPGR = 0x14;
150 
151  //Set the upper 32 bits of the MAC address
152  R_ETHERC1->MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
153  (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
154 
155  //Set the lower 16 bits of the MAC address
156  R_ETHERC1->MALR_b.MALR = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
157 
158  //Set descriptor length (16 bytes)
159  R_EDMAC1->EDMR_b.DL = 0;
160  //Select little endian mode
161  R_EDMAC1->EDMR_b.DE = 1;
162  //Use store and forward mode
163  R_EDMAC1->TFTR_b.TFT = 0;
164 
165  //Set transmit FIFO size (2048 bytes)
166  R_EDMAC1->FDR_b.TFD = 7;
167  //Set receive FIFO size (2048 bytes)
168  R_EDMAC1->FDR_b.RFD = 7;
169 
170  //Enable continuous reception of multiple frames
171  R_EDMAC1->RMCR_b.RNR = 1;
172 
173  //Accept transmit interrupt notifications
174  R_EDMAC1->TRIMD_b.TIM = 0;
175  R_EDMAC1->TRIMD_b.TIS = 1;
176 
177  //Disable all EDMAC interrupts
178  R_EDMAC1->EESIPR = 0;
179  //Enable only the desired EDMAC interrupts
180  R_EDMAC1->EESIPR_b.TWBIP = 1;
181  R_EDMAC1->EESIPR_b.FRIP = 1;
182 
183  //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
184  NVIC_SetPriorityGrouping(S7G2_ETH_IRQ_PRIORITY_GROUPING);
185 
186  //Configure EDMAC interrupt priority
187  NVIC_SetPriority(ETHER_EINT1_IRQn, NVIC_EncodePriority(S7G2_ETH_IRQ_PRIORITY_GROUPING,
189 
190  //Enable transmission and reception
191  R_ETHERC1->ECMR_b.TE = 1;
192  R_ETHERC1->ECMR_b.RE = 1;
193 
194  //Instruct the DMA to poll the receive descriptor list
195  R_EDMAC1->EDRRR_b.RR = 1;
196 
197  //Accept any packets from the upper layer
198  osSetEvent(&interface->nicTxEvent);
199 
200  //Successful initialization
201  return NO_ERROR;
202 }
203 
204 
205 //SK-S7G2 evaluation board?
206 #if defined(USE_SK_S7G2)
207 
208 /**
209  * @brief GPIO configuration
210  * @param[in] interface Underlying network interface
211  **/
212 
213 void s7g2EthInitGpio(NetInterface *interface)
214 {
215  //Unlock PFS registers
216  R_PMISC->PWPR_b.BOWI = 0;
217  R_PMISC->PWPR_b.PSFWE = 1;
218 
219  //Select RMII interface mode
220  R_PMISC->PFENET_b.PHYMODE1 = 0;
221 
222  //Configure ET1_MDC (P4_3)
223  R_PFS->P403PFS_b.PMR = 1;
224  R_PFS->P403PFS_b.PSEL = 23;
225 
226  //Configure ET1_MDIO (P4_4)
227  R_PFS->P404PFS_b.PMR = 1;
228  R_PFS->P404PFS_b.PSEL = 23;
229 
230  //Configure RMII1_TXD_EN (P4_5)
231  R_PFS->P405PFS_b.PMR = 1;
232  R_PFS->P405PFS_b.PSEL = 23;
233 
234  //Configure RMII1_TXD1 (P4_6)
235  R_PFS->P406PFS_b.PMR = 1;
236  R_PFS->P406PFS_b.PSEL = 23;
237 
238  //Configure RMII1_TXD0 (P7_0)
239  R_PFS->P700PFS_b.PMR = 1;
240  R_PFS->P700PFS_b.PSEL = 23;
241 
242  //Configure REF50CK1 (P7_1)
243  R_PFS->P701PFS_b.PMR = 1;
244  R_PFS->P701PFS_b.PSEL = 23;
245 
246  //Configure RMII1_RXD0 (P7_2)
247  R_PFS->P702PFS_b.PMR = 1;
248  R_PFS->P702PFS_b.PSEL = 23;
249 
250  //Configure RMII1_RXD1 (P7_3)
251  R_PFS->P703PFS_b.PMR = 1;
252  R_PFS->P703PFS_b.PSEL = 23;
253 
254  //Configure RMII1_RX_ER (P7_4)
255  R_PFS->P704PFS_b.PMR = 1;
256  R_PFS->P704PFS_b.PSEL = 23;
257 
258  //Configure RMII1_CRS_DV (P7_5)
259  R_PFS->P705PFS_b.PMR = 1;
260  R_PFS->P705PFS_b.PSEL = 23;
261 
262  //Lock PFS registers
263  R_PMISC->PWPR_b.PSFWE = 0;
264  R_PMISC->PWPR_b.BOWI = 1;
265 }
266 
267 #endif
268 
269 
270 /**
271  * @brief Initialize DMA descriptor lists
272  * @param[in] interface Underlying network interface
273  **/
274 
276 {
277  uint_t i;
278 
279  //Initialize TX descriptors
280  for(i = 0; i < S7G2_ETH_TX_BUFFER_COUNT; i++)
281  {
282  //The descriptor is initially owned by the application
283  txDmaDesc[i].td0 = 0;
284  //Transmit buffer length
285  txDmaDesc[i].td1 = 0;
286  //Transmit buffer address
287  txDmaDesc[i].td2 = (uint32_t) txBuffer[i];
288  //Clear padding field
289  txDmaDesc[i].padding = 0;
290  }
291 
292  //Mark the last descriptor entry with the TDLE flag
293  txDmaDesc[i - 1].td0 |= EDMAC_TD0_TDLE;
294  //Initialize TX descriptor index
295  txIndex = 0;
296 
297  //Initialize RX descriptors
298  for(i = 0; i < S7G2_ETH_RX_BUFFER_COUNT; i++)
299  {
300  //The descriptor is initially owned by the DMA
301  rxDmaDesc[i].rd0 = EDMAC_RD0_RACT;
302  //Receive buffer length
304  //Receive buffer address
305  rxDmaDesc[i].rd2 = (uint32_t) rxBuffer[i];
306  //Clear padding field
307  rxDmaDesc[i].padding = 0;
308  }
309 
310  //Mark the last descriptor entry with the RDLE flag
311  rxDmaDesc[i - 1].rd0 |= EDMAC_RD0_RDLE;
312  //Initialize RX descriptor index
313  rxIndex = 0;
314 
315  //Start address of the TX descriptor list
316  R_EDMAC1->TDLAR = (uint32_t) txDmaDesc;
317  //Start address of the RX descriptor list
318  R_EDMAC1->RDLAR = (uint32_t) rxDmaDesc;
319 }
320 
321 
322 /**
323  * @brief S7G2 Ethernet MAC timer handler
324  *
325  * This routine is periodically called by the TCP/IP stack to
326  * handle periodic operations such as polling the link state
327  *
328  * @param[in] interface Underlying network interface
329  **/
330 
331 void s7g2EthTick(NetInterface *interface)
332 {
333  //Handle periodic operations
334  interface->phyDriver->tick(interface);
335 }
336 
337 
338 /**
339  * @brief Enable interrupts
340  * @param[in] interface Underlying network interface
341  **/
342 
344 {
345  //Enable Ethernet MAC interrupts
346  NVIC_EnableIRQ(ETHER_EINT1_IRQn);
347  //Enable Ethernet PHY interrupts
348  interface->phyDriver->enableIrq(interface);
349 }
350 
351 
352 /**
353  * @brief Disable interrupts
354  * @param[in] interface Underlying network interface
355  **/
356 
358 {
359  //Disable Ethernet MAC interrupts
360  NVIC_DisableIRQ(ETHER_EINT1_IRQn);
361  //Disable Ethernet PHY interrupts
362  interface->phyDriver->disableIrq(interface);
363 }
364 
365 
366 /**
367  * @brief S7G2 Ethernet MAC interrupt service routine
368  **/
369 
371 {
372  bool_t flag;
373  uint32_t status;
374 
375  //Enter interrupt service routine
376  osEnterIsr();
377 
378  //This flag will be set if a higher priority task must be woken
379  flag = FALSE;
380 
381  //Read interrupt status register
382  status = R_EDMAC1->EESR;
383 
384  //A packet has been transmitted?
385  if(status & EDMAC_EESR_TWB)
386  {
387  //Clear TWB interrupt flag
388  R_EDMAC1->EESR = EDMAC_EESR_TWB;
389 
390  //Check whether the TX buffer is available for writing
391  if(!(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT))
392  {
393  //Notify the TCP/IP stack that the transmitter is ready to send
394  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
395  }
396  }
397 
398  //A packet has been received?
399  if(status & EDMAC_EESR_FR)
400  {
401  //Disable FR interrupts
402  R_EDMAC1->EESIPR_b.FRIP = 0;
403 
404  //Set event flag
405  nicDriverInterface->nicEvent = TRUE;
406  //Notify the TCP/IP stack of the event
407  flag |= osSetEventFromIsr(&netEvent);
408  }
409 
410  //Clear IR flag
411  R_ICU->IELSRn_b[ETHER_EINT1_IRQn].IR = 0;
412 
413  //Leave interrupt service routine
414  osExitIsr(flag);
415 }
416 
417 
418 /**
419  * @brief S7G2 Ethernet MAC event handler
420  * @param[in] interface Underlying network interface
421  **/
422 
424 {
425  error_t error;
426 
427  //Packet received?
428  if(R_EDMAC1->EESR & EDMAC_EESR_FR)
429  {
430  //Clear FR interrupt flag
431  R_EDMAC1->EESR = EDMAC_EESR_FR;
432 
433  //Process all pending packets
434  do
435  {
436  //Read incoming packet
437  error = s7g2EthReceivePacket(interface);
438 
439  //No more data in the receive buffer?
440  } while(error != ERROR_BUFFER_EMPTY);
441  }
442 
443  //Re-enable EDMAC interrupts
444  R_EDMAC1->EESIPR_b.TWBIP = 1;
445  R_EDMAC1->EESIPR_b.FRIP = 1;
446 }
447 
448 
449 /**
450  * @brief Send a packet
451  * @param[in] interface Underlying network interface
452  * @param[in] buffer Multi-part buffer containing the data to send
453  * @param[in] offset Offset to the first data byte
454  * @return Error code
455  **/
456 
458  const NetBuffer *buffer, size_t offset)
459 {
460  //Retrieve the length of the packet
461  size_t length = netBufferGetLength(buffer) - offset;
462 
463  //Check the frame length
465  {
466  //The transmitter can accept another packet
467  osSetEvent(&interface->nicTxEvent);
468  //Report an error
469  return ERROR_INVALID_LENGTH;
470  }
471 
472  //Make sure the current buffer is available for writing
473  if(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT)
474  return ERROR_FAILURE;
475 
476  //Copy user data to the transmit buffer
477  netBufferRead(txBuffer[txIndex], buffer, offset, length);
478 
479  //Write the number of bytes to send
480  txDmaDesc[txIndex].td1 = (length << 16) & EDMAC_TD1_TBL;
481 
482  //Check current index
483  if(txIndex < (S7G2_ETH_TX_BUFFER_COUNT - 1))
484  {
485  //Give the ownership of the descriptor to the DMA engine
486  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TFP_SOF |
488 
489  //Point to the next descriptor
490  txIndex++;
491  }
492  else
493  {
494  //Give the ownership of the descriptor to the DMA engine
495  txDmaDesc[txIndex].td0 = EDMAC_TD0_TACT | EDMAC_TD0_TDLE |
497 
498  //Wrap around
499  txIndex = 0;
500  }
501 
502  //Instruct the DMA to poll the transmit descriptor list
503  R_EDMAC1->EDTRR_b.TR = 1;
504 
505  //Check whether the next buffer is available for writing
506  if(!(txDmaDesc[txIndex].td0 & EDMAC_TD0_TACT))
507  {
508  //The transmitter can accept another packet
509  osSetEvent(&interface->nicTxEvent);
510  }
511 
512  //Successful write operation
513  return NO_ERROR;
514 }
515 
516 
517 /**
518  * @brief Receive a packet
519  * @param[in] interface Underlying network interface
520  * @return Error code
521  **/
522 
524 {
525  error_t error;
526  size_t n;
527 
528  //The current buffer is available for reading?
529  if(!(rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RACT))
530  {
531  //SOF and EOF flags should be set
532  if((rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_SOF) &&
533  (rxDmaDesc[rxIndex].rd0 & EDMAC_RD0_RFP_EOF))
534  {
535  //Make sure no error occurred
536  if(!(rxDmaDesc[rxIndex].rd0 & (EDMAC_RD0_RFS_MASK & ~EDMAC_RD0_RFS_RMAF)))
537  {
538  //Retrieve the length of the frame
539  n = rxDmaDesc[rxIndex].rd1 & EDMAC_RD1_RFL;
540  //Limit the number of data to read
542 
543  //Pass the packet to the upper layer
544  nicProcessPacket(interface, rxBuffer[rxIndex], n);
545 
546  //Valid packet received
547  error = NO_ERROR;
548  }
549  else
550  {
551  //The received packet contains an error
552  error = ERROR_INVALID_PACKET;
553  }
554  }
555  else
556  {
557  //The packet is not valid
558  error = ERROR_INVALID_PACKET;
559  }
560 
561  //Check current index
562  if(rxIndex < (S7G2_ETH_RX_BUFFER_COUNT - 1))
563  {
564  //Give the ownership of the descriptor back to the DMA
565  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT;
566  //Point to the next descriptor
567  rxIndex++;
568  }
569  else
570  {
571  //Give the ownership of the descriptor back to the DMA
572  rxDmaDesc[rxIndex].rd0 = EDMAC_RD0_RACT | EDMAC_RD0_RDLE;
573  //Wrap around
574  rxIndex = 0;
575  }
576 
577  //Instruct the DMA to poll the receive descriptor list
578  R_EDMAC1->EDRRR_b.RR = 1;
579  }
580  else
581  {
582  //No more data in the receive buffer
583  error = ERROR_BUFFER_EMPTY;
584  }
585 
586  //Return status code
587  return error;
588 }
589 
590 
591 /**
592  * @brief Configure MAC address filtering
593  * @param[in] interface Underlying network interface
594  * @return Error code
595  **/
596 
598 {
599  uint_t i;
600  bool_t acceptMulticast;
601 
602  //This flag will be set if multicast addresses should be accepted
603  acceptMulticast = FALSE;
604 
605  //The MAC address filter contains the list of MAC addresses to accept
606  //when receiving an Ethernet frame
607  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
608  {
609  //Valid entry?
610  if(interface->macAddrFilter[i].refCount > 0)
611  {
612  //Accept multicast addresses
613  acceptMulticast = TRUE;
614  //We are done
615  break;
616  }
617  }
618 
619  //Enable the reception of multicast frames if necessary
620  if(acceptMulticast)
621  R_EDMAC1->EESR_b.RMAF = 1;
622  else
623  R_EDMAC1->EESR_b.RMAF = 0;
624 
625  //Successful processing
626  return NO_ERROR;
627 }
628 
629 
630 /**
631  * @brief Adjust MAC configuration parameters for proper operation
632  * @param[in] interface Underlying network interface
633  * @return Error code
634  **/
635 
637 {
638  //10BASE-T or 100BASE-TX operation mode?
639  if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
640  R_ETHERC1->ECMR_b.RTM = 1;
641  else
642  R_ETHERC1->ECMR_b.RTM = 0;
643 
644  //Half-duplex or full-duplex mode?
645  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
646  R_ETHERC1->ECMR_b.DM = 1;
647  else
648  R_ETHERC1->ECMR_b.DM = 0;
649 
650  //Successful processing
651  return NO_ERROR;
652 }
653 
654 
655 /**
656  * @brief Write PHY register
657  * @param[in] phyAddr PHY address
658  * @param[in] regAddr Register address
659  * @param[in] data Register value
660  **/
661 
662 void s7g2EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
663 {
664  //Synchronization pattern
666  //Start of frame
668  //Set up a write operation
670  //Write PHY address
671  s7g2EthWriteSmi(phyAddr, 5);
672  //Write register address
674  //Turnaround
676  //Write register value
677  s7g2EthWriteSmi(data, 16);
678  //Release MDIO
679  s7g2EthReadSmi(1);
680 }
681 
682 
683 /**
684  * @brief Read PHY register
685  * @param[in] phyAddr PHY address
686  * @param[in] regAddr Register address
687  * @return Register value
688  **/
689 
690 uint16_t s7g2EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
691 {
692  uint16_t data;
693 
694  //Synchronization pattern
696  //Start of frame
698  //Set up a read operation
700  //Write PHY address
701  s7g2EthWriteSmi(phyAddr, 5);
702  //Write register address
704  //Turnaround to avoid contention
705  s7g2EthReadSmi(1);
706  //Read register value
707  data = s7g2EthReadSmi(16);
708  //Force the PHY to release the MDIO pin
709  s7g2EthReadSmi(1);
710 
711  //Return PHY register contents
712  return data;
713 }
714 
715 
716 /**
717  * @brief SMI write operation
718  * @param[in] data Raw data to be written
719  * @param[in] length Number of bits to be written
720  **/
721 
723 {
724  //Skip the most significant bits since they are meaningless
725  data <<= 32 - length;
726 
727  //Configure MDIO as an output
728  R_ETHERC1->PIR_b.MMD = 1;
729 
730  //Write the specified number of bits
731  while(length--)
732  {
733  //Write MDIO
734  if(data & 0x80000000)
735  R_ETHERC1->PIR_b.MDO = 1;
736  else
737  R_ETHERC1->PIR_b.MDO = 0;
738 
739  //Assert MDC
740  usleep(1);
741  R_ETHERC1->PIR_b.MDC = 1;
742  //Deassert MDC
743  usleep(1);
744  R_ETHERC1->PIR_b.MDC = 0;
745 
746  //Rotate data
747  data <<= 1;
748  }
749 }
750 
751 
752 /**
753  * @brief SMI read operation
754  * @param[in] length Number of bits to be read
755  * @return Data resulting from the MDIO read operation
756  **/
757 
759 {
760  uint32_t data = 0;
761 
762  //Configure MDIO as an input
763  R_ETHERC1->PIR_b.MMD = 0;
764 
765  //Read the specified number of bits
766  while(length--)
767  {
768  //Rotate data
769  data <<= 1;
770 
771  //Assert MDC
772  R_ETHERC1->PIR_b.MDC = 1;
773  usleep(1);
774  //Deassert MDC
775  R_ETHERC1->PIR_b.MDC = 0;
776  usleep(1);
777 
778  //Check MDIO state
779  if(R_ETHERC1->PIR_b.MDI)
780  data |= 0x00000001;
781  }
782 
783  //Return the received data
784  return data;
785 }
#define txDmaDesc
#define EDMAC_TD0_TWBI
void s7g2EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
void s7g2EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
TCP/IP stack core.
Renesas Synergy S7G2 Ethernet MAC controller.
Debugging facilities.
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
Generic error code.
Definition: error.h:43
#define rxDmaDesc
#define txBuffer
Receive DMA descriptor.
#define sleep(delay)
Definition: os_port.h:126
#define S7G2_ETH_IRQ_PRIORITY_GROUPING
#define EDMAC_TD1_TBL
const NicDriver s7g2EthDriver
S7G2 Ethernet MAC driver.
void s7g2EthEnableIrq(NetInterface *interface)
Enable interrupts.
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
#define S7G2_ETH_IRQ_GROUP_PRIORITY
Transmit DMA descriptor.
#define EDMAC_RD0_RFS_MASK
#define EDMAC_TD0_TFP_SOF
#define EDMAC_RD0_RFP_SOF
void s7g2EthInitGpio(NetInterface *interface)
#define EDMAC_RD1_RFL
void ETHER_EINT1_IRQHandler(void)
S7G2 Ethernet MAC interrupt service routine.
void s7g2EthTick(NetInterface *interface)
S7G2 Ethernet MAC timer handler.
#define EDMAC_RD1_RBL
#define EDMAC_EESR_TWB
#define EDMAC_EESR_FR
void s7g2EthEventHandler(NetInterface *interface)
S7G2 Ethernet MAC event handler.
#define SMI_START
#define EDMAC_TD0_TDLE
#define SMI_SYNC
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
#define usleep(delay)
Definition: os_port.h:122
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void s7g2EthDisableIrq(NetInterface *interface)
Disable interrupts.
#define EDMAC_TD0_TFP_EOF
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
void s7g2EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
Success.
Definition: error.h:42
#define rxBuffer
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
#define EDMAC_RD0_RDLE
unsigned int uint_t
Definition: compiler_port.h:43
#define S7G2_ETH_TX_BUFFER_SIZE
#define EDMAC_TD0_TACT
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define SMI_TA
#define S7G2_ETH_TX_BUFFER_COUNT
#define SMI_READ
#define S7G2_ETH_RX_BUFFER_COUNT
uint16_t s7g2EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
#define SMI_WRITE
#define S7G2_ETH_RX_BUFFER_SIZE
#define osExitIsr(flag)
error_t s7g2EthInit(NetInterface *interface)
S7G2 Ethernet MAC initialization.
#define EDMAC_RD0_RFS_RMAF
#define osEnterIsr()
#define EDMAC_RD0_RACT
uint32_t s7g2EthReadSmi(uint_t length)
SMI read operation.
error_t s7g2EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define FALSE
Definition: os_port.h:44
#define EDMAC_RD0_RFP_EOF
int bool_t
Definition: compiler_port.h:47
error_t s7g2EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t s7g2EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
#define S7G2_ETH_IRQ_SUB_PRIORITY
error_t s7g2EthReceivePacket(NetInterface *interface)
Receive a packet.