s7g2_eth_driver.h
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1 /**
2  * @file s7g2_eth_driver.h
3  * @brief Renesas Synergy S7G2 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _S7G2_ETH_DRIVER_H
30 #define _S7G2_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef S7G2_ETH_TX_BUFFER_COUNT
37  #define S7G2_ETH_TX_BUFFER_COUNT 3
38 #elif (S7G2_ETH_TX_BUFFER_COUNT < 1)
39  #error S7G2_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef S7G2_ETH_TX_BUFFER_SIZE
44  #define S7G2_ETH_TX_BUFFER_SIZE 1536
45 #elif (S7G2_ETH_TX_BUFFER_SIZE != 1536)
46  #error S7G2_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef S7G2_ETH_RX_BUFFER_COUNT
51  #define S7G2_ETH_RX_BUFFER_COUNT 6
52 #elif (S7G2_ETH_RX_BUFFER_COUNT < 1)
53  #error S7G2_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef S7G2_ETH_RX_BUFFER_SIZE
58  #define S7G2_ETH_RX_BUFFER_SIZE 1536
59 #elif (S7G2_ETH_RX_BUFFER_SIZE != 1536)
60  #error S7G2_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Interrupt priority grouping
64 #ifndef S7G2_ETH_IRQ_PRIORITY_GROUPING
65  #define S7G2_ETH_IRQ_PRIORITY_GROUPING 3
66 #elif (S7G2_ETH_IRQ_PRIORITY_GROUPING < 0)
67  #error S7G2_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
68 #endif
69 
70 //Ethernet interrupt group priority
71 #ifndef S7G2_ETH_IRQ_GROUP_PRIORITY
72  #define S7G2_ETH_IRQ_GROUP_PRIORITY 12
73 #elif (S7G2_ETH_IRQ_GROUP_PRIORITY < 0)
74  #error S7G2_ETH_IRQ_GROUP_PRIORITY parameter is not valid
75 #endif
76 
77 //Ethernet interrupt subpriority
78 #ifndef S7G2_ETH_IRQ_SUB_PRIORITY
79  #define S7G2_ETH_IRQ_SUB_PRIORITY 0
80 #elif (S7G2_ETH_IRQ_SUB_PRIORITY < 0)
81  #error S7G2_ETH_IRQ_SUB_PRIORITY parameter is not valid
82 #endif
83 
84 //EESR register
85 #define EDMAC_EESR_TWB 0x40000000
86 #define EDMAC_EESR_TABT 0x04000000
87 #define EDMAC_EESR_RABT 0x02000000
88 #define EDMAC_EESR_RFCOF 0x01000000
89 #define EDMAC_EESR_ADE 0x00800000
90 #define EDMAC_EESR_ECI 0x00400000
91 #define EDMAC_EESR_TC 0x00200000
92 #define EDMAC_EESR_TDE 0x00100000
93 #define EDMAC_EESR_TFUF 0x00080000
94 #define EDMAC_EESR_FR 0x00040000
95 #define EDMAC_EESR_RDE 0x00020000
96 #define EDMAC_EESR_RFOF 0x00010000
97 #define EDMAC_EESR_CND 0x00000800
98 #define EDMAC_EESR_DLC 0x00000400
99 #define EDMAC_EESR_CD 0x00000200
100 #define EDMAC_EESR_TRO 0x00000100
101 #define EDMAC_EESR_RMAF 0x00000080
102 #define EDMAC_EESR_RRF 0x00000010
103 #define EDMAC_EESR_RTLF 0x00000008
104 #define EDMAC_EESR_RTSF 0x00000004
105 #define EDMAC_EESR_PRE 0x00000002
106 #define EDMAC_EESR_CERF 0x00000001
107 
108 //Transmit DMA descriptor flags
109 #define EDMAC_TD0_TACT 0x80000000
110 #define EDMAC_TD0_TDLE 0x40000000
111 #define EDMAC_TD0_TFP_SOF 0x20000000
112 #define EDMAC_TD0_TFP_EOF 0x10000000
113 #define EDMAC_TD0_TFE 0x08000000
114 #define EDMAC_TD0_TWBI 0x04000000
115 #define EDMAC_TD0_TFS_MASK 0x0000010F
116 #define EDMAC_TD0_TFS_TABT 0x00000100
117 #define EDMAC_TD0_TFS_CND 0x00000008
118 #define EDMAC_TD0_TFS_DLC 0x00000004
119 #define EDMAC_TD0_TFS_CD 0x00000002
120 #define EDMAC_TD0_TFS_TRO 0x00000001
121 #define EDMAC_TD1_TBL 0xFFFF0000
122 #define EDMAC_TD2_TBA 0xFFFFFFFF
123 
124 //Receive DMA descriptor flags
125 #define EDMAC_RD0_RACT 0x80000000
126 #define EDMAC_RD0_RDLE 0x40000000
127 #define EDMAC_RD0_RFP_SOF 0x20000000
128 #define EDMAC_RD0_RFP_EOF 0x10000000
129 #define EDMAC_RD0_RFE 0x08000000
130 #define EDMAC_RD0_RFS_MASK 0x0000039F
131 #define EDMAC_RD0_RFS_RFOF 0x00000200
132 #define EDMAC_RD0_RFS_RABT 0x00000100
133 #define EDMAC_RD0_RFS_RMAF 0x00000080
134 #define EDMAC_RD0_RFS_RRF 0x00000010
135 #define EDMAC_RD0_RFS_RTLF 0x00000008
136 #define EDMAC_RD0_RFS_RTSF 0x00000004
137 #define EDMAC_RD0_RFS_PRE 0x00000002
138 #define EDMAC_RD0_RFS_CERF 0x00000001
139 #define EDMAC_RD1_RBL 0xFFFF0000
140 #define EDMAC_RD1_RFL 0x0000FFFF
141 #define EDMAC_RD2_RBA 0xFFFFFFFF
142 
143 //Serial Management Interface
144 #define SMI_SYNC 0xFFFFFFFF
145 #define SMI_START 0x00000001
146 #define SMI_WRITE 0x00000001
147 #define SMI_READ 0x00000002
148 #define SMI_TA 0x00000002
149 
150 //C++ guard
151 #ifdef __cplusplus
152  extern "C" {
153 #endif
154 
155 
156 /**
157  * @brief Transmit DMA descriptor
158  **/
159 
160 typedef struct
161 {
162  uint32_t td0;
163  uint32_t td1;
164  uint32_t td2;
165  uint32_t padding;
166 } S7g2TxDmaDesc;
167 
168 
169 /**
170  * @brief Receive DMA descriptor
171  **/
172 
173 typedef struct
174 {
175  uint32_t rd0;
176  uint32_t rd1;
177  uint32_t rd2;
178  uint32_t padding;
179 } S7g2RxDmaDesc;
180 
181 
182 //S7G2 Ethernet MAC driver
183 extern const NicDriver s7g2EthDriver;
184 
185 //S7G2 Ethernet MAC related functions
186 error_t s7g2EthInit(NetInterface *interface);
187 void s7g2EthInitGpio(NetInterface *interface);
188 void s7g2EthInitDmaDesc(NetInterface *interface);
189 
190 void s7g2EthTick(NetInterface *interface);
191 
192 void s7g2EthEnableIrq(NetInterface *interface);
193 void s7g2EthDisableIrq(NetInterface *interface);
194 void s7g2EthEventHandler(NetInterface *interface);
195 
197  const NetBuffer *buffer, size_t offset);
198 
200 
203 
204 void s7g2EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
205 uint16_t s7g2EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
206 
207 void s7g2EthWriteSmi(uint32_t data, uint_t length);
208 uint32_t s7g2EthReadSmi(uint_t length);
209 
210 //C++ guard
211 #ifdef __cplusplus
212  }
213 #endif
214 
215 #endif
error_t s7g2EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void s7g2EthEnableIrq(NetInterface *interface)
Enable interrupts.
error_t s7g2EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void s7g2EthTick(NetInterface *interface)
S7G2 Ethernet MAC timer handler.
Receive DMA descriptor.
uint16_t s7g2EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void s7g2EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint32_t s7g2EthReadSmi(uint_t length)
SMI read operation.
const NicDriver s7g2EthDriver
S7G2 Ethernet MAC driver.
void s7g2EthEventHandler(NetInterface *interface)
S7G2 Ethernet MAC event handler.
Transmit DMA descriptor.
void s7g2EthInitGpio(NetInterface *interface)
void s7g2EthDisableIrq(NetInterface *interface)
Disable interrupts.
NIC driver.
Definition: nic.h:161
void s7g2EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
error_t s7g2EthReceivePacket(NetInterface *interface)
Receive a packet.
uint16_t regAddr
error_t
Error codes.
Definition: error.h:40
unsigned int uint_t
Definition: compiler_port.h:43
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
error_t s7g2EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint8_t length
Definition: dtls_misc.h:140
Network interface controller abstraction layer.
void s7g2EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t s7g2EthInit(NetInterface *interface)
S7G2 Ethernet MAC initialization.