sama5d3_gigabit_eth_driver.c
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1 /**
2  * @file sama5d3_gigabit_eth_driver.c
3  * @brief SAMA5D3 Gigabit Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 //Switch to the appropriate trace level
30 #define TRACE_LEVEL NIC_TRACE_LEVEL
31 
32 //Dependencies
33 #include <limits.h>
34 #include "sama5d3x.h"
35 #include "core/net.h"
37 #include "debug.h"
38 
39 //Underlying network interface
40 static NetInterface *nicDriverInterface;
41 
42 //IAR EWARM compiler?
43 #if defined(__ICCARM__)
44 
45 //TX buffer
46 #pragma data_alignment = 8
47 #pragma location = ".ram_no_cache"
49 //RX buffer
50 #pragma data_alignment = 8
51 #pragma location = ".ram_no_cache"
53 //TX buffer descriptors
54 #pragma data_alignment = 8
55 #pragma location = ".ram_no_cache"
57 //RX buffer descriptors
58 #pragma data_alignment = 8
59 #pragma location = ".ram_no_cache"
61 
62 //GCC compiler?
63 #else
64 
65 //TX buffer
67  __attribute__((aligned(8), __section__(".ram_no_cache")));
68 //RX buffer
70  __attribute__((aligned(8), __section__(".ram_no_cache")));
71 //TX buffer descriptors
73  __attribute__((aligned(8), __section__(".ram_no_cache")));
74 //RX buffer descriptors
76  __attribute__((aligned(8), __section__(".ram_no_cache")));
77 
78 #endif
79 
80 //TX buffer index
81 static uint_t txBufferIndex;
82 //RX buffer index
83 static uint_t rxBufferIndex;
84 
85 
86 /**
87  * @brief SAMA5D3 Gigabit Ethernet MAC driver
88  **/
89 
91 {
93  ETH_MTU,
104  TRUE,
105  TRUE,
106  TRUE,
107  FALSE
108 };
109 
110 
111 /**
112  * @brief SAMA5D3 Gigabit Ethernet MAC initialization
113  * @param[in] interface Underlying network interface
114  * @return Error code
115  **/
116 
118 {
119  error_t error;
120  volatile uint32_t status;
121 
122  //Debug message
123  TRACE_INFO("Initializing SAMA5D3 Gigabit Ethernet MAC...\r\n");
124 
125  //Save underlying network interface
126  nicDriverInterface = interface;
127 
128  //Enable GMAC peripheral clock
129  PMC->PMC_PCER1 = (1 << (ID_GMAC - 32));
130  //Enable IRQ controller peripheral clock
131  PMC->PMC_PCER1 = (1 << (ID_IRQ - 32));
132 
133  //GPIO configuration
134  sama5d3GigabitEthInitGpio(interface);
135 
136  //Configure MDC clock speed
137  GMAC->GMAC_NCFGR = GMAC_NCFGR_DBW_DBW64 | GMAC_NCFGR_CLK_MCK_224;
138  //Enable management port (MDC and MDIO)
139  GMAC->GMAC_NCR |= GMAC_NCR_MPE;
140 
141  //PHY transceiver initialization
142  error = interface->phyDriver->init(interface);
143  //Failed to initialize PHY transceiver?
144  if(error)
145  return error;
146 
147  //Set the MAC address
148  GMAC->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
149  GMAC->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
150 
151  //Configure the receive filter
152  GMAC->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN;
153 
154  //Initialize hash table
155  GMAC->GMAC_HRB = 0;
156  GMAC->GMAC_HRT = 0;
157 
158  //Initialize buffer descriptors
160 
161  //Clear transmit status register
162  GMAC->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
163  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
164  //Clear receive status register
165  GMAC->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
166 
167  //First disable all GMAC interrupts
168  GMAC->GMAC_IDR = 0xFFFFFFFF;
169  //Only the desired ones are enabled
170  GMAC->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
171  GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
172 
173  //Read GMAC ISR register to clear any pending interrupt
174  status = GMAC->GMAC_ISR;
175 
176  //Configure interrupt controller
177  AIC->AIC_SSR = ID_GMAC;
178  AIC->AIC_SMR = AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE | AIC_SMR_PRIOR(SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY);
179  AIC->AIC_SVR = (uint32_t) sama5d3GigabitEthIrqHandler;
180 
181  //Enable the GMAC to transmit and receive data
182  GMAC->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
183 
184  //Accept any packets from the upper layer
185  osSetEvent(&interface->nicTxEvent);
186 
187  //Successful initialization
188  return NO_ERROR;
189 }
190 
191 
192 //SAMA5D3-Xplained evaluation board?
193 #if defined(USE_SAMA5D3_XPLAINED)
194 
195 /**
196  * @brief GPIO configuration
197  * @param[in] interface Underlying network interface
198  **/
199 
201 {
202  //Enable PIO peripheral clock
203  PMC->PMC_PCER0 = (1 << ID_PIOB);
204 
205  //Disable pull-up resistors on RGMII pins
206  PIOB->PIO_PUDR = GMAC_RGMII_MASK;
207  //Disable interrupts-on-change
208  PIOB->PIO_IDR = GMAC_RGMII_MASK;
209  //Assign MII pins to peripheral A function
210  PIOB->PIO_ABCDSR[0] &= ~GMAC_RGMII_MASK;
211  PIOB->PIO_ABCDSR[1] &= ~GMAC_RGMII_MASK;
212  //Disable the PIO from controlling the corresponding pins
213  PIOB->PIO_PDR = GMAC_RGMII_MASK;
214 
215  //Select RGMII operation mode
216  GMAC->GMAC_UR = GMAC_UR_RGMII;
217 }
218 
219 #endif
220 
221 
222 /**
223  * @brief Initialize buffer descriptors
224  * @param[in] interface Underlying network interface
225  **/
226 
228 {
229  uint_t i;
230  uint32_t address;
231 
232  //Initialize TX buffer descriptors
233  for(i = 0; i < SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT; i++)
234  {
235  //Calculate the address of the current TX buffer
236  address = (uint32_t) txBuffer[i];
237  //Write the address to the descriptor entry
238  txBufferDesc[i].address = address;
239  //Initialize status field
240  txBufferDesc[i].status = GMAC_TX_USED;
241  }
242 
243  //Mark the last descriptor entry with the wrap flag
244  txBufferDesc[i - 1].status |= GMAC_TX_WRAP;
245  //Initialize TX buffer index
246  txBufferIndex = 0;
247 
248  //Initialize RX buffer descriptors
249  for(i = 0; i < SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT; i++)
250  {
251  //Calculate the address of the current RX buffer
252  address = (uint32_t) rxBuffer[i];
253  //Write the address to the descriptor entry
254  rxBufferDesc[i].address = address & GMAC_RX_ADDRESS;
255  //Clear status field
256  rxBufferDesc[i].status = 0;
257  }
258 
259  //Mark the last descriptor entry with the wrap flag
260  rxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
261  //Initialize RX buffer index
262  rxBufferIndex = 0;
263 
264  //Start location of the TX descriptor list
265  GMAC->GMAC_TBQB = (uint32_t) txBufferDesc;
266  //Start location of the RX descriptor list
267  GMAC->GMAC_RBQB = (uint32_t) rxBufferDesc;
268 }
269 
270 
271 /**
272  * @brief SAMA5D3 Gigabit Ethernet MAC timer handler
273  *
274  * This routine is periodically called by the TCP/IP stack to
275  * handle periodic operations such as polling the link state
276  *
277  * @param[in] interface Underlying network interface
278  **/
279 
281 {
282  //Handle periodic operations
283  interface->phyDriver->tick(interface);
284 }
285 
286 
287 /**
288  * @brief Enable interrupts
289  * @param[in] interface Underlying network interface
290  **/
291 
293 {
294  //Enable Ethernet MAC interrupts
295  AIC->AIC_SSR = ID_GMAC;
296  AIC->AIC_IECR = AIC_IECR_INTEN;
297 
298  //Enable Ethernet PHY interrupts
299  interface->phyDriver->enableIrq(interface);
300 }
301 
302 
303 /**
304  * @brief Disable interrupts
305  * @param[in] interface Underlying network interface
306  **/
307 
309 {
310  //Disable Ethernet MAC interrupts
311  AIC->AIC_SSR = ID_GMAC;
312  AIC->AIC_IDCR = AIC_IDCR_INTD;
313 
314  //Disable Ethernet PHY interrupts
315  interface->phyDriver->disableIrq(interface);
316 }
317 
318 
319 /**
320  * @brief SAMA5D3 Gigabit Ethernet MAC interrupt service routine
321  **/
322 
324 {
325  bool_t flag;
326  volatile uint32_t isr;
327  volatile uint32_t tsr;
328  volatile uint32_t rsr;
329 
330  //Enter interrupt service routine
331  osEnterIsr();
332 
333  //This flag will be set if a higher priority task must be woken
334  flag = FALSE;
335 
336  //Each time the software reads GMAC_ISR, it has to check the
337  //contents of GMAC_TSR, GMAC_RSR and GMAC_NSR
338  isr = GMAC->GMAC_ISR;
339  tsr = GMAC->GMAC_TSR;
340  rsr = GMAC->GMAC_RSR;
341 
342  //A packet has been transmitted?
343  if(tsr & (GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
344  GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR))
345  {
346  //Only clear TSR flags that are currently set
347  GMAC->GMAC_TSR = tsr;
348 
349  //Avoid DMA lockup by sending only one frame at a time (see errata 57.5.1)
350  if((txBufferDesc[0].status & GMAC_TX_USED) &&
351  (txBufferDesc[1].status & GMAC_TX_USED))
352  {
353  //Notify the TCP/IP stack that the transmitter is ready to send
354  flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
355  }
356  }
357 
358  //A packet has been received?
359  if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
360  {
361  //Set event flag
362  nicDriverInterface->nicEvent = TRUE;
363  //Notify the TCP/IP stack of the event
364  flag |= osSetEventFromIsr(&netEvent);
365  }
366 
367  //Write AIC_EOICR register before exiting
368  AIC->AIC_EOICR = 0;
369 
370  //Leave interrupt service routine
371  osExitIsr(flag);
372 }
373 
374 
375 /**
376  * @brief SAMA5D3 Gigabit Ethernet MAC event handler
377  * @param[in] interface Underlying network interface
378  **/
379 
381 {
382  error_t error;
383  uint32_t rsr;
384 
385  //Read receive status
386  rsr = GMAC->GMAC_RSR;
387 
388  //Packet received?
389  if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
390  {
391  //Only clear RSR flags that are currently set
392  GMAC->GMAC_RSR = rsr;
393 
394  //Process all pending packets
395  do
396  {
397  //Read incoming packet
398  error = sama5d3GigabitEthReceivePacket(interface);
399 
400  //No more data in the receive buffer?
401  } while(error != ERROR_BUFFER_EMPTY);
402  }
403 }
404 
405 
406 /**
407  * @brief Send a packet
408  * @param[in] interface Underlying network interface
409  * @param[in] buffer Multi-part buffer containing the data to send
410  * @param[in] offset Offset to the first data byte
411  * @return Error code
412  **/
413 
415  const NetBuffer *buffer, size_t offset)
416 {
417  size_t length;
418 
419  //Retrieve the length of the packet
420  length = netBufferGetLength(buffer) - offset;
421 
422  //Check the frame length
424  {
425  //The transmitter can accept another packet
426  osSetEvent(&interface->nicTxEvent);
427  //Report an error
428  return ERROR_INVALID_LENGTH;
429  }
430 
431  //Make sure the current buffer is available for writing
432  if(!(txBufferDesc[txBufferIndex].status & GMAC_TX_USED))
433  return ERROR_FAILURE;
434 
435  //Copy user data to the transmit buffer
436  netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
437 
438  //Set the necessary flags in the descriptor entry
439  if(txBufferIndex < (SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT - 1))
440  {
441  //Write the status word
442  txBufferDesc[txBufferIndex].status =
444 
445  //Point to the next buffer
446  txBufferIndex++;
447  }
448  else
449  {
450  //Write the status word
451  txBufferDesc[txBufferIndex].status = GMAC_TX_WRAP |
453 
454  //Wrap around
455  txBufferIndex = 0;
456  }
457 
458  //Set the TSTART bit to initiate transmission
459  GMAC->GMAC_NCR |= GMAC_NCR_TSTART;
460 
461  //Check whether the next buffer is available for writing
462  if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
463  {
464  //The transmitter can accept another packet
465  osSetEvent(&interface->nicTxEvent);
466  }
467 
468  //Successful processing
469  return NO_ERROR;
470 }
471 
472 
473 /**
474  * @brief Receive a packet
475  * @param[in] interface Underlying network interface
476  * @return Error code
477  **/
478 
480 {
481  static uint8_t temp[ETH_MAX_FRAME_SIZE];
482  error_t error;
483  uint_t i;
484  uint_t j;
485  uint_t sofIndex;
486  uint_t eofIndex;
487  size_t n;
488  size_t size;
489  size_t length;
490 
491  //Initialize SOF and EOF indices
492  sofIndex = UINT_MAX;
493  eofIndex = UINT_MAX;
494 
495  //Search for SOF and EOF flags
496  for(i = 0; i < SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT; i++)
497  {
498  //Point to the current entry
499  j = rxBufferIndex + i;
500 
501  //Wrap around to the beginning of the buffer if necessary
504 
505  //No more entries to process?
506  if(!(rxBufferDesc[j].address & GMAC_RX_OWNERSHIP))
507  {
508  //Stop processing
509  break;
510  }
511  //A valid SOF has been found?
512  if(rxBufferDesc[j].status & GMAC_RX_SOF)
513  {
514  //Save the position of the SOF
515  sofIndex = i;
516  }
517  //A valid EOF has been found?
518  if((rxBufferDesc[j].status & GMAC_RX_EOF) && sofIndex != UINT_MAX)
519  {
520  //Save the position of the EOF
521  eofIndex = i;
522  //Retrieve the length of the frame
523  size = rxBufferDesc[j].status & GMAC_RX_LENGTH;
524  //Limit the number of data to read
525  size = MIN(size, ETH_MAX_FRAME_SIZE);
526  //Stop processing since we have reached the end of the frame
527  break;
528  }
529  }
530 
531  //Determine the number of entries to process
532  if(eofIndex != UINT_MAX)
533  j = eofIndex + 1;
534  else if(sofIndex != UINT_MAX)
535  j = sofIndex;
536  else
537  j = i;
538 
539  //Total number of bytes that have been copied from the receive buffer
540  length = 0;
541 
542  //Process incoming frame
543  for(i = 0; i < j; i++)
544  {
545  //Any data to copy from current buffer?
546  if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
547  {
548  //Calculate the number of bytes to read at a time
550  //Copy data from receive buffer
551  memcpy(temp + length, rxBuffer[rxBufferIndex], n);
552  //Update byte counters
553  length += n;
554  size -= n;
555  }
556 
557  //Mark the current buffer as free
558  rxBufferDesc[rxBufferIndex].address &= ~GMAC_RX_OWNERSHIP;
559 
560  //Point to the following entry
561  rxBufferIndex++;
562 
563  //Wrap around to the beginning of the buffer if necessary
564  if(rxBufferIndex >= SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT)
565  rxBufferIndex = 0;
566  }
567 
568  //Any packet to process?
569  if(length > 0)
570  {
571  //Pass the packet to the upper layer
572  nicProcessPacket(interface, temp, length);
573  //Valid packet received
574  error = NO_ERROR;
575  }
576  else
577  {
578  //No more data in the receive buffer
579  error = ERROR_BUFFER_EMPTY;
580  }
581 
582  //Return status code
583  return error;
584 }
585 
586 
587 /**
588  * @brief Configure MAC address filtering
589  * @param[in] interface Underlying network interface
590  * @return Error code
591  **/
592 
594 {
595  uint_t i;
596  uint_t k;
597  uint8_t *p;
598  uint32_t hashTable[2];
599  MacFilterEntry *entry;
600 
601  //Debug message
602  TRACE_DEBUG("Updating SAMA5D3 Gigabit hash table...\r\n");
603 
604  //Clear hash table
605  hashTable[0] = 0;
606  hashTable[1] = 0;
607 
608  //The MAC address filter contains the list of MAC addresses to accept
609  //when receiving an Ethernet frame
610  for(i = 0; i < MAC_ADDR_FILTER_SIZE; i++)
611  {
612  //Point to the current entry
613  entry = &interface->macAddrFilter[i];
614 
615  //Valid entry?
616  if(entry->refCount > 0)
617  {
618  //Point to the MAC address
619  p = entry->addr.b;
620 
621  //Apply the hash function
622  k = (p[0] >> 6) ^ p[0];
623  k ^= (p[1] >> 4) ^ (p[1] << 2);
624  k ^= (p[2] >> 2) ^ (p[2] << 4);
625  k ^= (p[3] >> 6) ^ p[3];
626  k ^= (p[4] >> 4) ^ (p[4] << 2);
627  k ^= (p[5] >> 2) ^ (p[5] << 4);
628 
629  //The hash value is reduced to a 6-bit index
630  k &= 0x3F;
631 
632  //Update hash table contents
633  hashTable[k / 32] |= (1 << (k % 32));
634  }
635  }
636 
637  //Write the hash table
638  GMAC->GMAC_HRB = hashTable[0];
639  GMAC->GMAC_HRT = hashTable[1];
640 
641  //Debug message
642  TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", GMAC->GMAC_HRB);
643  TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", GMAC->GMAC_HRT);
644 
645  //Successful processing
646  return NO_ERROR;
647 }
648 
649 
650 /**
651  * @brief Adjust MAC configuration parameters for proper operation
652  * @param[in] interface Underlying network interface
653  * @return Error code
654  **/
655 
657 {
658  uint32_t config;
659 
660  //Read network configuration register
661  config = GMAC->GMAC_NCFGR;
662 
663  //1000BASE-T operation mode?
664  if(interface->linkSpeed == NIC_LINK_SPEED_1GBPS)
665  {
666  config |= GMAC_NCFGR_GBE;
667  config &= ~GMAC_NCFGR_SPD;
668  }
669  //100BASE-TX operation mode?
670  else if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
671  {
672  config &= ~GMAC_NCFGR_GBE;
673  config |= GMAC_NCFGR_SPD;
674  }
675  //10BASE-T operation mode?
676  else
677  {
678  config &= ~GMAC_NCFGR_GBE;
679  config &= ~GMAC_NCFGR_SPD;
680  }
681 
682  //Half-duplex or full-duplex mode?
683  if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
684  config |= GMAC_NCFGR_FD;
685  else
686  config &= ~GMAC_NCFGR_FD;
687 
688  //Write configuration value back to NCFGR register
689  GMAC->GMAC_NCFGR = config;
690 
691  //Successful processing
692  return NO_ERROR;
693 }
694 
695 
696 /**
697  * @brief Write PHY register
698  * @param[in] phyAddr PHY address
699  * @param[in] regAddr Register address
700  * @param[in] data Register value
701  **/
702 
703 void sama5d3GigabitEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
704 {
705  uint32_t value;
706 
707  //Set up a write operation
708  value = GMAC_MAN_CLTTO | GMAC_MAN_OP(1) | GMAC_MAN_WTN(2);
709  //PHY address
710  value |= GMAC_MAN_PHYA(phyAddr);
711  //Register address
712  value |= GMAC_MAN_REGA(regAddr);
713  //Register value
714  value |= GMAC_MAN_DATA(data);
715 
716  //Start a write operation
717  GMAC->GMAC_MAN = value;
718  //Wait for the write to complete
719  while(!(GMAC->GMAC_NSR & GMAC_NSR_IDLE));
720 }
721 
722 
723 /**
724  * @brief Read PHY register
725  * @param[in] phyAddr PHY address
726  * @param[in] regAddr Register address
727  * @return Register value
728  **/
729 
730 uint16_t sama5d3GigabitEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
731 {
732  uint32_t value;
733 
734  //Set up a read operation
735  value = GMAC_MAN_CLTTO | GMAC_MAN_OP(2) | GMAC_MAN_WTN(2);
736  //PHY address
737  value |= GMAC_MAN_PHYA(phyAddr);
738  //Register address
739  value |= GMAC_MAN_REGA(regAddr);
740 
741  //Start a read operation
742  GMAC->GMAC_MAN = value;
743  //Wait for the read to complete
744  while(!(GMAC->GMAC_NSR & GMAC_NSR_IDLE));
745 
746  //Return PHY register contents
747  return GMAC->GMAC_MAN & GMAC_MAN_DATA_Msk;
748 }
void sama5d3GigabitEthInitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
#define GMAC_RX_SOF
MacAddr addr
MAC address.
Definition: ethernet.h:210
#define ETH_MAX_FRAME_SIZE
Definition: ethernet.h:80
void sama5d3GigabitEthTick(NetInterface *interface)
SAMA5D3 Gigabit Ethernet MAC timer handler.
TCP/IP stack core.
#define SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY
Debugging facilities.
uint8_t p
Definition: ndp.h:295
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:295
#define GMAC_RX_EOF
Generic error code.
Definition: error.h:43
#define SAMA5D3_GIGABIT_ETH_RX_BUFFER_SIZE
void sama5d3GigabitEthInitGpio(NetInterface *interface)
#define txBuffer
#define GMAC_TX_USED
void sama5d3GigabitEthIrqHandler(void)
SAMA5D3 Gigabit Ethernet MAC interrupt service routine.
void sama5d3GigabitEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
#define GMAC_TX_WRAP
SAMA5D3 Gigabit Ethernet MAC controller.
error_t sama5d3GigabitEthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
#define TRUE
Definition: os_port.h:48
#define MAC_ADDR_FILTER_SIZE
Definition: ethernet.h:65
Receive buffer descriptor.
error_t sama5d3GigabitEthReceivePacket(NetInterface *interface)
Receive a packet.
void sama5d3GigabitEthEventHandler(NetInterface *interface)
SAMA5D3 Gigabit Ethernet MAC event handler.
#define GMAC_TX_LAST
error_t sama5d3GigabitEthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Transmit buffer descriptor.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
Definition: net_mem.c:670
void sama5d3GigabitEthEnableIrq(NetInterface *interface)
Enable interrupts.
NIC driver.
Definition: nic.h:161
#define SAMA5D3_GIGABIT_ETH_RX_BUFFER_COUNT
const NicDriver sama5d3GigabitEthDriver
SAMA5D3 Gigabit Ethernet MAC driver.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
#define MIN(a, b)
Definition: os_port.h:60
#define GMAC_RX_OWNERSHIP
void sama5d3GigabitEthDisableIrq(NetInterface *interface)
Disable interrupts.
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
#define GMAC_RX_ADDRESS
error_t sama5d3GigabitEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
#define TRACE_INFO(...)
Definition: debug.h:86
uint16_t regAddr
#define ETH_MTU
Definition: ethernet.h:82
Ethernet interface.
Definition: nic.h:69
Success.
Definition: error.h:42
#define GMAC_RX_WRAP
#define rxBuffer
Ipv6Addr address
OsEvent netEvent
Definition: net.c:72
void nicProcessPacket(NetInterface *interface, void *packet, size_t length)
Handle a packet received by the network controller.
Definition: nic.c:239
uint_t refCount
Reference count for the current entry.
Definition: ethernet.h:211
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:40
uint16_t sama5d3GigabitEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
unsigned int uint_t
Definition: compiler_port.h:43
#define SAMA5D3_GIGABIT_ETH_TX_BUFFER_SIZE
uint8_t data[]
Definition: dtls_misc.h:167
#define SAMA5D3_GIGABIT_ETH_TX_BUFFER_COUNT
#define NetInterface
Definition: net.h:34
uint8_t value[]
Definition: dtls_misc.h:141
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
#define osExitIsr(flag)
#define osEnterIsr()
#define GMAC_RX_LENGTH
#define GMAC_TX_LENGTH
uint8_t length
Definition: dtls_misc.h:140
uint8_t n
#define GMAC_RGMII_MASK
#define FALSE
Definition: os_port.h:44
int bool_t
Definition: compiler_port.h:47
MAC filter table entry.
Definition: ethernet.h:208
error_t sama5d3GigabitEthInit(NetInterface *interface)
SAMA5D3 Gigabit Ethernet MAC initialization.
#define TRACE_DEBUG(...)
Definition: debug.h:98