stm32f107_eth_driver.h
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1 /**
2  * @file stm32f107_eth_driver.h
3  * @brief STM32F107 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _STM32F107_ETH_DRIVER_H
30 #define _STM32F107_ETH_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //Number of TX buffers
36 #ifndef STM32F107_ETH_TX_BUFFER_COUNT
37  #define STM32F107_ETH_TX_BUFFER_COUNT 2
38 #elif (STM32F107_ETH_TX_BUFFER_COUNT < 1)
39  #error STM32F107_ETH_TX_BUFFER_COUNT parameter is not valid
40 #endif
41 
42 //TX buffer size
43 #ifndef STM32F107_ETH_TX_BUFFER_SIZE
44  #define STM32F107_ETH_TX_BUFFER_SIZE 1536
45 #elif (STM32F107_ETH_TX_BUFFER_SIZE != 1536)
46  #error STM32F107_ETH_TX_BUFFER_SIZE parameter is not valid
47 #endif
48 
49 //Number of RX buffers
50 #ifndef STM32F107_ETH_RX_BUFFER_COUNT
51  #define STM32F107_ETH_RX_BUFFER_COUNT 4
52 #elif (STM32F107_ETH_RX_BUFFER_COUNT < 1)
53  #error STM32F107_ETH_RX_BUFFER_COUNT parameter is not valid
54 #endif
55 
56 //RX buffer size
57 #ifndef STM32F107_ETH_RX_BUFFER_SIZE
58  #define STM32F107_ETH_RX_BUFFER_SIZE 1536
59 #elif (STM32F107_ETH_RX_BUFFER_SIZE != 1536)
60  #error STM32F107_ETH_RX_BUFFER_SIZE parameter is not valid
61 #endif
62 
63 //Interrupt priority grouping
64 #ifndef STM32F107_ETH_IRQ_PRIORITY_GROUPING
65  #define STM32F107_ETH_IRQ_PRIORITY_GROUPING 3
66 #elif (STM32F107_ETH_IRQ_PRIORITY_GROUPING < 0)
67  #error STM32F107_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
68 #endif
69 
70 //Ethernet interrupt group priority
71 #ifndef STM32F107_ETH_IRQ_GROUP_PRIORITY
72  #define STM32F107_ETH_IRQ_GROUP_PRIORITY 12
73 #elif (STM32F107_ETH_IRQ_GROUP_PRIORITY < 0)
74  #error STM32F107_ETH_IRQ_GROUP_PRIORITY parameter is not valid
75 #endif
76 
77 //Ethernet interrupt subpriority
78 #ifndef STM32F107_ETH_IRQ_SUB_PRIORITY
79  #define STM32F107_ETH_IRQ_SUB_PRIORITY 0
80 #elif (STM32F107_ETH_IRQ_SUB_PRIORITY < 0)
81  #error STM32F107_ETH_IRQ_SUB_PRIORITY parameter is not valid
82 #endif
83 
84 //Transmit DMA descriptor flags
85 #define ETH_TDES0_OWN 0x80000000
86 #define ETH_TDES0_IC 0x40000000
87 #define ETH_TDES0_LS 0x20000000
88 #define ETH_TDES0_FS 0x10000000
89 #define ETH_TDES0_DC 0x08000000
90 #define ETH_TDES0_DP 0x04000000
91 #define ETH_TDES0_TTSE 0x02000000
92 #define ETH_TDES0_CIC 0x00C00000
93 #define ETH_TDES0_TER 0x00200000
94 #define ETH_TDES0_TCH 0x00100000
95 #define ETH_TDES0_TTSS 0x00020000
96 #define ETH_TDES0_IHE 0x00010000
97 #define ETH_TDES0_ES 0x00008000
98 #define ETH_TDES0_JT 0x00004000
99 #define ETH_TDES0_FF 0x00002000
100 #define ETH_TDES0_IPE 0x00001000
101 #define ETH_TDES0_LCA 0x00000800
102 #define ETH_TDES0_NC 0x00000400
103 #define ETH_TDES0_LCO 0x00000200
104 #define ETH_TDES0_EC 0x00000100
105 #define ETH_TDES0_VF 0x00000080
106 #define ETH_TDES0_CC 0x00000078
107 #define ETH_TDES0_ED 0x00000004
108 #define ETH_TDES0_UF 0x00000002
109 #define ETH_TDES0_DB 0x00000001
110 #define ETH_TDES1_TBS2 0x1FFF0000
111 #define ETH_TDES1_TBS1 0x00001FFF
112 #define ETH_TDES2_TBAP1 0xFFFFFFFF
113 #define ETH_TDES3_TBAP2 0xFFFFFFFF
114 
115 //Receive DMA descriptor flags
116 #define ETH_RDES0_OWN 0x80000000
117 #define ETH_RDES0_AFM 0x40000000
118 #define ETH_RDES0_FL 0x3FFF0000
119 #define ETH_RDES0_ES 0x00008000
120 #define ETH_RDES0_DE 0x00004000
121 #define ETH_RDES0_SAF 0x00002000
122 #define ETH_RDES0_LE 0x00001000
123 #define ETH_RDES0_OE 0x00000800
124 #define ETH_RDES0_VLAN 0x00000400
125 #define ETH_RDES0_FS 0x00000200
126 #define ETH_RDES0_LS 0x00000100
127 #define ETH_RDES0_IPHCE 0x00000080
128 #define ETH_RDES0_LCO 0x00000040
129 #define ETH_RDES0_FT 0x00000020
130 #define ETH_RDES0_RWT 0x00000010
131 #define ETH_RDES0_RE 0x00000008
132 #define ETH_RDES0_DBE 0x00000004
133 #define ETH_RDES0_CE 0x00000002
134 #define ETH_RDES0_PCE 0x00000001
135 #define ETH_RDES1_DIC 0x80000000
136 #define ETH_RDES1_RBS2 0x1FFF0000
137 #define ETH_RDES1_RER 0x00008000
138 #define ETH_RDES1_RCH 0x00004000
139 #define ETH_RDES1_RBS1 0x00001FFF
140 #define ETH_RDES2_RBAP1 0xFFFFFFFF
141 #define ETH_RDES3_RBAP2 0xFFFFFFFF
142 
143 //C++ guard
144 #ifdef __cplusplus
145  extern "C" {
146 #endif
147 
148 
149 /**
150  * @brief Transmit DMA descriptor
151  **/
152 
153 typedef struct
154 {
155  uint32_t tdes0;
156  uint32_t tdes1;
157  uint32_t tdes2;
158  uint32_t tdes3;
160 
161 
162 /**
163  * @brief Receive DMA descriptor
164  **/
165 
166 typedef struct
167 {
168  uint32_t rdes0;
169  uint32_t rdes1;
170  uint32_t rdes2;
171  uint32_t rdes3;
173 
174 
175 //STM32F107 Ethernet MAC driver
176 extern const NicDriver stm32f107EthDriver;
177 
178 //STM32F107 Ethernet MAC related functions
180 void stm32f107EthInitGpio(NetInterface *interface);
181 void stm32f107EthInitDmaDesc(NetInterface *interface);
182 
183 void stm32f107EthTick(NetInterface *interface);
184 
185 void stm32f107EthEnableIrq(NetInterface *interface);
186 void stm32f107EthDisableIrq(NetInterface *interface);
187 void stm32f107EthEventHandler(NetInterface *interface);
188 
190  const NetBuffer *buffer, size_t offset);
191 
193 
196 
197 void stm32f107EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
198 uint16_t stm32f107EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
199 
200 uint32_t stm32f107EthCalcCrc(const void *data, size_t length);
201 
202 //C++ guard
203 #ifdef __cplusplus
204  }
205 #endif
206 
207 #endif
uint16_t stm32f107EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void stm32f107EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t stm32f107EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
Transmit DMA descriptor.
void stm32f107EthEventHandler(NetInterface *interface)
STM32F107 Ethernet MAC event handler.
error_t stm32f107EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void stm32f107EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void stm32f107EthEnableIrq(NetInterface *interface)
Enable interrupts.
void stm32f107EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
Receive DMA descriptor.
const NicDriver stm32f107EthDriver
STM32F107 Ethernet MAC driver.
error_t stm32f107EthInit(NetInterface *interface)
STM32F107 Ethernet MAC initialization.
void stm32f107EthTick(NetInterface *interface)
STM32F107 Ethernet MAC timer handler.
NIC driver.
Definition: nic.h:161
uint32_t stm32f107EthCalcCrc(const void *data, size_t length)
CRC calculation.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
error_t stm32f107EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
uint16_t regAddr
error_t stm32f107EthReceivePacket(NetInterface *interface)
Receive a packet.
error_t
Error codes.
Definition: error.h:40
void stm32f107EthInitGpio(NetInterface *interface)
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint8_t length
Definition: dtls_misc.h:140
Network interface controller abstraction layer.