32 #define TRACE_LEVEL NIC_TRACE_LEVEL
44 #if defined(__ICCARM__)
47 #pragma data_alignment = 32
48 #pragma location = RA8_ETH_RAM_SECTION
51 #pragma data_alignment = 32
52 #pragma location = RA8_ETH_RAM_SECTION
55 #pragma data_alignment = 16
56 #pragma location = RA8_ETH_RAM_SECTION
59 #pragma data_alignment = 16
60 #pragma location = RA8_ETH_RAM_SECTION
123 TRACE_INFO(
"Initializing RA8 Ethernet MAC...\r\n");
126 nicDriverInterface = interface;
129 R_SYSTEM->PRCR = 0xA50B;
133 R_SYSTEM->PRCR = 0xA500;
144 if(interface->phyDriver != NULL)
147 error = interface->phyDriver->init(interface);
149 else if(interface->switchDriver != NULL)
152 error = interface->switchDriver->init(interface);
172 R_ETHERC0->IPGR = 0x14;
175 R_ETHERC0->MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
176 (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
179 R_ETHERC0->MALR = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
183 (0 << R_ETHERC_EDMAC_EDMR_DL_Pos);
190 (15 << R_ETHERC_EDMAC_FDR_RFD_Pos);
197 R_ETHERC_EDMAC_TRIMD_TIS_Msk;
200 R_ETHERC0->ECSIPR = 0;
204 R_ETHERC_EDMAC_EESIPR_FRIP_Msk;
214 R_ETHERC0->ECMR |= R_ETHERC0_ECMR_TE_Msk | R_ETHERC0_ECMR_RE_Msk;
235 #if defined(USE_EK_RA8D1)
237 R_SYSTEM->PRCR = 0xA50B;
239 R_SYSTEM->VBTICTLR &= ~R_SYSTEM_VBTICTLR_VCH0INEN_Msk;
241 R_SYSTEM->PRCR = 0xA500;
244 R_PMISC->PWPRS &= ~R_PMISC_PWPR_B0WI_Msk;
245 R_PMISC->PWPRS |= R_PMISC_PWPR_PFSWE_Msk;
248 R_PMISC->PFENET &= ~R_PMISC_PFENET_PHYMODE0_Msk;
251 R_PFS->PORT[4].PIN[1].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
252 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (1 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
255 R_PFS->PORT[4].PIN[2].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
256 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (1 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
259 R_PFS->PORT[4].PIN[5].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
260 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
263 R_PFS->PORT[4].PIN[6].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
264 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
267 R_PFS->PORT[7].PIN[0].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
268 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
271 R_PFS->PORT[7].PIN[1].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
272 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
275 R_PFS->PORT[7].PIN[2].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
276 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
279 R_PFS->PORT[7].PIN[3].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
280 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
283 R_PFS->PORT[7].PIN[4].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
284 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
287 R_PFS->PORT[7].PIN[5].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
288 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
291 R_PFS->PORT[7].PIN[6].PmnPFS = R_PFS_PORT_PIN_PmnPFS_PDR_Msk;
294 R_PMISC->PWPRS &= ~R_PMISC_PWPR_PFSWE_Msk;
295 R_PMISC->PWPRS |= R_PMISC_PWPR_B0WI_Msk;
298 R_PORT7->PCNTR3 = (1 << 6) << R_PORT0_PCNTR3_PORR_Pos;
300 R_PORT7->PCNTR3 = (1 << 6) << R_PORT0_PCNTR3_POSR_Pos;
304 #elif defined(USE_EK_RA8M1)
306 R_SYSTEM->PRCR = 0xA50B;
308 R_SYSTEM->VBTICTLR &= ~R_SYSTEM_VBTICTLR_VCH0INEN_Msk;
310 R_SYSTEM->PRCR = 0xA500;
313 R_PMISC->PWPRS &= ~R_PMISC_PWPR_B0WI_Msk;
314 R_PMISC->PWPRS |= R_PMISC_PWPR_PFSWE_Msk;
317 R_PMISC->PFENET &= ~R_PMISC_PFENET_PHYMODE0_Msk;
320 R_PFS->PORT[4].PIN[1].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
321 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (1 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
324 R_PFS->PORT[4].PIN[2].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
325 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (1 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
328 R_PFS->PORT[4].PIN[5].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
329 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
332 R_PFS->PORT[4].PIN[6].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
333 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
336 R_PFS->PORT[7].PIN[0].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
337 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
340 R_PFS->PORT[7].PIN[1].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
341 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
344 R_PFS->PORT[7].PIN[2].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
345 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
348 R_PFS->PORT[7].PIN[3].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
349 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
352 R_PFS->PORT[7].PIN[4].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
353 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
356 R_PFS->PORT[7].PIN[5].PmnPFS = (23 << R_PFS_PORT_PIN_PmnPFS_PSEL_Pos) |
357 R_PFS_PORT_PIN_PmnPFS_PMR_Msk | (3 << R_PFS_PORT_PIN_PmnPFS_DSCR_Pos);
360 R_PFS->PORT[4].PIN[4].PmnPFS = R_PFS_PORT_PIN_PmnPFS_PDR_Msk;
363 R_PMISC->PWPRS &= ~R_PMISC_PWPR_PFSWE_Msk;
364 R_PMISC->PWPRS |= R_PMISC_PWPR_B0WI_Msk;
367 R_PORT4->PCNTR3 = (1 << 4) << R_PORT0_PCNTR3_PORR_Pos;
369 R_PORT4->PCNTR3 = (1 << 4) << R_PORT0_PCNTR3_POSR_Pos;
439 if(interface->phyDriver != NULL)
442 interface->phyDriver->tick(interface);
444 else if(interface->switchDriver != NULL)
447 interface->switchDriver->tick(interface);
464 NVIC_EnableIRQ(EDMAC0_EINT_IRQn);
467 if(interface->phyDriver != NULL)
470 interface->phyDriver->enableIrq(interface);
472 else if(interface->switchDriver != NULL)
475 interface->switchDriver->enableIrq(interface);
492 NVIC_DisableIRQ(EDMAC0_EINT_IRQn);
495 if(interface->phyDriver != NULL)
498 interface->phyDriver->disableIrq(interface);
500 else if(interface->switchDriver != NULL)
503 interface->switchDriver->disableIrq(interface);
531 if((status & R_ETHERC_EDMAC_EESR_TWB_Msk) != 0)
545 if((status & R_ETHERC_EDMAC_EESR_FR_Msk) != 0)
551 nicDriverInterface->nicEvent =
TRUE;
557 R_ICU->IELSR[EDMAC0_EINT_IRQn] &= ~R_ICU_IELSR_IR_Msk;
749 if(interface->promiscuous)
752 R_ETHERC0->ECMR |= R_ETHERC0_ECMR_PRM_Msk;
757 R_ETHERC0->ECMR &= ~R_ETHERC0_ECMR_PRM_Msk;
760 R_ETHERC0->MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
761 (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];
764 R_ETHERC0->MALR = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];
767 acceptMulticast =
FALSE;
774 if(interface->macAddrFilter[i].refCount > 0)
777 acceptMulticast =
TRUE;
784 if(acceptMulticast || interface->acceptAllMulticast)
810 mode = R_ETHERC0->ECMR;
815 mode |= R_ETHERC0_ECMR_RTM_Msk;
819 mode &= ~R_ETHERC0_ECMR_RTM_Msk;
825 mode |= R_ETHERC0_ECMR_DM_Msk;
829 mode &= ~R_ETHERC0_ECMR_DM_Msk;
833 R_ETHERC0->ECMR = mode;
917 R_ETHERC0->PIR |= R_ETHERC0_PIR_MMD_Msk;
923 if((
data & 0x80000000) != 0)
925 R_ETHERC0->PIR |= R_ETHERC0_PIR_MDO_Msk;
929 R_ETHERC0->PIR &= ~R_ETHERC0_PIR_MDO_Msk;
934 R_ETHERC0->PIR |= R_ETHERC0_PIR_MDC_Msk;
937 R_ETHERC0->PIR &= ~R_ETHERC0_PIR_MDC_Msk;
956 R_ETHERC0->PIR &= ~R_ETHERC0_PIR_MMD_Msk;
965 R_ETHERC0->PIR |= R_ETHERC0_PIR_MDC_Msk;
968 R_ETHERC0->PIR &= ~R_ETHERC0_PIR_MDC_Msk;
972 if((R_ETHERC0->PIR & R_ETHERC0_PIR_MDI_Msk) != 0)
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define EDMAC_RD0_RFS_MASK
#define EDMAC_RD0_RFS_RMAF
#define R_MSTP_MSTPCRB_MSTPB15_Msk
#define EDMAC_TD0_TFP_EOF
#define EDMAC_RD0_RFP_EOF
#define EDMAC_RD0_RFP_SOF
#define EDMAC_TD0_TFP_SOF
void ra8EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t ra8EthInit(NetInterface *interface)
RA8 Ethernet MAC initialization.
void ra8EthEnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t ra8EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t ra8EthReceivePacket(NetInterface *interface)
Receive a packet.
void ra8EthTick(NetInterface *interface)
RA8 Ethernet MAC timer handler.
const NicDriver ra8EthDriver
RA8 Ethernet MAC driver.
error_t ra8EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void EDMAC0_EINT_IRQHandler(void)
RA8 Ethernet MAC interrupt service routine.
void ra8EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void ra8EthWriteSmi(uint32_t data, uint_t length)
SMI write operation.
void ra8EthDisableIrq(NetInterface *interface)
Disable interrupts.
error_t ra8EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint32_t ra8EthReadSmi(uint_t length)
SMI read operation.
void ra8EthEventHandler(NetInterface *interface)
RA8 Ethernet MAC event handler.
error_t ra8EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
__weak_func void ra8EthInitGpio(NetInterface *interface)
GPIO configuration.
Renesas RA8D1 / RA8M1 Ethernet MAC driver.
#define RA8_ETH_TX_BUFFER_COUNT
#define RA8_ETH_IRQ_GROUP_PRIORITY
#define RA8_ETH_RX_BUFFER_COUNT
#define RA8_ETH_IRQ_PRIORITY_GROUPING
#define RA8_ETH_RAM_SECTION
#define RA8_ETH_IRQ_SUB_PRIORITY
#define RA8_ETH_TX_BUFFER_SIZE
#define RA8_ETH_RX_BUFFER_SIZE
Structure describing a buffer that spans multiple chunks.