sama5d3_eth1_driver.h File Reference

SAMA5D3 Ethernet MAC driver (EMAC instance) More...

Go to the source code of this file.

Data Structures
struct	Sama5d3Eth1TxBufferDesc
	Transmit buffer descriptor. More...
struct	Sama5d3Eth1RxBufferDesc
	Receive buffer descriptor. More...

Macros
#define	SAMA5D3_ETH1_TX_BUFFER_COUNT   4
#define	SAMA5D3_ETH1_TX_BUFFER_SIZE   1536
#define	SAMA5D3_ETH1_RX_BUFFER_COUNT   96
#define	SAMA5D3_ETH1_RX_BUFFER_SIZE   128
#define	SAMA5D3_ETH1_IRQ_PRIORITY   0
#define	SAMA5D3_ETH1_RAM_SECTION   ".ram_no_cache"
#define	EMAC_RMII_MASK
#define	EMAC_TX_USED   0x80000000
#define	EMAC_TX_WRAP   0x40000000
#define	EMAC_TX_ERROR   0x20000000
#define	EMAC_TX_UNDERRUN   0x10000000
#define	EMAC_TX_EXHAUSTED   0x08000000
#define	EMAC_TX_NO_CRC   0x00010000
#define	EMAC_TX_LAST   0x00008000
#define	EMAC_TX_LENGTH   0x000007FF
#define	EMAC_RX_ADDRESS   0xFFFFFFFC
#define	EMAC_RX_WRAP   0x00000002
#define	EMAC_RX_OWNERSHIP   0x00000001
#define	EMAC_RX_BROADCAST   0x80000000
#define	EMAC_RX_MULTICAST_HASH   0x40000000
#define	EMAC_RX_UNICAST_HASH   0x20000000
#define	EMAC_RX_EXT_ADDR   0x10000000
#define	EMAC_RX_SAR1   0x04000000
#define	EMAC_RX_SAR2   0x02000000
#define	EMAC_RX_SAR3   0x01000000
#define	EMAC_RX_SAR4   0x00800000
#define	EMAC_RX_TYPE_ID   0x00400000
#define	EMAC_RX_VLAN_TAG   0x00200000
#define	EMAC_RX_PRIORITY_TAG   0x00100000
#define	EMAC_RX_VLAN_PRIORITY   0x000E0000
#define	EMAC_RX_CFI   0x00010000
#define	EMAC_RX_EOF   0x00008000
#define	EMAC_RX_SOF   0x00004000
#define	EMAC_RX_OFFSET   0x00003000
#define	EMAC_RX_LENGTH   0x00000FFF

Functions
error_t	sama5d3Eth1Init (NetInterface *interface)
	SAMA5D3 Ethernet MAC initialization. More...
void	sama5d3Eth1InitGpio (NetInterface *interface)
	GPIO configuration. More...
void	sama5d3Eth1InitBufferDesc (NetInterface *interface)
	Initialize buffer descriptors. More...
void	sama5d3Eth1Tick (NetInterface *interface)
	SAMA5D3 Ethernet MAC timer handler. More...
void	sama5d3Eth1EnableIrq (NetInterface *interface)
	Enable interrupts. More...
void	sama5d3Eth1DisableIrq (NetInterface *interface)
	Disable interrupts. More...
void	sama5d3Eth1IrqHandler (void)
	SAMA5D3 Ethernet MAC interrupt service routine. More...
void	sama5d3Eth1EventHandler (NetInterface *interface)
	SAMA5D3 Ethernet MAC event handler. More...
error_t	sama5d3Eth1SendPacket (NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
	Send a packet. More...
error_t	sama5d3Eth1ReceivePacket (NetInterface *interface)
	Receive a packet. More...
error_t	sama5d3Eth1UpdateMacAddrFilter (NetInterface *interface)
	Configure MAC address filtering. More...
error_t	sama5d3Eth1UpdateMacConfig (NetInterface *interface)
	Adjust MAC configuration parameters for proper operation. More...
void	sama5d3Eth1WritePhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
	Write PHY register. More...
uint16_t	sama5d3Eth1ReadPhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
	Read PHY register. More...

Variables
const NicDriver	sama5d3Eth1Driver
	SAMA5D3 Ethernet MAC driver (EMAC instance) More...

Detailed Description

SAMA5D3 Ethernet MAC driver (EMAC instance)

License

SPDX-License-Identifier: GPL-2.0-or-later

Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.

This file is part of CycloneTCP Open.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Author

Oryx Embedded SARL (www.oryx-embedded.com)

Version

2.4.0

Definition in file sama5d3_eth1_driver.h.

Macro Definition Documentation

EMAC_RMII_MASK

#define EMAC_RMII_MASK

Value:

   (PIO_PC9A_EMDIO | PIO_PC8A_EMDC | \
   PIO_PC7A_EREFCK | PIO_PC6A_ERXER | PIO_PC5A_ECRSDV | PIO_PC4A_ETXEN | \
   PIO_PC3A_ERX1 | PIO_PC2A_ERX0 | PIO_PC1A_ETX1 | PIO_PC0A_ETX0)

Definition at line 75 of file sama5d3_eth1_driver.h.

EMAC_RX_ADDRESS

#define EMAC_RX_ADDRESS   0xFFFFFFFC

Definition at line 90 of file sama5d3_eth1_driver.h.

EMAC_RX_BROADCAST

#define EMAC_RX_BROADCAST   0x80000000

Definition at line 93 of file sama5d3_eth1_driver.h.

EMAC_RX_CFI

#define EMAC_RX_CFI   0x00010000

Definition at line 105 of file sama5d3_eth1_driver.h.

EMAC_RX_EOF

#define EMAC_RX_EOF   0x00008000

Definition at line 106 of file sama5d3_eth1_driver.h.

EMAC_RX_EXT_ADDR

#define EMAC_RX_EXT_ADDR   0x10000000

Definition at line 96 of file sama5d3_eth1_driver.h.

EMAC_RX_LENGTH

#define EMAC_RX_LENGTH   0x00000FFF

Definition at line 109 of file sama5d3_eth1_driver.h.

EMAC_RX_MULTICAST_HASH

#define EMAC_RX_MULTICAST_HASH   0x40000000

Definition at line 94 of file sama5d3_eth1_driver.h.

EMAC_RX_OFFSET

#define EMAC_RX_OFFSET   0x00003000

Definition at line 108 of file sama5d3_eth1_driver.h.

EMAC_RX_OWNERSHIP

#define EMAC_RX_OWNERSHIP   0x00000001

Definition at line 92 of file sama5d3_eth1_driver.h.

EMAC_RX_PRIORITY_TAG

#define EMAC_RX_PRIORITY_TAG   0x00100000

Definition at line 103 of file sama5d3_eth1_driver.h.

EMAC_RX_SAR1

#define EMAC_RX_SAR1   0x04000000

Definition at line 97 of file sama5d3_eth1_driver.h.

EMAC_RX_SAR2

#define EMAC_RX_SAR2   0x02000000

Definition at line 98 of file sama5d3_eth1_driver.h.

EMAC_RX_SAR3

#define EMAC_RX_SAR3   0x01000000

Definition at line 99 of file sama5d3_eth1_driver.h.

EMAC_RX_SAR4

#define EMAC_RX_SAR4   0x00800000

Definition at line 100 of file sama5d3_eth1_driver.h.

EMAC_RX_SOF

#define EMAC_RX_SOF   0x00004000

Definition at line 107 of file sama5d3_eth1_driver.h.

EMAC_RX_TYPE_ID

#define EMAC_RX_TYPE_ID   0x00400000

Definition at line 101 of file sama5d3_eth1_driver.h.

EMAC_RX_UNICAST_HASH

#define EMAC_RX_UNICAST_HASH   0x20000000

Definition at line 95 of file sama5d3_eth1_driver.h.

EMAC_RX_VLAN_PRIORITY

#define EMAC_RX_VLAN_PRIORITY   0x000E0000

Definition at line 104 of file sama5d3_eth1_driver.h.

EMAC_RX_VLAN_TAG

#define EMAC_RX_VLAN_TAG   0x00200000

Definition at line 102 of file sama5d3_eth1_driver.h.

EMAC_RX_WRAP

#define EMAC_RX_WRAP   0x00000002

Definition at line 91 of file sama5d3_eth1_driver.h.

EMAC_TX_ERROR

#define EMAC_TX_ERROR   0x20000000

Definition at line 82 of file sama5d3_eth1_driver.h.

EMAC_TX_EXHAUSTED

#define EMAC_TX_EXHAUSTED   0x08000000

Definition at line 84 of file sama5d3_eth1_driver.h.

EMAC_TX_LAST

#define EMAC_TX_LAST   0x00008000

Definition at line 86 of file sama5d3_eth1_driver.h.

EMAC_TX_LENGTH

#define EMAC_TX_LENGTH   0x000007FF

Definition at line 87 of file sama5d3_eth1_driver.h.

EMAC_TX_NO_CRC

#define EMAC_TX_NO_CRC   0x00010000

Definition at line 85 of file sama5d3_eth1_driver.h.

EMAC_TX_UNDERRUN

#define EMAC_TX_UNDERRUN   0x10000000

Definition at line 83 of file sama5d3_eth1_driver.h.

EMAC_TX_USED

#define EMAC_TX_USED   0x80000000

Definition at line 80 of file sama5d3_eth1_driver.h.

EMAC_TX_WRAP

#define EMAC_TX_WRAP   0x40000000

Definition at line 81 of file sama5d3_eth1_driver.h.

SAMA5D3_ETH1_IRQ_PRIORITY

#define SAMA5D3_ETH1_IRQ_PRIORITY   0

Definition at line 64 of file sama5d3_eth1_driver.h.

SAMA5D3_ETH1_RAM_SECTION

#define SAMA5D3_ETH1_RAM_SECTION   ".ram_no_cache"

Definition at line 71 of file sama5d3_eth1_driver.h.

SAMA5D3_ETH1_RX_BUFFER_COUNT

#define SAMA5D3_ETH1_RX_BUFFER_COUNT   96

Definition at line 50 of file sama5d3_eth1_driver.h.

SAMA5D3_ETH1_RX_BUFFER_SIZE

#define SAMA5D3_ETH1_RX_BUFFER_SIZE   128

Definition at line 57 of file sama5d3_eth1_driver.h.

SAMA5D3_ETH1_TX_BUFFER_COUNT

#define SAMA5D3_ETH1_TX_BUFFER_COUNT   4

Definition at line 36 of file sama5d3_eth1_driver.h.

SAMA5D3_ETH1_TX_BUFFER_SIZE

#define SAMA5D3_ETH1_TX_BUFFER_SIZE   1536

Definition at line 43 of file sama5d3_eth1_driver.h.

Function Documentation

sama5d3Eth1DisableIrq()

void sama5d3Eth1DisableIrq

(

NetInterface *

interface

)

Disable interrupts.

Parameters

[in]

interface

Underlying network interface

Definition at line 362 of file sama5d3_eth1_driver.c.

sama5d3Eth1EnableIrq()

void sama5d3Eth1EnableIrq

(

NetInterface *

interface

)

Enable interrupts.

Parameters

[in]

interface

Underlying network interface

Definition at line 333 of file sama5d3_eth1_driver.c.

sama5d3Eth1EventHandler()

void sama5d3Eth1EventHandler

(

NetInterface *

interface

)

SAMA5D3 Ethernet MAC event handler.

Parameters

[in]

interface

Underlying network interface

Definition at line 447 of file sama5d3_eth1_driver.c.

sama5d3Eth1Init()

error_t sama5d3Eth1Init

(

NetInterface *

interface

)

SAMA5D3 Ethernet MAC initialization.

Parameters

[in]

interface

Underlying network interface

Returns

Error code

Definition at line 119 of file sama5d3_eth1_driver.c.

sama5d3Eth1InitBufferDesc()

void sama5d3Eth1InitBufferDesc

(

NetInterface *

interface

)

Initialize buffer descriptors.

Parameters

[in]

interface

Underlying network interface

Definition at line 255 of file sama5d3_eth1_driver.c.

sama5d3Eth1InitGpio()

void sama5d3Eth1InitGpio

(

NetInterface *

interface

)

GPIO configuration.

Parameters

[in]

interface

Underlying network interface

Definition at line 227 of file sama5d3_eth1_driver.c.

sama5d3Eth1IrqHandler()

void sama5d3Eth1IrqHandler

(

void

)

SAMA5D3 Ethernet MAC interrupt service routine.

Definition at line 390 of file sama5d3_eth1_driver.c.

sama5d3Eth1ReadPhyReg()

uint16_t sama5d3Eth1ReadPhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr
	)

Read PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)

Returns

Register value

Definition at line 922 of file sama5d3_eth1_driver.c.

sama5d3Eth1ReceivePacket()

error_t sama5d3Eth1ReceivePacket

(

NetInterface *

interface

)

Receive a packet.

Parameters

[in]

interface

Underlying network interface

Returns

Error code

Definition at line 550 of file sama5d3_eth1_driver.c.

sama5d3Eth1SendPacket()

error_t sama5d3Eth1SendPacket	(	NetInterface *	interface,
		const NetBuffer *	buffer,
		size_t	offset,
		NetTxAncillary *	ancillary
	)

Send a packet.

Parameters

[in]	interface	Underlying network interface
[in]	buffer	Multi-part buffer containing the data to send
[in]	offset	Offset to the first data byte
[in]	ancillary	Additional options passed to the stack along with the packet

Returns

Error code

Definition at line 483 of file sama5d3_eth1_driver.c.

sama5d3Eth1Tick()

void sama5d3Eth1Tick

(

NetInterface *

interface

)

SAMA5D3 Ethernet MAC timer handler.

This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state

Parameters

[in]

interface

Underlying network interface

Definition at line 308 of file sama5d3_eth1_driver.c.

sama5d3Eth1UpdateMacAddrFilter()

error_t sama5d3Eth1UpdateMacAddrFilter

(

NetInterface *

interface

)

Configure MAC address filtering.

Parameters

[in]

interface

Underlying network interface

Returns

Error code

Definition at line 682 of file sama5d3_eth1_driver.c.

sama5d3Eth1UpdateMacConfig()

error_t sama5d3Eth1UpdateMacConfig

(

NetInterface *

interface

)

Adjust MAC configuration parameters for proper operation.

Parameters

[in]

interface

Underlying network interface

Returns

Error code

Definition at line 840 of file sama5d3_eth1_driver.c.

sama5d3Eth1WritePhyReg()

void sama5d3Eth1WritePhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr,
		uint16_t	data
	)

Write PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)
[in]	data	Register value

Definition at line 883 of file sama5d3_eth1_driver.c.

Variable Documentation

sama5d3Eth1Driver

const NicDriver sama5d3Eth1Driver

extern

SAMA5D3 Ethernet MAC driver (EMAC instance)

Definition at line 92 of file sama5d3_eth1_driver.c.