32 #define TRACE_LEVEL NIC_TRACE_LEVEL
35 #include "stm32mp13xx.h"
36 #include "stm32mp13xx_hal.h"
41 #if defined(USE_STM32MP13XX_DK)
42 #include "stm32mp13xx_disco.h"
43 #include "stm32mp13xx_disco_io.h"
50 #if defined(__ICCARM__)
53 #pragma data_alignment = 4
54 #pragma location = STM32MP13XX_ETH1_RAM_SECTION
57 #pragma data_alignment = 4
58 #pragma location = STM32MP13XX_ETH1_RAM_SECTION
61 #pragma data_alignment = 8
62 #pragma location = STM32MP13XX_ETH1_RAM_SECTION
65 #pragma data_alignment = 8
66 #pragma location = STM32MP13XX_ETH1_RAM_SECTION
130 TRACE_INFO(
"Initializing STM32MP13 Ethernet MAC (ETH1)...\r\n");
133 nicDriverInterface = interface;
139 __HAL_RCC_ETH1CK_CLK_ENABLE();
140 __HAL_RCC_ETH1MAC_CLK_ENABLE();
141 __HAL_RCC_ETH1TX_CLK_ENABLE();
142 __HAL_RCC_ETH1RX_CLK_ENABLE();
145 __HAL_RCC_ETH1MAC_FORCE_RESET();
146 __HAL_RCC_ETH1MAC_RELEASE_RESET();
149 ETH->DMAMR |= ETH_DMAMR_SWR;
151 while((ETH->DMAMR & ETH_DMAMR_SWR) != 0)
156 ETH->MACMDIOAR = ETH_MACMDIOAR_CR_DIV124;
159 if(interface->phyDriver != NULL)
162 error = interface->phyDriver->init(interface);
164 else if(interface->switchDriver != NULL)
167 error = interface->switchDriver->init(interface);
182 ETH->MACCR = ETH_MACCR_GPSLCE | ETH_MACCR_DO;
185 temp = ETH->MACECR & ~ETH_MACECR_GPSL;
201 ETH->DMASBMR |= ETH_DMASBMR_AAL;
224 ETH->MMCTXIMR = ETH_MMCTXIMR_TXLPITRCIM | ETH_MMCTXIMR_TXLPIUSCIM |
225 ETH_MMCTXIMR_TXGPKTIM | ETH_MMCTXIMR_TXMCOLGPIM | ETH_MMCTXIMR_TXSCOLGPIM;
229 ETH->MMCRXIMR = ETH_MMCRXIMR_RXLPITRCIM | ETH_MMCRXIMR_RXLPIUSCIM |
230 ETH_MMCRXIMR_RXUCGPIM | ETH_MMCRXIMR_RXALGNERPIM | ETH_MMCRXIMR_RXCRCERPIM;
235 ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE;
241 ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
244 ETH->DMAC0TXCR |= ETH_DMAC0TXCR_ST;
245 ETH->DMAC0RXCR |= ETH_DMAC0RXCR_SR;
263 #if defined(USE_STM32MP13XX_DK)
264 GPIO_InitTypeDef GPIO_InitStructure;
265 BSP_IO_Init_t IO_InitStructure;
268 __HAL_RCC_SYSCFG_CLK_ENABLE();
271 __HAL_RCC_GPIOA_CLK_ENABLE();
272 __HAL_RCC_GPIOB_CLK_ENABLE();
273 __HAL_RCC_GPIOC_CLK_ENABLE();
274 __HAL_RCC_GPIOG_CLK_ENABLE();
277 HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH1_RMII);
280 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
281 GPIO_InitStructure.Pull = GPIO_NOPULL;
282 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
285 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2;
286 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
287 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
290 GPIO_InitStructure.Pin = GPIO_PIN_11;
291 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
292 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
295 GPIO_InitStructure.Pin = GPIO_PIN_1;
296 GPIO_InitStructure.Alternate = GPIO_AF10_ETH;
297 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
300 GPIO_InitStructure.Pin = GPIO_PIN_4 | GPIO_PIN_5;
301 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
302 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
305 GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_13 | GPIO_PIN_14;
306 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
307 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
310 IO_InitStructure.Pin = MCP23x17_GPIO_PIN_9;
311 IO_InitStructure.Pull = IO_NOPULL;
312 IO_InitStructure.Mode = IO_MODE_OUTPUT_PP;
313 BSP_IO_Init(0, &IO_InitStructure);
316 BSP_IO_WritePin(0, MCP23x17_GPIO_PIN_9, IO_PIN_RESET);
318 BSP_IO_WritePin(0, MCP23x17_GPIO_PIN_9, IO_PIN_SET);
360 ETH->DMAC0TXDLAR = (uint32_t) &
txDmaDesc[0];
365 ETH->DMAC0RXDLAR = (uint32_t) &
rxDmaDesc[0];
383 if(interface->phyDriver != NULL)
386 interface->phyDriver->tick(interface);
388 else if(interface->switchDriver != NULL)
391 interface->switchDriver->tick(interface);
408 IRQ_Enable(ETH1_IRQn);
411 if(interface->phyDriver != NULL)
414 interface->phyDriver->enableIrq(interface);
416 else if(interface->switchDriver != NULL)
419 interface->switchDriver->enableIrq(interface);
436 IRQ_Disable(ETH1_IRQn);
439 if(interface->phyDriver != NULL)
442 interface->phyDriver->disableIrq(interface);
444 else if(interface->switchDriver != NULL)
447 interface->switchDriver->disableIrq(interface);
472 status = ETH->DMAC0SR;
475 if((status & ETH_DMAC0SR_TI) != 0)
478 ETH->DMAC0SR = ETH_DMAC0SR_TI;
489 if((status & ETH_DMAC0SR_RI) != 0)
492 ETH->DMAC0SR = ETH_DMAC0SR_RI;
495 nicDriverInterface->nicEvent =
TRUE;
501 ETH->DMAC0SR = ETH_DMAC0SR_NIS;
577 ETH->DMAC0SR = ETH_DMAC0SR_TBU;
579 ETH->DMAC0TXDTPR = 0;
669 ETH->DMAC0SR = ETH_DMAC0SR_RBU;
671 ETH->DMAC0RXDTPR = 0;
690 uint32_t hashTable[2];
698 if(interface->promiscuous)
701 ETH->MACPFR = ETH_MACPFR_PR;
706 ETH->MACA0LR = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
707 ETH->MACA0HR = interface->macAddr.w[2];
723 entry = &interface->macAddrFilter[i];
736 k = (crc >> 26) & 0x3F;
739 hashTable[k / 32] |= (1 << (k % 32));
747 unicastMacAddr[j++] = entry->
addr;
757 ETH->MACA1LR = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
758 ETH->MACA1HR = unicastMacAddr[0].w[2] | ETH_MACA1HR_AE;
771 ETH->MACA2LR = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
772 ETH->MACA2HR = unicastMacAddr[1].w[2] | ETH_MACA2HR_AE;
785 ETH->MACA3LR = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
786 ETH->MACA3HR = unicastMacAddr[2].w[2] | ETH_MACA3HR_AE;
797 if(interface->acceptAllMulticast)
800 ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_PM;
805 ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC;
808 ETH->MACHT0R = hashTable[0];
809 ETH->MACHT1R = hashTable[1];
812 TRACE_DEBUG(
" MACHT0R = %08" PRIX32
"\r\n", ETH->MACHT0R);
813 TRACE_DEBUG(
" MACHT1R = %08" PRIX32
"\r\n", ETH->MACHT1R);
838 config &= ~ETH_MACCR_PS;
839 config &= ~ETH_MACCR_FES;
844 config |= ETH_MACCR_PS;
845 config |= ETH_MACCR_FES;
850 config |= ETH_MACCR_PS;
851 config &= ~ETH_MACCR_FES;
857 config |= ETH_MACCR_DM;
861 config &= ~ETH_MACCR_DM;
889 temp = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
893 temp |= (phyAddr << 21) & ETH_MACMDIOAR_PA;
895 temp |= (
regAddr << 16) & ETH_MACMDIOAR_RDA;
898 ETH->MACMDIODR =
data & ETH_MACMDIODR_GD;
901 ETH->MACMDIOAR = temp;
903 while((ETH->MACMDIOAR & ETH_MACMDIOAR_GB) != 0)
932 temp = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
936 temp |= (phyAddr << 21) & ETH_MACMDIOAR_PA;
938 temp |= (
regAddr << 16) & ETH_MACMDIOAR_RDA;
941 ETH->MACMDIOAR = temp;
943 while((ETH->MACMDIOAR & ETH_MACMDIOAR_GB) != 0)
948 data = ETH->MACMDIODR & ETH_MACMDIODR_GD;
976 p = (uint8_t *)
data;
981 for(i = 0; i <
length; i++)
984 for(j = 0; j < 8; j++)
987 if((((crc >> 31) ^ (
p[i] >> j)) & 0x01) != 0)
989 crc = (crc << 1) ^ 0x04C11DB7;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
const MacAddr MAC_UNSPECIFIED_ADDR
#define macIsMulticastAddr(macAddr)
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
#define osMemcpy(dest, src, length)
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
void stm32mp13xxEth1InitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void stm32mp13xxEth1Tick(NetInterface *interface)
STM32MP13 Ethernet MAC timer handler.
uint16_t stm32mp13xxEth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
error_t stm32mp13xxEth1UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
error_t stm32mp13xxEth1SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void stm32mp13xxEth1EventHandler(NetInterface *interface)
STM32MP13 Ethernet MAC event handler.
const NicDriver stm32mp13xxEth1Driver
STM32MP13 Ethernet MAC driver (ETH1 instance)
void stm32mp13xxEth1EnableIrq(NetInterface *interface)
Enable interrupts.
void stm32mp13xxEth1WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t stm32mp13xxEth1ReceivePacket(NetInterface *interface)
Receive a packet.
__weak_func void stm32mp13xxEth1InitGpio(NetInterface *interface)
GPIO configuration.
error_t stm32mp13xxEth1UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint32_t stm32mp13xxEth1CalcCrc(const void *data, size_t length)
CRC calculation.
void ETH1_IRQHandler(void)
STM32MP13 Ethernet MAC interrupt service routine.
error_t stm32mp13xxEth1Init(NetInterface *interface)
STM32MP13 Ethernet MAC initialization.
void stm32mp13xxEth1DisableIrq(NetInterface *interface)
Disable interrupts.
STM32MP13 Gigabit Ethernet MAC driver (ETH1 instance)
#define ETH_MTLTXQ0OMR_TQS_Val(n)
#define STM32MP13XX_ETH1_IRQ_PRIORITY
#define ETH_DMAC0TXCR_TXPBL_Val(n)
#define ETH_DMAC0RXCR_RBSZ_Val(n)
#define STM32MP13XX_ETH1_TX_BUFFER_SIZE
#define ETH_DMAC0CR_DSL_Val(n)
#define ETH_DMAMR_TXPR_Val(n)
#define ETH_MTLTXQ0OMR_TXQEN_Val(n)
#define ETH_MTLRXQ0OMR_RQS_Val(n)
#define STM32MP13XX_ETH1_TX_BUFFER_COUNT
#define ETH_DMAC0RXCR_RXPBL_Val(n)
#define STM32MP13XX_ETH1_RAM_SECTION
#define ETH_DMAMR_INTM_Val(n)
#define STM32MP13XX_ETH1_RX_BUFFER_SIZE
#define STM32MP13XX_ETH1_RX_BUFFER_COUNT
#define ETH_MACRXQC0R_RXQ0EN_Val(n)
#define ETH_MACMDIOAR_GOC_Val(n)
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.