32 #define TRACE_LEVEL NIC_TRACE_LEVEL
35 #include "stm32mp13xx.h"
36 #include "stm32mp13xx_hal.h"
41 #if defined(USE_STM32MP13XX_DK)
42 #include "stm32mp13xx_disco.h"
43 #include "stm32mp13xx_disco_io.h"
50 #if defined(__ICCARM__)
53 #pragma data_alignment = 4
54 #pragma location = STM32MP13XX_ETH2_RAM_SECTION
57 #pragma data_alignment = 4
58 #pragma location = STM32MP13XX_ETH2_RAM_SECTION
61 #pragma data_alignment = 8
62 #pragma location = STM32MP13XX_ETH2_RAM_SECTION
65 #pragma data_alignment = 8
66 #pragma location = STM32MP13XX_ETH2_RAM_SECTION
130 TRACE_INFO(
"Initializing STM32MP13 Ethernet MAC (ETH2)...\r\n");
133 nicDriverInterface = interface;
139 __HAL_RCC_ETH2CK_CLK_ENABLE();
140 __HAL_RCC_ETH2MAC_CLK_ENABLE();
141 __HAL_RCC_ETH2TX_CLK_ENABLE();
142 __HAL_RCC_ETH2RX_CLK_ENABLE();
145 __HAL_RCC_ETH2MAC_FORCE_RESET();
146 __HAL_RCC_ETH2MAC_RELEASE_RESET();
149 ETH2->DMAMR |= ETH_DMAMR_SWR;
151 while((ETH2->DMAMR & ETH_DMAMR_SWR) != 0)
156 ETH2->MACMDIOAR = ETH_MACMDIOAR_CR_DIV124;
159 if(interface->phyDriver != NULL)
162 error = interface->phyDriver->init(interface);
164 else if(interface->switchDriver != NULL)
167 error = interface->switchDriver->init(interface);
182 ETH2->MACCR = ETH_MACCR_GPSLCE | ETH_MACCR_DO;
185 temp = ETH2->MACECR & ~ETH_MACECR_GPSL;
192 ETH2->MACQ0TXFCR = 0;
201 ETH2->DMASBMR |= ETH_DMASBMR_AAL;
224 ETH2->MMCTXIMR = ETH_MMCTXIMR_TXLPITRCIM | ETH_MMCTXIMR_TXLPIUSCIM |
225 ETH_MMCTXIMR_TXGPKTIM | ETH_MMCTXIMR_TXMCOLGPIM | ETH_MMCTXIMR_TXSCOLGPIM;
229 ETH2->MMCRXIMR = ETH_MMCRXIMR_RXLPITRCIM | ETH_MMCRXIMR_RXLPIUSCIM |
230 ETH_MMCRXIMR_RXUCGPIM | ETH_MMCRXIMR_RXALGNERPIM | ETH_MMCRXIMR_RXCRCERPIM;
235 ETH2->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE;
241 ETH2->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
244 ETH2->DMAC0TXCR |= ETH_DMAC0TXCR_ST;
245 ETH2->DMAC0RXCR |= ETH_DMAC0RXCR_SR;
263 #if defined(USE_STM32MP13XX_DK)
264 GPIO_InitTypeDef GPIO_InitStructure;
265 BSP_IO_Init_t IO_InitStructure;
268 __HAL_RCC_SYSCFG_CLK_ENABLE();
271 __HAL_RCC_GPIOA_CLK_ENABLE();
272 __HAL_RCC_GPIOB_CLK_ENABLE();
273 __HAL_RCC_GPIOE_CLK_ENABLE();
274 __HAL_RCC_GPIOF_CLK_ENABLE();
275 __HAL_RCC_GPIOG_CLK_ENABLE();
278 GPIO_InitStructure.Pin = GPIO_PIN_8;
279 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
280 GPIO_InitStructure.Pull = GPIO_NOPULL;
281 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
282 GPIO_InitStructure.Alternate = GPIO_AF13_ETH2;
283 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
286 HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH2_RMII);
288 SYSCFG->PMCSETR = SYSCFG_PMCSETR_ETH2_REF_CLK_SEL;
291 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
292 GPIO_InitStructure.Pull = GPIO_NOPULL;
293 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
296 GPIO_InitStructure.Pin = GPIO_PIN_12;
297 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
298 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
301 GPIO_InitStructure.Pin = GPIO_PIN_2;
302 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
303 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
306 GPIO_InitStructure.Pin = GPIO_PIN_2;
307 GPIO_InitStructure.Alternate = GPIO_AF10_ETH;
308 HAL_GPIO_Init(GPIOE, &GPIO_InitStructure);
311 GPIO_InitStructure.Pin = GPIO_PIN_4 | GPIO_PIN_6 | GPIO_PIN_7;
312 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
313 HAL_GPIO_Init(GPIOF, &GPIO_InitStructure);
316 GPIO_InitStructure.Pin = GPIO_PIN_5 | GPIO_PIN_11;
317 GPIO_InitStructure.Alternate = GPIO_AF10_ETH;
318 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
321 IO_InitStructure.Pin = MCP23x17_GPIO_PIN_10;
322 IO_InitStructure.Pull = IO_NOPULL;
323 IO_InitStructure.Mode = IO_MODE_OUTPUT_PP;
324 BSP_IO_Init(0, &IO_InitStructure);
327 BSP_IO_WritePin(0, MCP23x17_GPIO_PIN_10, IO_PIN_RESET);
329 BSP_IO_WritePin(0, MCP23x17_GPIO_PIN_10, IO_PIN_SET);
371 ETH2->DMAC0TXDLAR = (uint32_t) &
txDmaDesc[0];
376 ETH2->DMAC0RXDLAR = (uint32_t) &
rxDmaDesc[0];
394 if(interface->phyDriver != NULL)
397 interface->phyDriver->tick(interface);
399 else if(interface->switchDriver != NULL)
402 interface->switchDriver->tick(interface);
419 IRQ_Enable(ETH2_IRQn);
422 if(interface->phyDriver != NULL)
425 interface->phyDriver->enableIrq(interface);
427 else if(interface->switchDriver != NULL)
430 interface->switchDriver->enableIrq(interface);
447 IRQ_Disable(ETH2_IRQn);
450 if(interface->phyDriver != NULL)
453 interface->phyDriver->disableIrq(interface);
455 else if(interface->switchDriver != NULL)
458 interface->switchDriver->disableIrq(interface);
483 status = ETH2->DMAC0SR;
486 if((status & ETH_DMAC0SR_TI) != 0)
489 ETH2->DMAC0SR = ETH_DMAC0SR_TI;
500 if((status & ETH_DMAC0SR_RI) != 0)
503 ETH2->DMAC0SR = ETH_DMAC0SR_RI;
506 nicDriverInterface->nicEvent =
TRUE;
512 ETH2->DMAC0SR = ETH_DMAC0SR_NIS;
588 ETH2->DMAC0SR = ETH_DMAC0SR_TBU;
590 ETH2->DMAC0TXDTPR = 0;
680 ETH2->DMAC0SR = ETH_DMAC0SR_RBU;
682 ETH2->DMAC0RXDTPR = 0;
701 uint32_t hashTable[2];
709 if(interface->promiscuous)
712 ETH2->MACPFR = ETH_MACPFR_PR;
717 ETH2->MACA0LR = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
718 ETH2->MACA0HR = interface->macAddr.w[2];
734 entry = &interface->macAddrFilter[i];
747 k = (crc >> 26) & 0x3F;
750 hashTable[k / 32] |= (1 << (k % 32));
758 unicastMacAddr[j++] = entry->
addr;
768 ETH2->MACA1LR = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16);
769 ETH2->MACA1HR = unicastMacAddr[0].w[2] | ETH_MACA1HR_AE;
782 ETH2->MACA2LR = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16);
783 ETH2->MACA2HR = unicastMacAddr[1].w[2] | ETH_MACA2HR_AE;
796 ETH2->MACA3LR = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16);
797 ETH2->MACA3HR = unicastMacAddr[2].w[2] | ETH_MACA3HR_AE;
808 if(interface->acceptAllMulticast)
811 ETH2->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_PM;
816 ETH2->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC;
819 ETH2->MACHT0R = hashTable[0];
820 ETH2->MACHT1R = hashTable[1];
823 TRACE_DEBUG(
" MACHT0R = %08" PRIX32
"\r\n", ETH2->MACHT0R);
824 TRACE_DEBUG(
" MACHT1R = %08" PRIX32
"\r\n", ETH2->MACHT1R);
844 config = ETH2->MACCR;
849 config &= ~ETH_MACCR_PS;
850 config &= ~ETH_MACCR_FES;
855 config |= ETH_MACCR_PS;
856 config |= ETH_MACCR_FES;
861 config |= ETH_MACCR_PS;
862 config &= ~ETH_MACCR_FES;
868 config |= ETH_MACCR_DM;
872 config &= ~ETH_MACCR_DM;
876 ETH2->MACCR = config;
900 temp = ETH2->MACMDIOAR & ETH_MACMDIOAR_CR;
904 temp |= (phyAddr << 21) & ETH_MACMDIOAR_PA;
906 temp |= (
regAddr << 16) & ETH_MACMDIOAR_RDA;
909 ETH2->MACMDIODR =
data & ETH_MACMDIODR_GD;
912 ETH2->MACMDIOAR = temp;
914 while((ETH2->MACMDIOAR & ETH_MACMDIOAR_GB) != 0)
943 temp = ETH2->MACMDIOAR & ETH_MACMDIOAR_CR;
947 temp |= (phyAddr << 21) & ETH_MACMDIOAR_PA;
949 temp |= (
regAddr << 16) & ETH_MACMDIOAR_RDA;
952 ETH2->MACMDIOAR = temp;
954 while((ETH2->MACMDIOAR & ETH_MACMDIOAR_GB) != 0)
959 data = ETH2->MACMDIODR & ETH_MACMDIODR_GD;
987 p = (uint8_t *)
data;
992 for(i = 0; i <
length; i++)
995 for(j = 0; j < 8; j++)
998 if((((crc >> 31) ^ (
p[i] >> j)) & 0x01) != 0)
1000 crc = (crc << 1) ^ 0x04C11DB7;
__attribute__((naked))
AVR32 Ethernet MAC interrupt wrapper.
@ ERROR_FAILURE
Generic error code.
const MacAddr MAC_UNSPECIFIED_ADDR
#define macIsMulticastAddr(macAddr)
#define MAC_ADDR_FILTER_SIZE
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
size_t netBufferRead(void *dest, const NetBuffer *src, size_t srcOffset, size_t length)
Read data from a multi-part buffer.
const NetRxAncillary NET_DEFAULT_RX_ANCILLARY
void nicProcessPacket(NetInterface *interface, uint8_t *packet, size_t length, NetRxAncillary *ancillary)
Handle a packet received by the network controller.
@ NIC_TYPE_ETHERNET
Ethernet interface.
#define osMemcpy(dest, src, length)
bool_t osSetEventFromIsr(OsEvent *event)
Set an event object to the signaled state from an interrupt service routine.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
#define ETH_MTLTXQ0OMR_TQS_Val(n)
#define ETH_DMAC0TXCR_TXPBL_Val(n)
#define ETH_DMAC0RXCR_RBSZ_Val(n)
#define ETH_DMAC0CR_DSL_Val(n)
#define ETH_DMAMR_TXPR_Val(n)
#define ETH_MTLTXQ0OMR_TXQEN_Val(n)
#define ETH_MTLRXQ0OMR_RQS_Val(n)
#define ETH_DMAC0RXCR_RXPBL_Val(n)
#define ETH_DMAMR_INTM_Val(n)
#define ETH_MACRXQC0R_RXQ0EN_Val(n)
#define ETH_MACMDIOAR_GOC_Val(n)
void stm32mp13xxEth2Tick(NetInterface *interface)
STM32MP13 Ethernet MAC timer handler.
error_t stm32mp13xxEth2UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t stm32mp13xxEth2SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void stm32mp13xxEth2EnableIrq(NetInterface *interface)
Enable interrupts.
void ETH2_IRQHandler(void)
STM32MP13 Ethernet MAC interrupt service routine.
error_t stm32mp13xxEth2ReceivePacket(NetInterface *interface)
Receive a packet.
uint16_t stm32mp13xxEth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
__weak_func void stm32mp13xxEth2InitGpio(NetInterface *interface)
GPIO configuration.
void stm32mp13xxEth2WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
void stm32mp13xxEth2DisableIrq(NetInterface *interface)
Disable interrupts.
uint32_t stm32mp13xxEth2CalcCrc(const void *data, size_t length)
CRC calculation.
error_t stm32mp13xxEth2Init(NetInterface *interface)
STM32MP13 Ethernet MAC initialization.
const NicDriver stm32mp13xxEth2Driver
STM32MP13 Ethernet MAC driver (ETH2 instance)
void stm32mp13xxEth2InitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
error_t stm32mp13xxEth2UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void stm32mp13xxEth2EventHandler(NetInterface *interface)
STM32MP13 Ethernet MAC event handler.
STM32MP13 Gigabit Ethernet MAC driver (ETH2 instance)
#define STM32MP13XX_ETH2_RAM_SECTION
#define STM32MP13XX_ETH2_TX_BUFFER_SIZE
#define STM32MP13XX_ETH2_IRQ_PRIORITY
#define STM32MP13XX_ETH2_RX_BUFFER_COUNT
#define STM32MP13XX_ETH2_RX_BUFFER_SIZE
#define STM32MP13XX_ETH2_TX_BUFFER_COUNT
uint_t refCount
Reference count for the current entry.
Structure describing a buffer that spans multiple chunks.