ar8035_driver.h
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1 /**
2  * @file ar8035_driver.h
3  * @brief AR8035 Gigabit Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _AR8035_DRIVER_H
30 #define _AR8035_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef AR8035_PHY_ADDR
37  #define AR8035_PHY_ADDR 0
38 #elif (AR8035_PHY_ADDR < 0 || AR8035_PHY_ADDR > 31)
39  #error AR8035_PHY_ADDR parameter is not valid
40 #endif
41 
42 //AR8035 registers
43 #define AR8035_PHY_REG_BMCR 0x00
44 #define AR8035_PHY_REG_BMSR 0x01
45 #define AR8035_PHY_REG_PHYIDR1 0x02
46 #define AR8035_PHY_REG_PHYIDR2 0x03
47 #define AR8035_PHY_REG_ANAR 0x04
48 #define AR8035_PHY_REG_ANLPAR 0x05
49 #define AR8035_PHY_REG_ANER 0x06
50 #define AR8035_PHY_REG_ANNPTR 0x07
51 #define AR8035_PHY_REG_LPNPAR 0x08
52 #define AR8035_PHY_REG_1000BT_CTRL 0x09
53 #define AR8035_PHY_REG_1000BT_STATUS 0x0A
54 #define AR8035_PHY_REG_MMD_CTRL 0x0D
55 #define AR8035_PHY_REG_MMD_DATA 0x0E
56 #define AR8035_PHY_REG_EXT_STATUS 0x0F
57 #define AR8035_PHY_REG_FUNCTION_CTRL 0x10
58 #define AR8035_PHY_REG_PHY_STATUS 0x11
59 #define AR8035_PHY_REG_INT_EN 0x12
60 #define AR8035_PHY_REG_INT_STATUS 0x13
61 #define AR8035_PHY_REG_SMART_SPEED 0x14
62 #define AR8035_PHY_REG_CDT_CTRL 0x16
63 #define AR8035_PHY_REG_LED_CTRL 0x18
64 #define AR8035_PHY_REG_MAN_LED_OVERRIDE 0x19
65 #define AR8035_PHY_REG_CDT_STATUS 0x1C
66 #define AR8035_PHY_REG_DBG_PORT_ADDR 0x1D
67 #define AR8035_PHY_REG_DBG_PORT_DATA 0x1E
68 
69 //BMCR register
70 #define BMCR_RESET (1 << 15)
71 #define BMCR_LOOPBACK (1 << 14)
72 #define BMCR_SPEED_SEL_LSB (1 << 13)
73 #define BMCR_AN_EN (1 << 12)
74 #define BMCR_POWER_DOWN (1 << 11)
75 #define BMCR_ISOLATE (1 << 10)
76 #define BMCR_RESTART_AN (1 << 9)
77 #define BMCR_DUPLEX_MODE (1 << 8)
78 #define BMCR_COL_TEST (1 << 7)
79 #define BMCR_SPEED_SEL_MSB (1 << 6)
80 
81 //BMSR register
82 #define BMSR_100BT4 (1 << 15)
83 #define BMSR_100BTX_FD (1 << 14)
84 #define BMSR_100BTX_HD (1 << 13)
85 #define BMSR_10BT_FD (1 << 12)
86 #define BMSR_10BT_HD (1 << 11)
87 #define BMSR_100BT2_FD (1 << 10)
88 #define BMSR_100BT2_HD (1 << 9)
89 #define BMSR_EXTENDED_STATUS (1 << 8)
90 #define BMSR_NO_PREAMBLE (1 << 6)
91 #define BMSR_AN_COMPLETE (1 << 5)
92 #define BMSR_REMOTE_FAULT (1 << 4)
93 #define BMSR_AN_ABLE (1 << 3)
94 #define BMSR_LINK_STATUS (1 << 2)
95 #define BMSR_JABBER_DETECT (1 << 1)
96 #define BMSR_EXTENDED_CAP (1 << 0)
97 
98 //ANAR register
99 #define ANAR_NEXT_PAGE (1 << 15)
100 #define ANAR_ACK (1 << 14)
101 #define ANAR_REMOTE_FAULT (1 << 13)
102 #define ANAR_XNP_ABLE (1 << 12)
103 #define ANAR_ASYMMETRIC_PAUSE (1 << 11)
104 #define ANAR_PAUSE (1 << 10)
105 #define ANAR_100BT4 (1 << 9)
106 #define ANAR_100BTX_FD (1 << 8)
107 #define ANAR_100BTX_HD (1 << 7)
108 #define ANAR_10BT_FD (1 << 6)
109 #define ANAR_10BT_HD (1 << 5)
110 #define ANAR_SELECTOR4 (1 << 4)
111 #define ANAR_SELECTOR3 (1 << 3)
112 #define ANAR_SELECTOR2 (1 << 2)
113 #define ANAR_SELECTOR1 (1 << 1)
114 #define ANAR_SELECTOR0 (1 << 0)
115 
116 //ANLPAR register
117 #define ANLPAR_NEXT_PAGE (1 << 15)
118 #define ANLPAR_ACK (1 << 14)
119 #define ANLPAR_REMOTE_FAULT (1 << 13)
120 #define ANLPAR_ASYMMETRIC_PAUSE (1 << 11)
121 #define ANLPAR_PAUSE (1 << 10)
122 #define ANLPAR_100BT4 (1 << 9)
123 #define ANLPAR_100BTX_FD (1 << 8)
124 #define ANLPAR_100BTX_HD (1 << 7)
125 #define ANLPAR_10BT_FD (1 << 6)
126 #define ANLPAR_10BT_HD (1 << 5)
127 #define ANLPAR_SELECTOR4 (1 << 4)
128 #define ANLPAR_SELECTOR3 (1 << 3)
129 #define ANLPAR_SELECTOR2 (1 << 2)
130 #define ANLPAR_SELECTOR1 (1 << 1)
131 #define ANLPAR_SELECTOR0 (1 << 0)
132 
133 //ANER register
134 #define ANER_PAR_DET_FAULT (1 << 4)
135 #define ANER_LP_NEXT_PAGE_ABLE (1 << 3)
136 #define ANER_NEXT_PAGE_ABLE (1 << 2)
137 #define ANER_PAGE_RECEIVED (1 << 1)
138 #define ANER_LP_AN_ABLE (1 << 0)
139 
140 //ANNPTR register
141 #define ANNPTR_NEXT_PAGE (1 << 15)
142 #define ANNPTR_MSG_PAGE (1 << 13)
143 #define ANNPTR_ACK2 (1 << 12)
144 #define ANNPTR_TOGGLE (1 << 11)
145 #define ANNPTR_MESSAGE10 (1 << 10)
146 #define ANNPTR_MESSAGE9 (1 << 9)
147 #define ANNPTR_MESSAGE8 (1 << 8)
148 #define ANNPTR_MESSAGE7 (1 << 7)
149 #define ANNPTR_MESSAGE6 (1 << 6)
150 #define ANNPTR_MESSAGE5 (1 << 5)
151 #define ANNPTR_MESSAGE4 (1 << 4)
152 #define ANNPTR_MESSAGE3 (1 << 3)
153 #define ANNPTR_MESSAGE2 (1 << 2)
154 #define ANNPTR_MESSAGE1 (1 << 1)
155 #define ANNPTR_MESSAGE0 (1 << 0)
156 
157 //LPNPAR register
158 #define LPNPAR_NEXT_PAGE (1 << 15)
159 #define LPNPAR_MSG_PAGE (1 << 13)
160 #define LPNPAR_ACK2 (1 << 12)
161 #define LPNPAR_TOGGLE (1 << 11)
162 #define LPNPAR_MESSAGE10 (1 << 10)
163 #define LPNPAR_MESSAGE9 (1 << 9)
164 #define LPNPAR_MESSAGE8 (1 << 8)
165 #define LPNPAR_MESSAGE7 (1 << 7)
166 #define LPNPAR_MESSAGE6 (1 << 6)
167 #define LPNPAR_MESSAGE5 (1 << 5)
168 #define LPNPAR_MESSAGE4 (1 << 4)
169 #define LPNPAR_MESSAGE3 (1 << 3)
170 #define LPNPAR_MESSAGE2 (1 << 2)
171 #define LPNPAR_MESSAGE1 (1 << 1)
172 #define LPNPAR_MESSAGE0 (1 << 0)
173 
174 //1000BT_CTRL register
175 #define _1000BT_CTRL_TEST_MODE2 (1 << 15)
176 #define _1000BT_CTRL_TEST_MODE1 (1 << 14)
177 #define _1000BT_CTRL_TEST_MODE0 (1 << 13)
178 #define _1000BT_CTRL_MS_MAN_CONF_EN (1 << 12)
179 #define _1000BT_CTRL_MS_MAN_CONF_VAL (1 << 11)
180 #define _1000BT_CTRL_PORT_TYPE (1 << 10)
181 #define _1000BT_CTRL_1000BT_FD (1 << 9)
182 #define _1000BT_CTRL_1000BT_HD (1 << 8)
183 
184 //1000BT_STATUS register
185 #define _1000BT_STATUS_MS_CONF_FAULT (1 << 15)
186 #define _1000BT_STATUS_MS_CONF_RES (1 << 14)
187 #define _1000BT_STATUS_LOC_REC_STATUS (1 << 13)
188 #define _1000BT_STATUS_REM_REC_STATUS (1 << 12)
189 #define _1000BT_STATUS_LP_1000BT_FD (1 << 11)
190 #define _1000BT_STATUS_LP_1000BT_HD (1 << 10)
191 #define _1000BT_STATUS_IDLE_ERR_CTR7 (1 << 7)
192 #define _1000BT_STATUS_IDLE_ERR_CTR6 (1 << 6)
193 #define _1000BT_STATUS_IDLE_ERR_CTR5 (1 << 5)
194 #define _1000BT_STATUS_IDLE_ERR_CTR4 (1 << 4)
195 #define _1000BT_STATUS_IDLE_ERR_CTR3 (1 << 3)
196 #define _1000BT_STATUS_IDLE_ERR_CTR2 (1 << 2)
197 #define _1000BT_STATUS_IDLE_ERR_CTR1 (1 << 1)
198 #define _1000BT_STATUS_IDLE_ERR_CTR0 (1 << 0)
199 
200 //MMD_CTRL register
201 #define MMD_CTRL_FUNCTION1 (1 << 15)
202 #define MMD_CTRL_FUNCTION0 (1 << 14)
203 #define MMD_CTRL_DEVAD4 (1 << 4)
204 #define MMD_CTRL_DEVAD3 (1 << 3)
205 #define MMD_CTRL_DEVAD2 (1 << 2)
206 #define MMD_CTRL_DEVAD1 (1 << 1)
207 #define MMD_CTRL_DEVAD0 (1 << 0)
208 
209 //EXT_STATUS register
210 #define EXT_STATUS_1000BX_FD (1 << 15)
211 #define EXT_STATUS_1000BX_HD (1 << 14)
212 #define EXT_STATUS_1000BT_FD (1 << 13)
213 #define EXT_STATUS_1000BT_HD (1 << 12)
214 
215 //FUNCTION register
216 #define FUNCTION_ASSERT_CRS_ON_TX (1 << 11)
217 #define FUNCTION_FORCE_LINK (1 << 10)
218 #define FUNCTION_MDI_CROSSOVER_MODE1 (1 << 6)
219 #define FUNCTION_MDI_CROSSOVER_MODE0 (1 << 5)
220 #define FUNCTION_SQE_TEST (1 << 2)
221 #define FUNCTION_POLARITY_REVERSAL (1 << 1)
222 #define FUNCTION_DISABLE_JABBER (1 << 0)
223 
224 //PHY_STATUS register
225 #define PHY_STATUS_SPEED1 (1 << 15)
226 #define PHY_STATUS_SPEED0 (1 << 14)
227 #define PHY_STATUS_DUPLEX (1 << 13)
228 #define PHY_STATUS_PAGE_RECEIVED (1 << 12)
229 #define PHY_STATUS_SPEED_DUPLEX_RESOLVED (1 << 11)
230 #define PHY_STATUS_LINK (1 << 10)
231 #define PHY_STATUS_MDI_CROSSOVER_STATUS (1 << 6)
232 #define PHY_STATUS_WIRESPEED_DOWNGRADE (1 << 5)
233 #define PHY_STATUS_TX_PAUSE_ENABLED (1 << 3)
234 #define PHY_STATUS_RX_PAUSE_ENABLED (1 << 2)
235 #define PHY_STATUS_POLARITY (1 << 1)
236 #define PHY_STATUS_JABBER (1 << 0)
237 
238 //Speed
239 #define PHY_STATUS_SPEED_MASK (3 << 14)
240 #define PHY_STATUS_SPEED_10 (0 << 14)
241 #define PHY_STATUS_SPEED_100 (1 << 14)
242 #define PHY_STATUS_SPEED_1000 (2 << 14)
243 
244 //INT_EN register
245 #define INT_EN_AN_ERROR (1 << 15)
246 #define INT_EN_SPEED_CHANGED (1 << 14)
247 #define INT_EN_PAGE_RECEIVED (1 << 12)
248 #define INT_EN_LINK_FAIL (1 << 11)
249 #define INT_EN_LINK_SUCCESS (1 << 10)
250 #define INT_EN_FAST_LINK_DOWN1 (1 << 9)
251 #define INT_EN_LINK_FAIL_BX (1 << 8)
252 #define INT_EN_LINK_SUCCESS_BX (1 << 7)
253 #define INT_EN_FAST_LINK_DOWN0 (1 << 6)
254 #define INT_EN_WIRESPEED_DOWNGRADE (1 << 5)
255 #define INT_EN_10MS_PTP (1 << 4)
256 #define INT_EN_RX_PTP (1 << 3)
257 #define INT_EN_TX_PTP (1 << 2)
258 #define INT_EN_POLARITY_CHANGED (1 << 1)
259 #define INT_EN_WOL_PTP (1 << 0)
260 
261 //INT_STATUS register
262 #define INT_STATUS_AN_ERROR (1 << 15)
263 #define INT_STATUS_SPEED_CHANGED (1 << 14)
264 #define INT_STATUS_PAGE_RECEIVED (1 << 12)
265 #define INT_STATUS_LINK_FAIL (1 << 11)
266 #define INT_STATUS_LINK_SUCCESS (1 << 10)
267 #define INT_STATUS_FAST_LINK_DOWN1 (1 << 9)
268 #define INT_STATUS_LINK_FAIL_BX (1 << 8)
269 #define INT_STATUS_LINK_SUCCESS_BX (1 << 7)
270 #define INT_STATUS_FAST_LINK_DOWN0 (1 << 6)
271 #define INT_STATUS_WIRESPEED_DOWNGRADE (1 << 5)
272 #define INT_STATUS_10MS_PTP (1 << 4)
273 #define INT_STATUS_RX_PTP (1 << 3)
274 #define INT_STATUS_TX_PTP (1 << 2)
275 #define INT_STATUS_POLARITY_CHANGED (1 << 1)
276 #define INT_STATUS_WOL_PTP (1 << 0)
277 
278 //SMART_SPEED register
279 #define SMART_SPEED_EN (1 << 5)
280 #define SMART_SPEED_RETRY_LIMIT2 (1 << 4)
281 #define SMART_SPEED_RETRY_LIMIT1 (1 << 3)
282 #define SMART_SPEED_RETRY_LIMIT0 (1 << 2)
283 #define SMART_SPEED_TIMER (1 << 1)
284 
285 //CDT_CTRL register
286 #define CDT_CTRL_MDI_PAIR_SELECT1 (1 << 9)
287 #define CDT_CTRL_MDI_PAIR_SELECT0 (1 << 8)
288 #define CDT_CTRL_ENABLE_TEST (1 << 0)
289 
290 //LED_CTRL register
291 #define LED_CTRL_DISABLE_LED (1 << 15)
292 #define LED_CTRL_LED_ON_TIME2 (1 << 14)
293 #define LED_CTRL_LED_ON_TIME1 (1 << 13)
294 #define LED_CTRL_LED_ON_TIME0 (1 << 12)
295 #define LED_CTRL_LED_OFF_TIME2 (1 << 10)
296 #define LED_CTRL_LED_OFF_TIME1 (1 << 9)
297 #define LED_CTRL_LED_OFF_TIME0 (1 << 8)
298 #define LED_CTRL_LED_LINK_CTRL1 (1 << 4)
299 #define LED_CTRL_LED_LINK_CTRL0 (1 << 3)
300 #define LED_CTRL_LED_ACT_CTRL (1 << 1)
301 
302 //MAN_LED_OVERRIDE register
303 #define MAN_LED_OVERRIDE_LED_ACT_CTRL (1 << 12)
304 #define MAN_LED_OVERRIDE_LED_LINK_CTRL1 (1 << 7)
305 #define MAN_LED_OVERRIDE_LED_LINK_CTRL0 (1 << 6)
306 #define MAN_LED_OVERRIDE_LED_RX_CTRL1 (1 << 3)
307 #define MAN_LED_OVERRIDE_LED_RX_CTRL0 (1 << 2)
308 #define MAN_LED_OVERRIDE_LED_TX_CTRL1 (1 << 1)
309 #define MAN_LED_OVERRIDE_LED_TX_CTRL0 (1 << 0)
310 
311 //CDT_STATUS register
312 #define CDT_STATUS_STATUS1 (1 << 9)
313 #define CDT_STATUS_STATUS0 (1 << 8)
314 #define CDT_STATUS_DELTA_TIME7 (1 << 7)
315 #define CDT_STATUS_DELTA_TIME6 (1 << 6)
316 #define CDT_STATUS_DELTA_TIME5 (1 << 5)
317 #define CDT_STATUS_DELTA_TIME4 (1 << 4)
318 #define CDT_STATUS_DELTA_TIME3 (1 << 3)
319 #define CDT_STATUS_DELTA_TIME2 (1 << 2)
320 #define CDT_STATUS_DELTA_TIME1 (1 << 1)
321 #define CDT_STATUS_DELTA_TIME0 (1 << 0)
322 
323 //C++ guard
324 #ifdef __cplusplus
325  extern "C" {
326 #endif
327 
328 //AR8035 Ethernet PHY driver
329 extern const PhyDriver ar8035PhyDriver;
330 
331 //AR8035 related functions
332 error_t ar8035Init(NetInterface *interface);
333 
334 void ar8035Tick(NetInterface *interface);
335 
336 void ar8035EnableIrq(NetInterface *interface);
337 void ar8035DisableIrq(NetInterface *interface);
338 
339 void ar8035EventHandler(NetInterface *interface);
340 
341 void ar8035WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
342 uint16_t ar8035ReadPhyReg(NetInterface *interface, uint8_t address);
343 
344 void ar8035DumpPhyReg(NetInterface *interface);
345 
346 //C++ guard
347 #ifdef __cplusplus
348  }
349 #endif
350 
351 #endif
void ar8035DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
error_t ar8035Init(NetInterface *interface)
AR8035 PHY transceiver initialization.
Definition: ar8035_driver.c:58
PHY driver.
Definition: nic.h:196
void ar8035EnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t ar8035ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
void ar8035Tick(NetInterface *interface)
AR8035 timer handler.
void ar8035WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
Ipv6Addr address
const PhyDriver ar8035PhyDriver
AR8035 Ethernet PHY driver.
Definition: ar8035_driver.c:42
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void ar8035DisableIrq(NetInterface *interface)
Disable interrupts.
Network interface controller abstraction layer.
void ar8035EventHandler(NetInterface *interface)
AR8035 event handler.