dp83822_driver.h
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1 /**
2  * @file dp83822_driver.h
3  * @brief DP83822 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _DP83822_DRIVER_H
30 #define _DP83822_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef DP83822_PHY_ADDR
37  #define DP83822_PHY_ADDR 1
38 #elif (DP83822_PHY_ADDR < 0 || DP83822_PHY_ADDR > 31)
39  #error DP83822_PHY_ADDR parameter is not valid
40 #endif
41 
42 //DP83822 registers
43 #define DP83822_PHY_REG_BMCR 0x00
44 #define DP83822_PHY_REG_BMSR 0x01
45 #define DP83822_PHY_REG_PHYIDR1 0x02
46 #define DP83822_PHY_REG_PHYIDR2 0x03
47 #define DP83822_PHY_REG_ANAR 0x04
48 #define DP83822_PHY_REG_ANLPAR 0x05
49 #define DP83822_PHY_REG_ANER 0x06
50 #define DP83822_PHY_REG_ANNPTR 0x07
51 #define DP83822_PHY_REG_ANLNPTR 0x08
52 #define DP83822_PHY_REG_CR1 0x09
53 #define DP83822_PHY_REG_CR2 0x0A
54 #define DP83822_PHY_REG_CR3 0x0B
55 #define DP83822_PHY_REG_REGCR 0x0D
56 #define DP83822_PHY_REG_ADDAR 0x0E
57 #define DP83822_PHY_REG_FLDS 0x0F
58 #define DP83822_PHY_REG_PHYSTS 0x10
59 #define DP83822_PHY_REG_PHYSCR 0x11
60 #define DP83822_PHY_REG_MISR1 0x12
61 #define DP83822_PHY_REG_MISR2 0x13
62 #define DP83822_PHY_REG_FCSCR 0x14
63 #define DP83822_PHY_REG_RECR 0x15
64 #define DP83822_PHY_REG_BISCR 0x16
65 #define DP83822_PHY_REG_RCSR 0x17
66 #define DP83822_PHY_REG_LEDCR 0x18
67 #define DP83822_PHY_REG_PHYCR 0x19
68 #define DP83822_PHY_REG_10BTSCR 0x1A
69 #define DP83822_PHY_REG_BICSR1 0x1B
70 #define DP83822_PHY_REG_BICSR2 0x1C
71 #define DP83822_PHY_REG_CDCR 0x1E
72 #define DP83822_PHY_REG_PHYRCR 0x1F
73 
74 //BMCR register
75 #define BMCR_RESET (1 << 15)
76 #define BMCR_LOOPBACK (1 << 14)
77 #define BMCR_SPEED_SEL (1 << 13)
78 #define BMCR_AN_EN (1 << 12)
79 #define BMCR_POWER_DOWN (1 << 11)
80 #define BMCR_ISOLATE (1 << 10)
81 #define BMCR_RESTART_AN (1 << 9)
82 #define BMCR_DUPLEX_MODE (1 << 8)
83 #define BMCR_COL_TEST (1 << 7)
84 
85 //BMSR register
86 #define BMSR_100BT4 (1 << 15)
87 #define BMSR_100BTX_FD (1 << 14)
88 #define BMSR_100BTX (1 << 13)
89 #define BMSR_10BT_FD (1 << 12)
90 #define BMSR_10BT (1 << 11)
91 #define BMSR_NO_PREAMBLE (1 << 6)
92 #define BMSR_AN_COMPLETE (1 << 5)
93 #define BMSR_REMOTE_FAULT (1 << 4)
94 #define BMSR_AN_ABLE (1 << 3)
95 #define BMSR_LINK_STATUS (1 << 2)
96 #define BMSR_JABBER_DETECT (1 << 1)
97 #define BMSR_EXTENDED_CAP (1 << 0)
98 
99 //ANAR register
100 #define ANAR_NP (1 << 15)
101 #define ANAR_RF (1 << 13)
102 #define ANAR_ASM_DIR (1 << 11)
103 #define ANAR_PAUSE (1 << 10)
104 #define ANAR_100BT4 (1 << 9)
105 #define ANAR_100BTX_FD (1 << 8)
106 #define ANAR_100BTX (1 << 7)
107 #define ANAR_10BT_FD (1 << 6)
108 #define ANAR_10BT (1 << 5)
109 #define ANAR_SELECTOR4 (1 << 4)
110 #define ANAR_SELECTOR3 (1 << 3)
111 #define ANAR_SELECTOR2 (1 << 2)
112 #define ANAR_SELECTOR1 (1 << 1)
113 #define ANAR_SELECTOR0 (1 << 0)
114 
115 //ANLPAR register
116 #define ANLPAR_NP (1 << 15)
117 #define ANLPAR_ACK (1 << 14)
118 #define ANLPAR_RF (1 << 13)
119 #define ANLPAR_ASM_DIR (1 << 11)
120 #define ANLPAR_PAUSE (1 << 10)
121 #define ANLPAR_100BT4 (1 << 9)
122 #define ANLPAR_100BTX_FD (1 << 8)
123 #define ANLPAR_100BTX (1 << 7)
124 #define ANLPAR_10BT_FD (1 << 6)
125 #define ANLPAR_10BT (1 << 5)
126 #define ANLPAR_SELECTOR4 (1 << 4)
127 #define ANLPAR_SELECTOR3 (1 << 3)
128 #define ANLPAR_SELECTOR2 (1 << 2)
129 #define ANLPAR_SELECTOR1 (1 << 1)
130 #define ANLPAR_SELECTOR0 (1 << 0)
131 
132 //ANER register
133 #define ANER_PDF (1 << 4)
134 #define ANER_LP_NP_ABLE (1 << 3)
135 #define ANER_NP_ABLE (1 << 2)
136 #define ANER_PAGE_RX (1 << 1)
137 #define ANER_LP_AN_ABLE (1 << 0)
138 
139 //ANNPTR register
140 #define ANNPTR_NP (1 << 15)
141 #define ANNPTR_MP (1 << 13)
142 #define ANNPTR_ACK2 (1 << 12)
143 #define ANNPTR_TOG_TX (1 << 11)
144 #define ANNPTR_CODE10 (1 << 10)
145 #define ANNPTR_CODE9 (1 << 9)
146 #define ANNPTR_CODE8 (1 << 8)
147 #define ANNPTR_CODE7 (1 << 7)
148 #define ANNPTR_CODE6 (1 << 6)
149 #define ANNPTR_CODE5 (1 << 5)
150 #define ANNPTR_CODE4 (1 << 4)
151 #define ANNPTR_CODE3 (1 << 3)
152 #define ANNPTR_CODE2 (1 << 2)
153 #define ANNPTR_CODE1 (1 << 1)
154 #define ANNPTR_CODE0 (1 << 0)
155 
156 //ANLNPTR register
157 #define ANLNPTR_NP (1 << 15)
158 #define ANLNPTR_ACK (1 << 14)
159 #define ANLNPTR_MP (1 << 13)
160 #define ANLNPTR_ACK2 (1 << 12)
161 #define ANLNPTR_TOGGLE (1 << 11)
162 #define ANLNPTR_MESSAGE10 (1 << 10)
163 #define ANLNPTR_MESSAGE9 (1 << 9)
164 #define ANLNPTR_MESSAGE8 (1 << 8)
165 #define ANLNPTR_MESSAGE7 (1 << 7)
166 #define ANLNPTR_MESSAGE6 (1 << 6)
167 #define ANLNPTR_MESSAGE5 (1 << 5)
168 #define ANLNPTR_MESSAGE4 (1 << 4)
169 #define ANLNPTR_MESSAGE3 (1 << 3)
170 #define ANLNPTR_MESSAGE2 (1 << 2)
171 #define ANLNPTR_MESSAGE1 (1 << 1)
172 #define ANLNPTR_MESSAGE0 (1 << 0)
173 
174 //CR1 register
175 #define CR1_RMII_ENHANCED_MODE (1 << 9)
176 #define CR1_TDR_AUTO_RUN (1 << 8)
177 #define CR1_LINK_LOSS_RECOVERY (1 << 7)
178 #define CR1_FAST_AUTO_MDIX (1 << 6)
179 #define CR1_ROBUST_AUTO_MDIX (1 << 5)
180 #define CR1_FAST_AN_EN (1 << 4)
181 #define CR1_FAST_AN_SEL1 (1 << 3)
182 #define CR1_FAST_AN_SEL0 (1 << 2)
183 #define CR1_FAST_RX_DV_DETECT (1 << 1)
184 
185 //CR2 register
186 #define CR2_FORCE_FAR_END_LINK_DROP (1 << 15)
187 #define CR2_100BFX_EN (1 << 14)
188 #define CR2_ASY_LINK_UP_IN_PD (1 << 6)
189 #define CR2_EXT_FULL_DUPLEX_ABLE (1 << 5)
190 #define CR2_ENHANCED_LED_LINK (1 << 4)
191 #define CR2_ISOLATE_MII (1 << 3)
192 #define CR2_RX_ER_DURING_IDLE (1 << 2)
193 #define CR2_ODD_NIBBLE_DETECT_DIS (1 << 1)
194 #define CR2_RMII_RX_CLK (1 << 0)
195 
196 //CR3 register
197 #define CR3_DESCR_FAST_LINK_DOWN (1 << 10)
198 #define CR_POLARITY_SWAP (1 << 6)
199 #define CR_MDIX_SWAP (1 << 5)
200 #define CR_FAST_LINK_DOWN_MODE3 (1 << 3)
201 #define CR_FAST_LINK_DOWN_MODE2 (1 << 2)
202 #define CR_FAST_LINK_DOWN_MODE1 (1 << 1)
203 #define CR_FAST_LINK_DOWN_MODE0 (1 << 0)
204 
205 //REGCR register
206 #define REGCR_EXTENDED_REG_CMD1 (1 << 15)
207 #define REGCR_EXTENDED_REG_CMD0 (1 << 14)
208 #define REGCR_DEVAD4 (1 << 4)
209 #define REGCR_DEVAD3 (1 << 3)
210 #define REGCR_DEVAD2 (1 << 2)
211 #define REGCR_DEVAD1 (1 << 1)
212 #define REGCR_DEVAD0 (1 << 0)
213 
214 //FLDS register
215 #define FLDS_FAST_LINK_DOWN_STATUS4 (1 << 8)
216 #define FLDS_FAST_LINK_DOWN_STATUS3 (1 << 7)
217 #define FLDS_FAST_LINK_DOWN_STATUS2 (1 << 6)
218 #define FLDS_FAST_LINK_DOWN_STATUS1 (1 << 5)
219 #define FLDS_FAST_LINK_DOWN_STATUS0 (1 << 4)
220 
221 //PHYSTS register
222 #define PHYSTS_MDIX_MODE (1 << 14)
223 #define PHYSTS_RX_ERROR_LATCH (1 << 13)
224 #define PHYSTS_POLARITY_STATUS (1 << 12)
225 #define PHYSTS_FALSE_CARRIER_SENSE (1 << 11)
226 #define PHYSTS_SIGNAL_DETECT (1 << 10)
227 #define PHYSTS_DESCRAMBLER_LOCK (1 << 9)
228 #define PHYSTS_PAGE_RECEIVED (1 << 8)
229 #define PHYSTS_MII_INTERRUPT (1 << 7)
230 #define PHYSTS_REMOTE_FAULT (1 << 6)
231 #define PHYSTS_JABBER_DETECT (1 << 5)
232 #define PHYSTS_AN_COMPLETE (1 << 4)
233 #define PHYSTS_LOOPBACK_STATUS (1 << 3)
234 #define PHYSTS_DUPLEX_STATUS (1 << 2)
235 #define PHYSTS_SPEED_STATUS (1 << 1)
236 #define PHYSTS_LINK_STATUS (1 << 0)
237 
238 //PHYSCR register
239 #define PHYSCR_DISABLE_PLL (1 << 15)
240 #define PHYSCR_POWER_SAVE_MODE_EN (1 << 14)
241 #define PHYSCR_POWER_SAVE_MODE1 (1 << 13)
242 #define PHYSCR_POWER_SAVE_MODE0 (1 << 12)
243 #define PHYSCR_SCRAMBLER_BYPASS (1 << 11)
244 #define PHYSCR_LOOPBACK_FIFO_DEPTH1 (1 << 9)
245 #define PHYSCR_LOOPBACK_FIFO_DEPTH0 (1 << 8)
246 #define PHYSCR_COL_FULL_DUPLEX_EN (1 << 4)
247 #define PHYSCR_INT_POLARITY (1 << 3)
248 #define PHYSCR_TEST_INT (1 << 2)
249 #define PHYSCR_INT_EN (1 << 1)
250 #define PHYSCR_INT_OE (1 << 0)
251 
252 //MISR1 register
253 #define MISR1_LQ_INT (1 << 15)
254 #define MISR1_ED_INT (1 << 14)
255 #define MISR1_LINK_INT (1 << 13)
256 #define MISR1_SPD_INT (1 << 12)
257 #define MISR1_DUP_INT (1 << 11)
258 #define MISR1_ANC_INT (1 << 10)
259 #define MISR1_FHF_INT (1 << 9)
260 #define MISR1_RHF_INT (1 << 8)
261 #define MISR1_LQ_INT_EN (1 << 7)
262 #define MISR1_ED_INT_EN (1 << 6)
263 #define MISR1_LINK_INT_EN (1 << 5)
264 #define MISR1_SPD_INT_EN (1 << 4)
265 #define MISR1_DUP_INT_EN (1 << 3)
266 #define MISR1_ANC_INT_EN (1 << 2)
267 #define MISR1_FHF_INT_EN (1 << 1)
268 #define MISR1_RHF_INT_EN (1 << 0)
269 
270 //MISR2 register
271 #define MISR2_EEE_ERROR_INT (1 << 15)
272 #define MISR2_AN_ERROR_INT (1 << 14)
273 #define MISR2_PR_INT (1 << 13)
274 #define MISR2_FIFO_OF_UF_INT (1 << 12)
275 #define MISR2_MDI_CHANGE_INT (1 << 11)
276 #define MISR2_SLEEP_MODE_INT (1 << 10)
277 #define MISR2_POL_CHANGE_INT (1 << 9)
278 #define MISR2_JABBER_DETECT_INT (1 << 8)
279 #define MISR2_EEE_ERROR_INT_EN (1 << 7)
280 #define MISR2_AN_ERROR_INT_EN (1 << 6)
281 #define MISR2_PR_INT_EN (1 << 5)
282 #define MISR2_FIFO_OF_UF_INT_EN (1 << 4)
283 #define MISR2_MDI_CHANGE_INT_EN (1 << 3)
284 #define MISR2_SLEEP_MODE_INT_EN (1 << 2)
285 #define MISR2_POL_CHANGE_INT_EN (1 << 1)
286 #define MISR2_JABBER_DETECT_INT_EN (1 << 0)
287 
288 //FCSCR register
289 #define FCSCR_FCSCNT7 (1 << 7)
290 #define FCSCR_FCSCNT6 (1 << 6)
291 #define FCSCR_FCSCNT5 (1 << 5)
292 #define FCSCR_FCSCNT4 (1 << 4)
293 #define FCSCR_FCSCNT3 (1 << 3)
294 #define FCSCR_FCSCNT2 (1 << 2)
295 #define FCSCR_FCSCNT1 (1 << 1)
296 #define FCSCR_FCSCNT0 (1 << 0)
297 
298 //RECR register
299 #define RECR_RXERCNT7 (1 << 7)
300 #define RECR_RXERCNT6 (1 << 6)
301 #define RECR_RXERCNT5 (1 << 5)
302 #define RECR_RXERCNT4 (1 << 4)
303 #define RECR_RXERCNT3 (1 << 3)
304 #define RECR_RXERCNT2 (1 << 2)
305 #define RECR_RXERCNT1 (1 << 1)
306 #define RECR_RXERCNT0 (1 << 0)
307 
308 //BISCR register
309 #define BISCR_ERROR_COUNTER_MODE (1 << 14)
310 #define BISCR_PRBS_CHECK (1 << 13)
311 #define BISCR_PACKET_GEN_EN (1 << 12)
312 #define BISCR_PRBS_CHECK_LOCK_SYNC (1 << 11)
313 #define BISCR_PRBS_CHECK_SYNC_LOSS (1 << 10)
314 #define BISCR_PACKET_GEN_STATUS (1 << 9)
315 #define BISCR_POWER_MODE (1 << 8)
316 #define BISCR_TX_MII_LOOPBACK (1 << 6)
317 #define BISCR_LOOPBACK_MODE4 (1 << 4)
318 #define BISCR_LOOPBACK_MODE3 (1 << 3)
319 #define BISCR_LOOPBACK_MODE2 (1 << 2)
320 #define BISCR_LOOPBACK_MODE1 (1 << 1)
321 #define BISCR_LOOPBACK_MODE0 (1 << 0)
322 
323 //RCSR register
324 #define RCSR_RGMII_RX_CLK_SHIFT (1 << 12)
325 #define RCSR_RGMII_TX_CLK_SHIFT (1 << 11)
326 #define RCSR_RGMII_TX_SYNCED (1 << 10)
327 #define RCSR_RGMII_MODE (1 << 9)
328 #define RCSR_RMII_TX_CLOCK_SHIFT (1 << 8)
329 #define RCSR_RMII_CLK_SEL (1 << 7)
330 #define RCSR_RMII_ASYNC_FIFO_BP (1 << 6)
331 #define RCSR_RMII_MODE (1 << 5)
332 #define RCSR_RMII_REV_SEL (1 << 4)
333 #define RCSR_RMII_OVF_STATUS (1 << 3)
334 #define RCSR_RMII_UNF_STATUS (1 << 2)
335 #define RCSR_ELAST_BUFFER_SIZE1 (1 << 1)
336 #define RCSR_ELAST_BUFFER_SIZE0 (1 << 0)
337 
338 //LEDCR register
339 #define LEDCR_BLINK_RATE1 (1 << 10)
340 #define LEDCR_BLINK_RATE0 (1 << 9)
341 #define LEDCR_LED_0_POLARITY (1 << 7)
342 #define LEDCR_DRIVE_LED_0 (1 << 4)
343 #define LEDCR_LED_0_ON_OFF (1 << 1)
344 
345 //PHYCR register
346 #define PHYCR_MDIX_EN (1 << 15)
347 #define PHYCR_FORCE_MDIX (1 << 14)
348 #define PHYCR_PAUSE_RX_STATUS (1 << 13)
349 #define PHYCR_PAUSE_TX_STATUS (1 << 12)
350 #define PHYCR_MII_LINK_STATUS (1 << 11)
351 #define PHYCR_BP_LED_STRETCH (1 << 7)
352 #define PHYCR_LED_CONFIG (1 << 5)
353 #define PHYCR_PHY_ADDR4 (1 << 4)
354 #define PHYCR_PHY_ADDR3 (1 << 3)
355 #define PHYCR_PHY_ADDR2 (1 << 2)
356 #define PHYCR_PHY_ADDR1 (1 << 1)
357 #define PHYCR_PHY_ADDR0 (1 << 0)
358 
359 //10BTSCR register
360 #define _10BTSCR_RX_THRESHOLD_EN (1 << 13)
361 #define _10BTSCR_SQUELCH3 (1 << 12)
362 #define _10BTSCR_SQUELCH2 (1 << 11)
363 #define _10BTSCR_SQUELCH1 (1 << 10)
364 #define _10BTSCR_SQUELCH0 (1 << 9)
365 #define _10BTSCR_NLP_DIS (1 << 7)
366 #define _10BTSCR_POLARITY_STATUS (1 << 4)
367 #define _10BTSCR_JABBER_DIS (1 << 0)
368 
369 //BICSR1 register
370 #define BICSR1_BIST_ERROR_COUNT7 (1 << 15)
371 #define BICSR1_BIST_ERROR_COUNT6 (1 << 14)
372 #define BICSR1_BIST_ERROR_COUNT5 (1 << 13)
373 #define BICSR1_BIST_ERROR_COUNT4 (1 << 12)
374 #define BICSR1_BIST_ERROR_COUNT3 (1 << 11)
375 #define BICSR1_BIST_ERROR_COUNT2 (1 << 10)
376 #define BICSR1_BIST_ERROR_COUNT1 (1 << 9)
377 #define BICSR1_BIST_ERROR_COUNT0 (1 << 8)
378 #define BICSR1_BIST_IPG_LENGTH7 (1 << 7)
379 #define BICSR1_BIST_IPG_LENGTH6 (1 << 6)
380 #define BICSR1_BIST_IPG_LENGTH5 (1 << 5)
381 #define BICSR1_BIST_IPG_LENGTH4 (1 << 4)
382 #define BICSR1_BIST_IPG_LENGTH3 (1 << 3)
383 #define BICSR1_BIST_IPG_LENGTH2 (1 << 2)
384 #define BICSR1_BIST_IPG_LENGTH1 (1 << 1)
385 #define BICSR1_BIST_IPG_LENGTH0 (1 << 0)
386 
387 //BICSR2 register
388 #define BICSR2_BIST_PACKET_LENGTH10 (1 << 10)
389 #define BICSR2_BIST_PACKET_LENGTH9 (1 << 9)
390 #define BICSR2_BIST_PACKET_LENGTH8 (1 << 8)
391 #define BICSR2_BIST_PACKET_LENGTH7 (1 << 7)
392 #define BICSR2_BIST_PACKET_LENGTH6 (1 << 6)
393 #define BICSR2_BIST_PACKET_LENGTH5 (1 << 5)
394 #define BICSR2_BIST_PACKET_LENGTH4 (1 << 4)
395 #define BICSR2_BIST_PACKET_LENGTH3 (1 << 3)
396 #define BICSR2_BIST_PACKET_LENGTH2 (1 << 2)
397 #define BICSR2_BIST_PACKET_LENGTH1 (1 << 1)
398 #define BICSR2_BIST_PACKET_LENGTH0 (1 << 0)
399 
400 //CDCR register
401 #define CDCR_CABLE_DIAG_START (1 << 15)
402 #define CDCR_CABLE_DIAG_STATUS (1 << 1)
403 #define CDCR_CABLE_DIAG_TEST_FAIL (1 << 0)
404 
405 //PHYRCR register
406 #define PHYRCR_SOFT_RESET (1 << 15)
407 #define PHYRCR_DIGITAL_RESTART (1 << 14)
408 
409 //C++ guard
410 #ifdef __cplusplus
411  extern "C" {
412 #endif
413 
414 //DP83822 Ethernet PHY driver
415 extern const PhyDriver dp83822PhyDriver;
416 
417 //DP83822 related functions
418 error_t dp83822Init(NetInterface *interface);
419 
420 void dp83822Tick(NetInterface *interface);
421 
422 void dp83822EnableIrq(NetInterface *interface);
423 void dp83822DisableIrq(NetInterface *interface);
424 
425 void dp83822EventHandler(NetInterface *interface);
426 
427 void dp83822WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
428 uint16_t dp83822ReadPhyReg(NetInterface *interface, uint8_t address);
429 
430 void dp83822DumpPhyReg(NetInterface *interface);
431 
432 //C++ guard
433 #ifdef __cplusplus
434  }
435 #endif
436 
437 #endif
void dp83822EnableIrq(NetInterface *interface)
Enable interrupts.
PHY driver.
Definition: nic.h:196
void dp83822WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
void dp83822DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
const PhyDriver dp83822PhyDriver
DP83822 Ethernet PHY driver.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void dp83822EventHandler(NetInterface *interface)
DP83822 event handler.
void dp83822DisableIrq(NetInterface *interface)
Disable interrupts.
void dp83822Tick(NetInterface *interface)
DP83822 timer handler.
uint16_t dp83822ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
Network interface controller abstraction layer.
error_t dp83822Init(NetInterface *interface)
DP83822 PHY transceiver initialization.