dp83822_driver.h
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1 /**
2  * @file dp83822_driver.h
3  * @brief DP83822 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _DP83822_DRIVER_H
32 #define _DP83822_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //PHY address
38 #ifndef DP83822_PHY_ADDR
39  #define DP83822_PHY_ADDR 1
40 #elif (DP83822_PHY_ADDR < 0 || DP83822_PHY_ADDR > 31)
41  #error DP83822_PHY_ADDR parameter is not valid
42 #endif
43 
44 //DP83822 PHY registers
45 #define DP83822_BMCR 0x00
46 #define DP83822_BMSR 0x01
47 #define DP83822_PHYID1 0x02
48 #define DP83822_PHYID2 0x03
49 #define DP83822_ANAR 0x04
50 #define DP83822_ANLPAR 0x05
51 #define DP83822_ANER 0x06
52 #define DP83822_ANNPR 0x07
53 #define DP83822_ANLPNPR 0x08
54 #define DP83822_CR1 0x09
55 #define DP83822_CR2 0x0A
56 #define DP83822_CR3 0x0B
57 #define DP83822_REGCR 0x0D
58 #define DP83822_ADDAR 0x0E
59 #define DP83822_FLDS 0x0F
60 #define DP83822_PHYSTS 0x10
61 #define DP83822_PHYSCR 0x11
62 #define DP83822_MISR1 0x12
63 #define DP83822_MISR2 0x13
64 #define DP83822_FCSCR 0x14
65 #define DP83822_RECR 0x15
66 #define DP83822_BISCR 0x16
67 #define DP83822_RCSR 0x17
68 #define DP83822_LEDCR 0x18
69 #define DP83822_PHYCR 0x19
70 #define DP83822_10BTSCR 0x1A
71 #define DP83822_BICSR1 0x1B
72 #define DP83822_BICSR2 0x1C
73 #define DP83822_CDCR 0x1E
74 #define DP83822_PHYRCR 0x1F
75 
76 //Basic Mode Control register
77 #define DP83822_BMCR_RESET 0x8000
78 #define DP83822_BMCR_LOOPBACK 0x4000
79 #define DP83822_BMCR_SPEED_SEL 0x2000
80 #define DP83822_BMCR_AN_EN 0x1000
81 #define DP83822_BMCR_POWER_DOWN 0x0800
82 #define DP83822_BMCR_ISOLATE 0x0400
83 #define DP83822_BMCR_RESTART_AN 0x0200
84 #define DP83822_BMCR_DUPLEX_MODE 0x0100
85 #define DP83822_BMCR_COL_TEST 0x0080
86 
87 //Basic Mode Status register
88 #define DP83822_BMSR_100BT4 0x8000
89 #define DP83822_BMSR_100BTX_FD 0x4000
90 #define DP83822_BMSR_100BTX_HD 0x2000
91 #define DP83822_BMSR_10BT_FD 0x1000
92 #define DP83822_BMSR_10BT_HD 0x0800
93 #define DP83822_BMSR_SMI_PREAMBLE_SUPPR 0x0040
94 #define DP83822_BMSR_AN_COMPLETE 0x0020
95 #define DP83822_BMSR_REMOTE_FAULT 0x0010
96 #define DP83822_BMSR_AN_CAPABLE 0x0008
97 #define DP83822_BMSR_LINK_STATUS 0x0004
98 #define DP83822_BMSR_JABBER_DETECT 0x0002
99 #define DP83822_BMSR_EXTENDED_CAPABLE 0x0001
100 
101 //PHY Identifier 1 register
102 #define DP83822_PHYID1_OUI_MSB 0xFFFF
103 #define DP83822_PHYID1_OUI_MSB_DEFAULT 0x2000
104 
105 //PHY Identifier 2 register
106 #define DP83822_PHYID2_OUI_LSB 0xFC00
107 #define DP83822_PHYID2_OUI_LSB_DEFAULT 0xA000
108 #define DP83822_PHYID2_VNDR_MDL 0x03F0
109 #define DP83822_PHYID2_VNDR_MDL_DEFAULT 0x0240
110 #define DP83822_PHYID2_MDL_REV 0x000F
111 
112 //Auto-Negotiation Advertisement register
113 #define DP83822_ANAR_NEXT_PAGE 0x8000
114 #define DP83822_ANAR_REMOTE_FAULT 0x2000
115 #define DP83822_ANAR_ASYM_DIR 0x0800
116 #define DP83822_ANAR_PAUSE 0x0400
117 #define DP83822_ANAR_100BT4 0x0200
118 #define DP83822_ANAR_100BTX_FD 0x0100
119 #define DP83822_ANAR_100BTX_HD 0x0080
120 #define DP83822_ANAR_10BT_FD 0x0040
121 #define DP83822_ANAR_10BT_HD 0x0020
122 #define DP83822_ANAR_SELECTOR 0x001F
123 #define DP83822_ANAR_SELECTOR_DEFAULT 0x0001
124 
125 //Auto-Negotiation Link Partner Ability register
126 #define DP83822_ANLPAR_NEXT_PAGE 0x8000
127 #define DP83822_ANLPAR_ACK 0x4000
128 #define DP83822_ANLPAR_REMOTE_FAULT 0x2000
129 #define DP83822_ANLPAR_ASYM_DIR 0x0800
130 #define DP83822_ANLPAR_PAUSE 0x0400
131 #define DP83822_ANLPAR_100BT4 0x0200
132 #define DP83822_ANLPAR_100BTX_FD 0x0100
133 #define DP83822_ANLPAR_100BTX_HD 0x0080
134 #define DP83822_ANLPAR_10BT_FD 0x0040
135 #define DP83822_ANLPAR_10BT_HD 0x0020
136 #define DP83822_ANLPAR_SELECTOR 0x001F
137 #define DP83822_ANLPAR_SELECTOR_DEFAULT 0x0001
138 
139 //Auto-Negotiation Expansion register
140 #define DP83822_ANER_PAR_DETECT_FAULT 0x0010
141 #define DP83822_ANER_LP_NEXT_PAGE_ABLE 0x0008
142 #define DP83822_ANER_NEXT_PAGE_ABLE 0x0004
143 #define DP83822_ANER_PAGE_RECEIVED 0x0002
144 #define DP83822_ANER_LP_AN_ABLE 0x0001
145 
146 //Auto-Negotiation Next Page TX register
147 #define DP83822_ANNPR_NEXT_PAGE 0x8000
148 #define DP83822_ANNPR_MSG_PAGE 0x2000
149 #define DP83822_ANNPR_ACK2 0x1000
150 #define DP83822_ANNPR_TOGGLE 0x0800
151 #define DP83822_ANNPR_CODE 0x07FF
152 
153 //Auto-Negotiation Link Partner Ability Next Page register
154 #define DP83822_ANLPNPR_NEXT_PAGE 0x8000
155 #define DP83822_ANLPNPR_ACK 0x4000
156 #define DP83822_ANLPNPR_MSG_PAGE 0x2000
157 #define DP83822_ANLPNPR_ACK2 0x1000
158 #define DP83822_ANLPNPR_TOGGLE 0x0800
159 #define DP83822_ANLPNPR_MESSAGE 0x07FF
160 
161 //Control 1 register
162 #define DP83822_CR1_RMII_ENHANCED_MODE 0x0200
163 #define DP83822_CR1_TDR_AUTO_RUN 0x0100
164 #define DP83822_CR1_LINK_LOSS_RECOVERY 0x0080
165 #define DP83822_CR1_FAST_AUTO_MDIX 0x0040
166 #define DP83822_CR1_ROBUST_AUTO_MDIX 0x0020
167 #define DP83822_CR1_FAST_AN_EN 0x0010
168 #define DP83822_CR1_FAST_AN_SEL 0x000C
169 #define DP83822_CR1_FAST_RX_DV_DETECT 0x0002
170 
171 //Control 2 register
172 #define DP83822_CR2_FORCE_FAR_END_LINK_DROP 0x8000
173 #define DP83822_CR2_100BFX_EN 0x4000
174 #define DP83822_CR2_FAST_LINK_UP_IN_PD 0x0040
175 #define DP83822_CR2_EXTENDED_FD_ABLE 0x0020
176 #define DP83822_CR2_ENHANCED_LED_LINK 0x0010
177 #define DP83822_CR2_ISOLATE_MII 0x0008
178 #define DP83822_CR2_RX_ER_DURING_IDLE 0x0004
179 #define DP83822_CR2_ODD_NIBBLE_DETECT_DIS 0x0002
180 #define DP83822_CR2_RMII_RECEIVE_CLK 0x0001
181 
182 //Control 3 register
183 #define DP83822_CR3_DESCRAMBLER_FAST_LINK_DOWN 0x0400
184 #define DP83822_CR3_POLARITY_SWAP 0x0040
185 #define DP83822_CR3_MDIX_SWAP 0x0020
186 #define DP83822_CR3_FAST_LINK_DOWN_MODE 0x000F
187 
188 //Register Control register
189 #define DP83822_REGCR_CMD 0xC000
190 #define DP83822_REGCR_CMD_ADDR 0x0000
191 #define DP83822_REGCR_CMD_DATA_NO_POST_INC 0x4000
192 #define DP83822_REGCR_CMD_DATA_POST_INC_RW 0x8000
193 #define DP83822_REGCR_CMD_DATA_POST_INC_W 0xC000
194 #define DP83822_REGCR_DEVAD 0x001F
195 
196 //Fast Link Down Status register
197 #define DP83822_FLDS_FAST_LINK_DOWN_STATUS 0x01F0
198 
199 //PHY Status register
200 #define DP83822_PHYSTS_MDIX_MODE 0x4000
201 #define DP83822_PHYSTS_RECEIVE_ERROR_LATCH 0x2000
202 #define DP83822_PHYSTS_POLARITY_STATUS 0x1000
203 #define DP83822_PHYSTS_FCS_LATCH 0x0800
204 #define DP83822_PHYSTS_SIGNAL_DETECT 0x0400
205 #define DP83822_PHYSTS_DESCRAMBLER_LOCK 0x0200
206 #define DP83822_PHYSTS_PAGE_RECEIVED 0x0100
207 #define DP83822_PHYSTS_MII_INTERRUPT 0x0080
208 #define DP83822_PHYSTS_REMOTE_FAULT 0x0040
209 #define DP83822_PHYSTS_JABBER_DETECT 0x0020
210 #define DP83822_PHYSTS_AN_COMPLETE 0x0010
211 #define DP83822_PHYSTS_LOOPBACK_STATUS 0x0008
212 #define DP83822_PHYSTS_DUPLEX_STATUS 0x0004
213 #define DP83822_PHYSTS_SPEED_STATUS 0x0002
214 #define DP83822_PHYSTS_LINK_STATUS 0x0001
215 
216 //PHY Specific Control register
217 #define DP83822_PHYSCR_PLL_DIS 0x8000
218 #define DP83822_PHYSCR_POWER_SAVE_MODE_EN 0x4000
219 #define DP83822_PHYSCR_POWER_SAVE_MODE 0x3000
220 #define DP83822_PHYSCR_SCRAMBLER_BYPASS 0x0800
221 #define DP83822_PHYSCR_LOOPBACK_FIFO_DEPTH 0x0300
222 #define DP83822_PHYSCR_COL_FD_EN 0x0010
223 #define DP83822_PHYSCR_INT_POLARITY 0x0008
224 #define DP83822_PHYSCR_TEST_INT 0x0004
225 #define DP83822_PHYSCR_INT_EN 0x0002
226 #define DP83822_PHYSCR_INT_OE 0x0001
227 
228 //MII Interrupt Status 1 register
229 #define DP83822_MISR1_LQ_INT 0x8000
230 #define DP83822_MISR1_ED_INT 0x4000
231 #define DP83822_MISR1_LINK_INT 0x2000
232 #define DP83822_MISR1_SPD_INT 0x1000
233 #define DP83822_MISR1_DUP_INT 0x0800
234 #define DP83822_MISR1_ANC_INT 0x0400
235 #define DP83822_MISR1_FHF_INT 0x0200
236 #define DP83822_MISR1_RHF_INT 0x0100
237 #define DP83822_MISR1_LQ_INT_EN 0x0080
238 #define DP83822_MISR1_ED_INT_EN 0x0040
239 #define DP83822_MISR1_LINK_INT_EN 0x0020
240 #define DP83822_MISR1_SPD_INT_EN 0x0010
241 #define DP83822_MISR1_DUP_INT_EN 0x0008
242 #define DP83822_MISR1_ANC_INT_EN 0x0004
243 #define DP83822_MISR1_FHF_INT_EN 0x0002
244 #define DP83822_MISR1_RHF_INT_EN 0x0001
245 
246 //MII Interrupt Status 2 register
247 #define DP83822_MISR2_EEE_ERROR_INT 0x8000
248 #define DP83822_MISR2_AN_ERROR_INT 0x4000
249 #define DP83822_MISR2_PR_INT 0x2000
250 #define DP83822_MISR2_FIFO_OF_UF_INT 0x1000
251 #define DP83822_MISR2_MDI_CHANGE_INT 0x0800
252 #define DP83822_MISR2_SLEEP_MODE_INT 0x0400
253 #define DP83822_MISR2_POL_CHANGE_INT 0x0200
254 #define DP83822_MISR2_JABBER_DETECT_INT 0x0100
255 #define DP83822_MISR2_EEE_ERROR_INT_EN 0x0080
256 #define DP83822_MISR2_AN_ERROR_INT_EN 0x0040
257 #define DP83822_MISR2_PR_INT_EN 0x0020
258 #define DP83822_MISR2_FIFO_OF_UF_INT_EN 0x0010
259 #define DP83822_MISR2_MDI_CHANGE_INT_EN 0x0008
260 #define DP83822_MISR2_SLEEP_MODE_INT_EN 0x0004
261 #define DP83822_MISR2_POL_CHANGE_INT_EN 0x0002
262 #define DP83822_MISR2_JABBER_DETECT_INT_EN 0x0001
263 
264 //False Carrier Sense Counter register
265 #define DP83822_FCSCR_FCSCNT 0x00FF
266 
267 //Receive Error Counter register
268 #define DP83822_RECR_RXERCNT 0xFFFF
269 
270 //BIST Control register
271 #define DP83822_BISCR_ERROR_COUNTER_MODE 0x4000
272 #define DP83822_BISCR_PRBS_CHECKER 0x2000
273 #define DP83822_BISCR_PACKET_GEN_EN 0x1000
274 #define DP83822_BISCR_PRBS_CHECKER_LOCK_SYNC 0x0800
275 #define DP83822_BISCR_PRBS_CHECKER_SYNC_LOSS 0x0400
276 #define DP83822_BISCR_PACKET_GEN_STATUS 0x0200
277 #define DP83822_BISCR_POWER_MODE 0x0100
278 #define DP83822_BISCR_TX_MII_LOOPBACK 0x0040
279 #define DP83822_BISCR_LOOPBACK_MODE 0x001F
280 
281 //RMII and Status register
282 #define DP83822_RCSR_RGMII_RX_CLK_SHIFT 0x1000
283 #define DP83822_RCSR_RGMII_TX_CLK_SHIFT 0x0800
284 #define DP83822_RCSR_RGMII_TX_SYNCED 0x0400
285 #define DP83822_RCSR_RGMII_MODE 0x0200
286 #define DP83822_RCSR_RMII_TX_CLOCK_SHIFT 0x0100
287 #define DP83822_RCSR_RMII_CLK_SEL 0x0080
288 #define DP83822_RCSR_RMII_ASYNC_FIFO_BYPASS 0x0040
289 #define DP83822_RCSR_RMII_MODE 0x0020
290 #define DP83822_RCSR_RMII_REV_SEL 0x0010
291 #define DP83822_RCSR_RMII_OVF_STATUS 0x0008
292 #define DP83822_RCSR_RMII_UNF_STATUS 0x0004
293 #define DP83822_RCSR_RX_ELAST_BUFFER_SIZE 0x0003
294 
295 //LED Direct Control register
296 #define DP83822_LEDCR_BLINK_RATE 0x0600
297 #define DP83822_LEDCR_LED_0_POLARITY 0x0080
298 #define DP83822_LEDCR_DRIVE_LED_0 0x0010
299 #define DP83822_LEDCR_LED_0_ON_OFF 0x0002
300 
301 //PHY Control register
302 #define DP83822_PHYCR_MDIX_EN 0x8000
303 #define DP83822_PHYCR_FORCE_MDIX 0x4000
304 #define DP83822_PHYCR_PAUSE_RX_STATUS 0x2000
305 #define DP83822_PHYCR_PAUSE_TX_STATUS 0x1000
306 #define DP83822_PHYCR_MII_LINK_STATUS 0x0800
307 #define DP83822_PHYCR_BYPASS_LED_STRETCH 0x0080
308 #define DP83822_PHYCR_LED_CONFIG 0x0020
309 #define DP83822_PHYCR_PHY_ADDR 0x001F
310 
311 //10Base-T Status/Control register
312 #define DP83822_10BTSCR_RX_THRESHOLD_EN 0x2000
313 #define DP83822_10BTSCR_SQUELCH 0x1E00
314 #define DP83822_10BTSCR_NLP_DIS 0x0080
315 #define DP83822_10BTSCR_POLARITY_STATUS 0x0010
316 #define DP83822_10BTSCR_JABBER_DIS 0x0001
317 
318 //BIST Control and Status 1 register
319 #define DP83822_BICSR1_BIST_ERROR_COUNT 0xFF00
320 #define DP83822_BICSR1_BIST_IPG_LENGTH 0x00FF
321 
322 //BIST Control and Status 2 register
323 #define DP83822_BICSR2_BIST_PACKET_LENGTH 0x07FF
324 
325 //Cable Diagnostic Control register
326 #define DP83822_CDCR_CABLE_DIAG_START 0x8000
327 #define DP83822_CDCR_CDCR_CABLE_DIAG_STATUS 0x0002
328 #define DP83822_CDCR_CDCR_CABLE_DIAG_TEST_FAIL 0x0001
329 
330 //PHY Reset Control register
331 #define DP83822_PHYRCR_SOFT_RESET 0x8000
332 #define DP83822_PHYRCR_DIGITAL_RESTART 0x4000
333 
334 //C++ guard
335 #ifdef __cplusplus
336 extern "C" {
337 #endif
338 
339 //DP83822 Ethernet PHY driver
340 extern const PhyDriver dp83822PhyDriver;
341 
342 //DP83822 related functions
343 error_t dp83822Init(NetInterface *interface);
344 
345 void dp83822Tick(NetInterface *interface);
346 
347 void dp83822EnableIrq(NetInterface *interface);
348 void dp83822DisableIrq(NetInterface *interface);
349 
350 void dp83822EventHandler(NetInterface *interface);
351 
352 void dp83822WritePhyReg(NetInterface *interface, uint8_t address,
353  uint16_t data);
354 
355 uint16_t dp83822ReadPhyReg(NetInterface *interface, uint8_t address);
356 
357 void dp83822DumpPhyReg(NetInterface *interface);
358 
359 //C++ guard
360 #ifdef __cplusplus
361 }
362 #endif
363 
364 #endif
PHY driver.
Definition: nic.h:214
void dp83822EventHandler(NetInterface *interface)
DP83822 event handler.
void dp83822DisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t dp83822ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
const PhyDriver dp83822PhyDriver
DP83822 Ethernet PHY driver.
error_t
Error codes.
Definition: error.h:42
#define NetInterface
Definition: net.h:36
void dp83822WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
void dp83822EnableIrq(NetInterface *interface)
Enable interrupts.
Network interface controller abstraction layer.
Ipv6Addr address
uint8_t data[]
Definition: dtls_misc.h:176
error_t dp83822Init(NetInterface *interface)
DP83822 PHY transceiver initialization.
void dp83822DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
void dp83822Tick(NetInterface *interface)
DP83822 timer handler.