dp83848_driver.h
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1 /**
2  * @file dp83848_driver.h
3  * @brief DP83848 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _DP83848_DRIVER_H
32 #define _DP83848_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //PHY address
38 #ifndef DP83848_PHY_ADDR
39  #define DP83848_PHY_ADDR 1
40 #elif (DP83848_PHY_ADDR < 0 || DP83848_PHY_ADDR > 31)
41  #error DP83848_PHY_ADDR parameter is not valid
42 #endif
43 
44 //DP83848 PHY registers
45 #define DP83848_BMCR 0x00
46 #define DP83848_BMSR 0x01
47 #define DP83848_PHYID1 0x02
48 #define DP83848_PHYID2 0x03
49 #define DP83848_ANAR 0x04
50 #define DP83848_ANLPAR 0x05
51 #define DP83848_ANER 0x06
52 #define DP83848_ANNPR 0x07
53 #define DP83848_PHYSTS 0x10
54 #define DP83848_MICR 0x11
55 #define DP83848_MISR 0x12
56 #define DP83848_FCSCR 0x14
57 #define DP83848_RECR 0x15
58 #define DP83848_PCSR 0x16
59 #define DP83848_RBR 0x17
60 #define DP83848_LEDCR 0x18
61 #define DP83848_PHYCR 0x19
62 #define DP83848_10BTSCR 0x1A
63 #define DP83848_CDCTRL1 0x1B
64 #define DP83848_EDCR 0x1D
65 
66 //Basic Mode Control register
67 #define DP83848_BMCR_RESET 0x8000
68 #define DP83848_BMCR_LOOPBACK 0x4000
69 #define DP83848_BMCR_SPEED_SEL 0x2000
70 #define DP83848_BMCR_AN_EN 0x1000
71 #define DP83848_BMCR_POWER_DOWN 0x0800
72 #define DP83848_BMCR_ISOLATE 0x0400
73 #define DP83848_BMCR_RESTART_AN 0x0200
74 #define DP83848_BMCR_DUPLEX_MODE 0x0100
75 #define DP83848_BMCR_COL_TEST 0x0080
76 
77 //Basic Mode Status register
78 #define DP83848_BMSR_100BT4 0x8000
79 #define DP83848_BMSR_100BTX_FD 0x4000
80 #define DP83848_BMSR_100BTX_HD 0x2000
81 #define DP83848_BMSR_10BT_FD 0x1000
82 #define DP83848_BMSR_10BT_HD 0x0800
83 #define DP83848_BMSR_MF_PREAMBLE_SUPPR 0x0040
84 #define DP83848_BMSR_AN_COMPLETE 0x0020
85 #define DP83848_BMSR_REMOTE_FAULT 0x0010
86 #define DP83848_BMSR_AN_CAPABLE 0x0008
87 #define DP83848_BMSR_LINK_STATUS 0x0004
88 #define DP83848_BMSR_JABBER_DETECT 0x0002
89 #define DP83848_BMSR_EXTENDED_CAPABLE 0x0001
90 
91 //PHY Identifier 1 register
92 #define DP83848_PHYID1_OUI_MSB 0xFFFF
93 #define DP83848_PHYID1_OUI_MSB_DEFAULT 0x2000
94 
95 //PHY Identifier 2 register
96 #define DP83848_PHYID2_OUI_LSB 0xFC00
97 #define DP83848_PHYID2_OUI_LSB_DEFAULT 0x5C00
98 #define DP83848_PHYID2_VNDR_MDL 0x03F0
99 #define DP83848_PHYID2_VNDR_MDL_DEFAULT 0x0090
100 #define DP83848_PHYID2_MDL_REV 0x000F
101 
102 //Auto-Negotiation Advertisement register
103 #define DP83848_ANAR_NEXT_PAGE 0x8000
104 #define DP83848_ANAR_REMOTE_FAULT 0x2000
105 #define DP83848_ANAR_ASM_DIR 0x0800
106 #define DP83848_ANAR_PAUSE 0x0400
107 #define DP83848_ANAR_100BT4 0x0200
108 #define DP83848_ANAR_100BTX_FD 0x0100
109 #define DP83848_ANAR_100BTX_HD 0x0080
110 #define DP83848_ANAR_10BT_FD 0x0040
111 #define DP83848_ANAR_10BT_HD 0x0020
112 #define DP83848_ANAR_SELECTOR 0x001F
113 #define DP83848_ANAR_SELECTOR_DEFAULT 0x0001
114 
115 //Auto-Negotiation Link Partner Ability register
116 #define DP83848_ANLPAR_NEXT_PAGE 0x8000
117 #define DP83848_ANLPAR_ACK 0x4000
118 #define DP83848_ANLPAR_REMOTE_FAULT 0x2000
119 #define DP83848_ANLPAR_ASM_DIR 0x0800
120 #define DP83848_ANLPAR_PAUSE 0x0400
121 #define DP83848_ANLPAR_100BT4 0x0200
122 #define DP83848_ANLPAR_100BTX_FD 0x0100
123 #define DP83848_ANLPAR_100BTX_HD 0x0080
124 #define DP83848_ANLPAR_10BT_FD 0x0040
125 #define DP83848_ANLPAR_10BT_HD 0x0020
126 #define DP83848_ANLPAR_SELECTOR 0x001F
127 #define DP83848_ANLPAR_SELECTOR_DEFAULT 0x0001
128 
129 //Auto-Negotiation Expansion register
130 #define DP83848_ANER_PAR_DETECT_FAULT 0x0010
131 #define DP83848_ANER_LP_NP_ABLE 0x0008
132 #define DP83848_ANER_NP_ABLE 0x0004
133 #define DP83848_ANER_PAGE_RX 0x0002
134 #define DP83848_ANER_LP_AN_ABLE 0x0001
135 
136 //Auto-Negotiation Next Page TX register
137 #define DP83848_ANNPR_NEXT_PAGE 0x8000
138 #define DP83848_ANNPR_MSG_PAGE 0x2000
139 #define DP83848_ANNPR_ACK2 0x1000
140 #define DP83848_ANNPR_TOGGLE 0x0800
141 #define DP83848_ANNPR_CODE 0x07FF
142 
143 //PHY Status register
144 #define DP83848_PHYSTS_MDIX_MODE 0x4000
145 #define DP83848_PHYSTS_RECEIVE_ERROR_LATCH 0x2000
146 #define DP83848_PHYSTS_POLARITY_STATUS 0x1000
147 #define DP83848_PHYSTS_FCS_LATCH 0x0800
148 #define DP83848_PHYSTS_SIGNAL_DETECT 0x0400
149 #define DP83848_PHYSTS_DESCRAMBLER_LOCK 0x0200
150 #define DP83848_PHYSTS_PAGE_RECEIVED 0x0100
151 #define DP83848_PHYSTS_MII_INTERRUPT 0x0080
152 #define DP83848_PHYSTS_REMOTE_FAULT 0x0040
153 #define DP83848_PHYSTS_JABBER_DETECT 0x0020
154 #define DP83848_PHYSTS_AN_COMPLETE 0x0010
155 #define DP83848_PHYSTS_LOOPBACK_STATUS 0x0008
156 #define DP83848_PHYSTS_DUPLEX_STATUS 0x0004
157 #define DP83848_PHYSTS_SPEED_STATUS 0x0002
158 #define DP83848_PHYSTS_LINK_STATUS 0x0001
159 
160 //MII Interrupt Control register
161 #define DP83848_MICR_TINT 0x0004
162 #define DP83848_MICR_INTEN 0x0002
163 #define DP83848_MICR_INT_OE 0x0001
164 
165 //MII Interrupt Status register
166 #define DP83848_MISR_ED_INT 0x4000
167 #define DP83848_MISR_LINK_INT 0x2000
168 #define DP83848_MISR_SPD_INT 0x1000
169 #define DP83848_MISR_DUP_INT 0x0800
170 #define DP83848_MISR_ANC_INT 0x0400
171 #define DP83848_MISR_FHF_INT 0x0200
172 #define DP83848_MISR_RHF_INT 0x0100
173 #define DP83848_MISR_ED_INT_EN 0x0040
174 #define DP83848_MISR_LINK_INT_EN 0x0020
175 #define DP83848_MISR_SPD_INT_EN 0x0010
176 #define DP83848_MISR_DUP_INT_EN 0x0008
177 #define DP83848_MISR_ANC_INT_EN 0x0004
178 #define DP83848_MISR_FHF_INT_EN 0x0002
179 #define DP83848_MISR_RHF_INT_EN 0x0001
180 
181 //False Carrier Sense Counter register
182 #define DP83848_FCSCR_FCSCNT 0x00FF
183 
184 //Receive Error Counter register
185 #define DP83848_RECR_RXERCNT 0x00FF
186 
187 //PCS Sub-Layer Configuration and Status register
188 #define DP83848_PCSR_TQ_EN 0x0400
189 #define DP83848_PCSR_SD_FORCE_PMA 0x0200
190 #define DP83848_PCSR_SD_OPTION 0x0100
191 #define DP83848_PCSR_DESC_TIME 0x0080
192 #define DP83848_PCSR_FORCE_100_OK 0x0020
193 #define DP83848_PCSR_NRZI_BYPASS 0x0004
194 
195 //RMII and Bypass register
196 #define DP83848_RBR_RMII_MODE 0x0020
197 #define DP83848_RBR_RMII_REV1_0 0x0010
198 #define DP83848_RBR_RX_OVF_STS 0x0008
199 #define DP83848_RBR_RX_UNF_STS 0x0004
200 #define DP83848_RBR_ELAST_BUF 0x0003
201 
202 //LED Direct Control register
203 #define DP83848_LEDCR_DRV_SPDLED 0x0020
204 #define DP83848_LEDCR_DRV_LNKLED 0x0010
205 #define DP83848_LEDCR_DRV_ACTLED 0x0008
206 #define DP83848_LEDCR_SPDLED 0x0004
207 #define DP83848_LEDCR_LNKLED 0x0002
208 #define DP83848_LEDCR_ACTLED 0x0001
209 
210 //PHY Control register
211 #define DP83848_PHYCR_MDIX_EN 0x8000
212 #define DP83848_PHYCR_FORCE_MDIX 0x4000
213 #define DP83848_PHYCR_PAUSE_RX 0x2000
214 #define DP83848_PHYCR_PAUSE_TX 0x1000
215 #define DP83848_PHYCR_BIST_FE 0x0800
216 #define DP83848_PHYCR_PSR_15 0x0400
217 #define DP83848_PHYCR_BIST_STATUS 0x0200
218 #define DP83848_PHYCR_BIST_START 0x0100
219 #define DP83848_PHYCR_BP_STRETCH 0x0080
220 #define DP83848_PHYCR_LED_CNFG 0x0060
221 #define DP83848_PHYCR_PHYADDR 0x001F
222 
223 //10Base-T Status/Control register
224 #define DP83848_10BTSCR_10BT_SERIAL 0x8000
225 #define DP83848_10BTSCR_SQUELCH 0x0E00
226 #define DP83848_10BTSCR_LOOPBACK_10_DIS 0x0100
227 #define DP83848_10BTSCR_LP_DIS 0x0080
228 #define DP83848_10BTSCR_FORCE_LINK_10 0x0040
229 #define DP83848_10BTSCR_POLARITY 0x0010
230 #define DP83848_10BTSCR_HEARTBEAT_DIS 0x0002
231 #define DP83848_10BTSCR_JABBER_DIS 0x0001
232 
233 //CD Test Control and BIST Extensions register
234 #define DP83848_CDCTRL1_BIST_ERROR_COUNT 0xFF00
235 #define DP83848_CDCTRL1_BIST_CONT_MODE 0x0020
236 #define DP83848_CDCTRL1_CDPATTEN_10 0x0010
237 #define DP83848_CDCTRL1_10MEG_PATT_GAP 0x0004
238 #define DP83848_CDCTRL1_CDPATTSEL 0x0003
239 
240 //Energy Detect Control register
241 #define DP83848_EDCR_ED_EN 0x8000
242 #define DP83848_EDCR_ED_AUTO_UP 0x4000
243 #define DP83848_EDCR_ED_AUTO_DOWN 0x2000
244 #define DP83848_EDCR_ED_MAN 0x1000
245 #define DP83848_EDCR_ED_BURST_DIS 0x0800
246 #define DP83848_EDCR_ED_PWR_STATE 0x0400
247 #define DP83848_EDCR_ED_ERR_MET 0x0200
248 #define DP83848_EDCR_ED_DATA_MET 0x0100
249 #define DP83848_EDCR_ED_ERR_COUNT 0x00F0
250 #define DP83848_EDCR_ED_DATA_COUNT 0x000F
251 
252 //C++ guard
253 #ifdef __cplusplus
254 extern "C" {
255 #endif
256 
257 //DP83848 Ethernet PHY driver
258 extern const PhyDriver dp83848PhyDriver;
259 
260 //DP83848 related functions
261 error_t dp83848Init(NetInterface *interface);
262 
263 void dp83848Tick(NetInterface *interface);
264 
265 void dp83848EnableIrq(NetInterface *interface);
266 void dp83848DisableIrq(NetInterface *interface);
267 
268 void dp83848EventHandler(NetInterface *interface);
269 
270 void dp83848WritePhyReg(NetInterface *interface, uint8_t address,
271  uint16_t data);
272 
273 uint16_t dp83848ReadPhyReg(NetInterface *interface, uint8_t address);
274 
275 void dp83848DumpPhyReg(NetInterface *interface);
276 
277 //C++ guard
278 #ifdef __cplusplus
279 }
280 #endif
281 
282 #endif
void dp83848DisableIrq(NetInterface *interface)
Disable interrupts.
PHY driver.
Definition: nic.h:214
void dp83848EnableIrq(NetInterface *interface)
Enable interrupts.
void dp83848DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
error_t
Error codes.
Definition: error.h:42
#define NetInterface
Definition: net.h:36
void dp83848EventHandler(NetInterface *interface)
DP83848 event handler.
void dp83848WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
error_t dp83848Init(NetInterface *interface)
DP83848 PHY transceiver initialization.
uint16_t dp83848ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
Network interface controller abstraction layer.
const PhyDriver dp83848PhyDriver
DP83848 Ethernet PHY driver.
Ipv6Addr address
void dp83848Tick(NetInterface *interface)
DP83848 timer handler.
uint8_t data[]
Definition: dtls_misc.h:176