dp83848_driver.h
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1 /**
2  * @file dp83848_driver.h
3  * @brief DP83848 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _DP83848_DRIVER_H
30 #define _DP83848_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef DP83848_PHY_ADDR
37  #define DP83848_PHY_ADDR 1
38 #elif (DP83848_PHY_ADDR < 0 || DP83848_PHY_ADDR > 31)
39  #error DP83848_PHY_ADDR parameter is not valid
40 #endif
41 
42 //DP83848 registers
43 #define DP83848_PHY_REG_BMCR 0x00
44 #define DP83848_PHY_REG_BMSR 0x01
45 #define DP83848_PHY_REG_PHYIDR1 0x02
46 #define DP83848_PHY_REG_PHYIDR2 0x03
47 #define DP83848_PHY_REG_ANAR 0x04
48 #define DP83848_PHY_REG_ANLPAR 0x05
49 #define DP83848_PHY_REG_ANER 0x06
50 #define DP83848_PHY_REG_ANNPTR 0x07
51 #define DP83848_PHY_REG_PHYSTS 0x10
52 #define DP83848_PHY_REG_MICR 0x11
53 #define DP83848_PHY_REG_MISR 0x12
54 #define DP83848_PHY_REG_FCSCR 0x14
55 #define DP83848_PHY_REG_RECR 0x15
56 #define DP83848_PHY_REG_PCSR 0x16
57 #define DP83848_PHY_REG_RBR 0x17
58 #define DP83848_PHY_REG_LEDCR 0x18
59 #define DP83848_PHY_REG_PHYCR 0x19
60 #define DP83848_PHY_REG_10BTSCR 0x1A
61 #define DP83848_PHY_REG_CDCTRL1 0x1B
62 #define DP83848_PHY_REG_EDCR 0x1D
63 
64 //BMCR register
65 #define BMCR_RESET (1 << 15)
66 #define BMCR_LOOPBACK (1 << 14)
67 #define BMCR_SPEED_SEL (1 << 13)
68 #define BMCR_AN_EN (1 << 12)
69 #define BMCR_POWER_DOWN (1 << 11)
70 #define BMCR_ISOLATE (1 << 10)
71 #define BMCR_RESTART_AN (1 << 9)
72 #define BMCR_DUPLEX_MODE (1 << 8)
73 #define BMCR_COL_TEST (1 << 7)
74 
75 //BMSR register
76 #define BMSR_100BT4 (1 << 15)
77 #define BMSR_100BTX_FD (1 << 14)
78 #define BMSR_100BTX (1 << 13)
79 #define BMSR_10BT_FD (1 << 12)
80 #define BMSR_10BT (1 << 11)
81 #define BMSR_NO_PREAMBLE (1 << 6)
82 #define BMSR_AN_COMPLETE (1 << 5)
83 #define BMSR_REMOTE_FAULT (1 << 4)
84 #define BMSR_AN_ABLE (1 << 3)
85 #define BMSR_LINK_STATUS (1 << 2)
86 #define BMSR_JABBER_DETECT (1 << 1)
87 #define BMSR_EXTENDED_CAP (1 << 0)
88 
89 //ANAR register
90 #define ANAR_NP (1 << 15)
91 #define ANAR_RF (1 << 13)
92 #define ANAR_ASM_DIR (1 << 11)
93 #define ANAR_PAUSE (1 << 10)
94 #define ANAR_100BT4 (1 << 9)
95 #define ANAR_100BTX_FD (1 << 8)
96 #define ANAR_100BTX (1 << 7)
97 #define ANAR_10BT_FD (1 << 6)
98 #define ANAR_10BT (1 << 5)
99 #define ANAR_SELECTOR4 (1 << 4)
100 #define ANAR_SELECTOR3 (1 << 3)
101 #define ANAR_SELECTOR2 (1 << 2)
102 #define ANAR_SELECTOR1 (1 << 1)
103 #define ANAR_SELECTOR0 (1 << 0)
104 
105 //ANLPAR register
106 #define ANLPAR_NP (1 << 15)
107 #define ANLPAR_ACK (1 << 14)
108 #define ANLPAR_RF (1 << 13)
109 #define ANLPAR_ASM_DIR (1 << 11)
110 #define ANLPAR_PAUSE (1 << 10)
111 #define ANLPAR_100BT4 (1 << 9)
112 #define ANLPAR_100BTX_FD (1 << 8)
113 #define ANLPAR_100BTX (1 << 7)
114 #define ANLPAR_10BT_FD (1 << 6)
115 #define ANLPAR_10BT (1 << 5)
116 #define ANLPAR_SELECTOR4 (1 << 4)
117 #define ANLPAR_SELECTOR3 (1 << 3)
118 #define ANLPAR_SELECTOR2 (1 << 2)
119 #define ANLPAR_SELECTOR1 (1 << 1)
120 #define ANLPAR_SELECTOR0 (1 << 0)
121 
122 //ANER register
123 #define ANER_PDF (1 << 4)
124 #define ANER_LP_NP_ABLE (1 << 3)
125 #define ANER_NP_ABLE (1 << 2)
126 #define ANER_PAGE_RX (1 << 1)
127 #define ANER_LP_AN_ABLE (1 << 0)
128 
129 //ANNPTR register
130 #define ANNPTR_NP (1 << 15)
131 #define ANNPTR_MP (1 << 13)
132 #define ANNPTR_ACK2 (1 << 12)
133 #define ANNPTR_TOG_TX (1 << 11)
134 #define ANNPTR_CODE10 (1 << 10)
135 #define ANNPTR_CODE9 (1 << 9)
136 #define ANNPTR_CODE8 (1 << 8)
137 #define ANNPTR_CODE7 (1 << 7)
138 #define ANNPTR_CODE6 (1 << 6)
139 #define ANNPTR_CODE5 (1 << 5)
140 #define ANNPTR_CODE4 (1 << 4)
141 #define ANNPTR_CODE3 (1 << 3)
142 #define ANNPTR_CODE2 (1 << 2)
143 #define ANNPTR_CODE1 (1 << 1)
144 #define ANNPTR_CODE0 (1 << 0)
145 
146 //PHYSTS register
147 #define PHYSTS_MDIX_MODE (1 << 14)
148 #define PHYSTS_RX_ERROR_LATCH (1 << 13)
149 #define PHYSTS_POLARITY_STATUS (1 << 12)
150 #define PHYSTS_FALSE_CARRIER_SENSE (1 << 11)
151 #define PHYSTS_SIGNAL_DETECT (1 << 10)
152 #define PHYSTS_DESCRAMBLER_LOCK (1 << 9)
153 #define PHYSTS_PAGE_RECEIVED (1 << 8)
154 #define PHYSTS_MII_INTERRUPT (1 << 7)
155 #define PHYSTS_REMOTE_FAULT (1 << 6)
156 #define PHYSTS_JABBER_DETECT (1 << 5)
157 #define PHYSTS_AN_COMPLETE (1 << 4)
158 #define PHYSTS_LOOPBACK_STATUS (1 << 3)
159 #define PHYSTS_DUPLEX_STATUS (1 << 2)
160 #define PHYSTS_SPEED_STATUS (1 << 1)
161 #define PHYSTS_LINK_STATUS (1 << 0)
162 
163 //MICR register
164 #define MICR_TINT (1 << 2)
165 #define MICR_INTEN (1 << 1)
166 #define MICR_INT_OE (1 << 0)
167 
168 //MISR register
169 #define MISR_ED_INT (1 << 14)
170 #define MISR_LINK_INT (1 << 13)
171 #define MISR_SPD_INT (1 << 12)
172 #define MISR_DUP_INT (1 << 11)
173 #define MISR_ANC_INT (1 << 10)
174 #define MISR_FHF_INT (1 << 9)
175 #define MISR_RHF_INT (1 << 8)
176 #define MISR_ED_INT_EN (1 << 6)
177 #define MISR_LINK_INT_EN (1 << 5)
178 #define MISR_SPD_INT_EN (1 << 4)
179 #define MISR_DUP_INT_EN (1 << 3)
180 #define MISR_ANC_INT_EN (1 << 2)
181 #define MISR_FHF_INT_EN (1 << 1)
182 #define MISR_RHF_INT_EN (1 << 0)
183 
184 //FCSCR register
185 #define FCSCR_FCSCNT7 (1 << 7)
186 #define FCSCR_FCSCNT6 (1 << 6)
187 #define FCSCR_FCSCNT5 (1 << 5)
188 #define FCSCR_FCSCNT4 (1 << 4)
189 #define FCSCR_FCSCNT3 (1 << 3)
190 #define FCSCR_FCSCNT2 (1 << 2)
191 #define FCSCR_FCSCNT1 (1 << 1)
192 #define FCSCR_FCSCNT0 (1 << 0)
193 
194 //RECR register
195 #define RECR_RXERCNT7 (1 << 7)
196 #define RECR_RXERCNT6 (1 << 6)
197 #define RECR_RXERCNT5 (1 << 5)
198 #define RECR_RXERCNT4 (1 << 4)
199 #define RECR_RXERCNT3 (1 << 3)
200 #define RECR_RXERCNT2 (1 << 2)
201 #define RECR_RXERCNT1 (1 << 1)
202 #define RECR_RXERCNT0 (1 << 0)
203 
204 //PCSR register
205 #define PCSR_TQ_EN (1 << 10)
206 #define PCSR_SD_FORCE_PMA (1 << 9)
207 #define PCSR_SD_OPTION (1 << 8)
208 #define PCSR_DESC_TIME (1 << 7)
209 #define PCSR_FORCE_100_OK (1 << 5)
210 #define PCSR_NRZI_BYPASS (1 << 2)
211 
212 //RBR register
213 #define RBR_RMII_MODE (1 << 5)
214 #define RBR_RMII_REV1_0 (1 << 4)
215 #define RBR_RX_OVF_STS (1 << 3)
216 #define RBR_RX_UNF_STS (1 << 2)
217 #define RBR_ELAST_BUF1 (1 << 1)
218 #define RBR_ELAST_BUF0 (1 << 0)
219 
220 //LEDCR register
221 #define LEDCR_DRV_SPDLED (1 << 5)
222 #define LEDCR_DRV_LNKLED (1 << 4)
223 #define LEDCR_DRV_ACTLED (1 << 3)
224 #define LEDCR_SPDLED (1 << 2)
225 #define LEDCR_LNKLED (1 << 1)
226 #define LEDCR_ACTLED (1 << 0)
227 
228 //PHYCR register
229 #define PHYCR_MDIX_EN (1 << 15)
230 #define PHYCR_FORCE_MDIX (1 << 14)
231 #define PHYCR_PAUSE_RX (1 << 13)
232 #define PHYCR_PAUSE_TX (1 << 12)
233 #define PHYCR_BIST_FE (1 << 11)
234 #define PHYCR_PSR_15 (1 << 10)
235 #define PHYCR_BIST_STATUS (1 << 9)
236 #define PHYCR_BIST_START (1 << 8)
237 #define PHYCR_BP_STRETCH (1 << 7)
238 #define PHYCR_LED_CNFG1 (1 << 6)
239 #define PHYCR_LED_CNFG0 (1 << 5)
240 #define PHYCR_PHYADDR4 (1 << 4)
241 #define PHYCR_PHYADDR3 (1 << 3)
242 #define PHYCR_PHYADDR2 (1 << 2)
243 #define PHYCR_PHYADDR1 (1 << 1)
244 #define PHYCR_PHYADDR0 (1 << 0)
245 
246 //10BTSCR register
247 #define _10BTSCR_10BT_SERIAL (1 << 15)
248 #define _10BTSCR_SQUELCH2 (1 << 11)
249 #define _10BTSCR_SQUELCH1 (1 << 10)
250 #define _10BTSCR_SQUELCH0 (1 << 9)
251 #define _10BTSCR_LOOPBACK_10_DIS (1 << 8)
252 #define _10BTSCR_LP_DIS (1 << 7)
253 #define _10BTSCR_FORCE_LINK_10 (1 << 6)
254 #define _10BTSCR_POLARITY (1 << 4)
255 #define _10BTSCR_HEARTBEAT_DIS (1 << 1)
256 #define _10BTSCR_JABBER_DIS (1 << 0)
257 
258 //CDCTRL1 register
259 #define CDCTRL1_BIST_ERROR_COUNT7 (1 << 15)
260 #define CDCTRL1_BIST_ERROR_COUNT6 (1 << 14)
261 #define CDCTRL1_BIST_ERROR_COUNT5 (1 << 13)
262 #define CDCTRL1_BIST_ERROR_COUNT4 (1 << 12)
263 #define CDCTRL1_BIST_ERROR_COUNT3 (1 << 11)
264 #define CDCTRL1_BIST_ERROR_COUNT2 (1 << 10)
265 #define CDCTRL1_BIST_ERROR_COUNT1 (1 << 9)
266 #define CDCTRL1_BIST_ERROR_COUNT0 (1 << 8)
267 #define CDCTRL1_BIST_CONT_MODE (1 << 5)
268 #define CDCTRL1_CDPATTEN_10 (1 << 4)
269 #define CDCTRL1_10MEG_PATT_GAP (1 << 2)
270 #define CDCTRL1_CDPATTSEL1 (1 << 1)
271 #define CDCTRL1_CDPATTSEL0 (1 << 0)
272 
273 //EDCR register
274 #define EDCR_ED_EN (1 << 15)
275 #define EDCR_ED_AUTO_UP (1 << 14)
276 #define EDCR_ED_AUTO_DOWN (1 << 13)
277 #define EDCR_ED_MAN (1 << 12)
278 #define EDCR_ED_BURST_DIS (1 << 11)
279 #define EDCR_ED_PWR_STATE (1 << 10)
280 #define EDCR_ED_ERR_MET (1 << 9)
281 #define EDCR_ED_DATA_MET (1 << 8)
282 #define EDCR_ED_ERR_COUNT3 (1 << 7)
283 #define EDCR_ED_ERR_COUNT2 (1 << 6)
284 #define EDCR_ED_ERR_COUNT1 (1 << 5)
285 #define EDCR_ED_ERR_COUNT0 (1 << 4)
286 #define EDCR_ED_DATA_COUNT3 (1 << 3)
287 #define EDCR_ED_DATA_COUNT2 (1 << 2)
288 #define EDCR_ED_DATA_COUNT1 (1 << 1)
289 #define EDCR_ED_DATA_COUNT0 (1 << 0)
290 
291 //C++ guard
292 #ifdef __cplusplus
293  extern "C" {
294 #endif
295 
296 //DP83848 Ethernet PHY driver
297 extern const PhyDriver dp83848PhyDriver;
298 
299 //DP83848 related functions
300 error_t dp83848Init(NetInterface *interface);
301 
302 void dp83848Tick(NetInterface *interface);
303 
304 void dp83848EnableIrq(NetInterface *interface);
305 void dp83848DisableIrq(NetInterface *interface);
306 
307 void dp83848EventHandler(NetInterface *interface);
308 
309 void dp83848WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
310 uint16_t dp83848ReadPhyReg(NetInterface *interface, uint8_t address);
311 
312 void dp83848DumpPhyReg(NetInterface *interface);
313 
314 //C++ guard
315 #ifdef __cplusplus
316  }
317 #endif
318 
319 #endif
void dp83848EventHandler(NetInterface *interface)
DP83848 event handler.
error_t dp83848Init(NetInterface *interface)
DP83848 PHY transceiver initialization.
const PhyDriver dp83848PhyDriver
DP83848 Ethernet PHY driver.
void dp83848WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
void dp83848EnableIrq(NetInterface *interface)
Enable interrupts.
PHY driver.
Definition: nic.h:196
uint16_t dp83848ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
void dp83848Tick(NetInterface *interface)
DP83848 timer handler.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void dp83848DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
Network interface controller abstraction layer.
void dp83848DisableIrq(NetInterface *interface)
Disable interrupts.