ip101_driver.h
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1 /**
2  * @file ip101_driver.h
3  * @brief IC+ IP101 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _IP101_DRIVER_H
30 #define _IP101_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef IP101_PHY_ADDR
37  #define IP101_PHY_ADDR 1
38 #elif (IP101_PHY_ADDR < 0 || IP101_PHY_ADDR > 31)
39  #error IP101_PHY_ADDR parameter is not valid
40 #endif
41 
42 //IP101 registers
43 #define IP101_PHY_REG_BMCR 0x00
44 #define IP101_PHY_REG_BMSR 0x01
45 #define IP101_PHY_REG_PHYIDR1 0x02
46 #define IP101_PHY_REG_PHYIDR2 0x03
47 #define IP101_PHY_REG_ANAR 0x04
48 #define IP101_PHY_REG_ANLPAR 0x05
49 #define IP101_PHY_REG_ANER 0x06
50 #define IP101_PHY_REG_ANNPTR 0x07
51 #define IP101_PHY_REG_LPNPAR 0x08
52 #define IP101_PHY_REG_MMDACR 0x0D
53 #define IP101_PHY_REG_MMDAADR 0x0E
54 #define IP101_PHY_REG_PHYSCR 0x10
55 #define IP101_PHY_REG_ICSR 0x11
56 #define IP101_PHY_REG_PHYSMR 0x12
57 #define IP101_PHY_REG_IOSCR 0x1D
58 #define IP101_PHY_REG_PHYMCSSR 0x1E
59 
60 //BMCR register
61 #define BMCR_RESET (1 << 15)
62 #define BMCR_LOOPBACK (1 << 14)
63 #define BMCR_SPEED_SEL (1 << 13)
64 #define BMCR_AN_EN (1 << 12)
65 #define BMCR_POWER_DOWN (1 << 11)
66 #define BMCR_ISOLATE (1 << 10)
67 #define BMCR_RESTART_AN (1 << 9)
68 #define BMCR_DUPLEX_MODE (1 << 8)
69 #define BMCR_COL_TEST (1 << 7)
70 
71 //BMSR register
72 #define BMSR_100BT4 (1 << 15)
73 #define BMSR_100BTX_FD (1 << 14)
74 #define BMSR_100BTX (1 << 13)
75 #define BMSR_10BT_FD (1 << 12)
76 #define BMSR_10BT (1 << 11)
77 #define BMSR_NO_PREAMBLE (1 << 6)
78 #define BMSR_AN_COMPLETE (1 << 5)
79 #define BMSR_REMOTE_FAULT (1 << 4)
80 #define BMSR_AN_ABLE (1 << 3)
81 #define BMSR_LINK_STATUS (1 << 2)
82 #define BMSR_JABBER_DETECT (1 << 1)
83 #define BMSR_EXTENDED_CAP (1 << 0)
84 
85 //ANAR register
86 #define ANAR_NP (1 << 15)
87 #define ANAR_RF (1 << 13)
88 #define ANAR_ASYMMETRIC_PAUSE (1 << 11)
89 #define ANAR_PAUSE (1 << 10)
90 #define ANAR_100BT4 (1 << 9)
91 #define ANAR_100BTX_FD (1 << 8)
92 #define ANAR_100BTX (1 << 7)
93 #define ANAR_10BT_FD (1 << 6)
94 #define ANAR_10BT (1 << 5)
95 #define ANAR_SELECTOR4 (1 << 4)
96 #define ANAR_SELECTOR3 (1 << 3)
97 #define ANAR_SELECTOR2 (1 << 2)
98 #define ANAR_SELECTOR1 (1 << 1)
99 #define ANAR_SELECTOR0 (1 << 0)
100 
101 //ANLPAR register
102 #define ANLPAR_NP (1 << 15)
103 #define ANLPAR_ACK (1 << 14)
104 #define ANLPAR_RF (1 << 13)
105 #define ANLPAR_ASYMMETRIC_PAUSE (1 << 11)
106 #define ANLPAR_PAUSE (1 << 10)
107 #define ANLPAR_100BT4 (1 << 9)
108 #define ANLPAR_100BTX_FD (1 << 8)
109 #define ANLPAR_100BTX (1 << 7)
110 #define ANLPAR_10BT_FD (1 << 6)
111 #define ANLPAR_10BT (1 << 5)
112 #define ANLPAR_SELECTOR4 (1 << 4)
113 #define ANLPAR_SELECTOR3 (1 << 3)
114 #define ANLPAR_SELECTOR2 (1 << 2)
115 #define ANLPAR_SELECTOR1 (1 << 1)
116 #define ANLPAR_SELECTOR0 (1 << 0)
117 
118 //ANER register
119 #define ANER_MLF (1 << 4)
120 #define ANER_LP_NP_ABLE (1 << 3)
121 #define ANER_NP_ABLE (1 << 2)
122 #define ANER_PAGE_RX (1 << 1)
123 #define ANER_LP_AN_ABLE (1 << 0)
124 
125 //ANNPTR register
126 #define ANNPTR_NP (1 << 15)
127 #define ANNPTR_MP (1 << 13)
128 #define ANNPTR_ACK2 (1 << 12)
129 #define ANNPTR_TOGGLE (1 << 11)
130 #define ANNPTR_CODE10 (1 << 10)
131 #define ANNPTR_CODE9 (1 << 9)
132 #define ANNPTR_CODE8 (1 << 8)
133 #define ANNPTR_CODE7 (1 << 7)
134 #define ANNPTR_CODE6 (1 << 6)
135 #define ANNPTR_CODE5 (1 << 5)
136 #define ANNPTR_CODE4 (1 << 4)
137 #define ANNPTR_CODE3 (1 << 3)
138 #define ANNPTR_CODE2 (1 << 2)
139 #define ANNPTR_CODE1 (1 << 1)
140 #define ANNPTR_CODE0 (1 << 0)
141 
142 //LPNPAR register
143 #define LPNPAR_NEXT_PAGE (1 << 15)
144 #define LPNPAR_MSG_PAGE (1 << 13)
145 #define LPNPAR_ACK2 (1 << 12)
146 #define LPNPAR_TOGGLE (1 << 11)
147 #define LPNPAR_MESSAGE10 (1 << 10)
148 #define LPNPAR_MESSAGE9 (1 << 9)
149 #define LPNPAR_MESSAGE8 (1 << 8)
150 #define LPNPAR_MESSAGE7 (1 << 7)
151 #define LPNPAR_MESSAGE6 (1 << 6)
152 #define LPNPAR_MESSAGE5 (1 << 5)
153 #define LPNPAR_MESSAGE4 (1 << 4)
154 #define LPNPAR_MESSAGE3 (1 << 3)
155 #define LPNPAR_MESSAGE2 (1 << 2)
156 #define LPNPAR_MESSAGE1 (1 << 1)
157 #define LPNPAR_MESSAGE0 (1 << 0)
158 
159 //MMDACR register
160 #define MMDACR_FUNCTION1 (1 << 15)
161 #define MMDACR_FUNCTION0 (1 << 14)
162 #define MMDACR_DEVAD4 (1 << 4)
163 #define MMDACR_DEVAD3 (1 << 3)
164 #define MMDACR_DEVAD2 (1 << 2)
165 #define MMDACR_DEVAD1 (1 << 1)
166 #define MMDACR_DEVAD0 (1 << 0)
167 
168 //PHYSCR register
169 #define PHYSCR_RMII_V10 (1 << 13)
170 #define PHYSCR_RMII_V12 (1 << 12)
171 #define PHYSCR_AUTO_MDIX_DIS (1 << 11)
172 #define PHYSCR_JABBER_ENABLE (1 << 9)
173 #define PHYSCR_FEF_DISABLE (1 << 8)
174 #define PHYSCR_NWAY_PSAVE_DIS (1 << 7)
175 #define PHYSCR_BYPASS_DSP_RESET (1 << 5)
176 #define PHYSCR_REPEATER_MODE (1 << 2)
177 #define PHYSCR_LDPS_ENABLE (1 << 1)
178 #define PHYSCR_ANALOG_OFF (1 << 0)
179 
180 //ICSR register
181 #define ICSR_INTR_EN (1 << 15)
182 #define ICSR_RESERVED2 (1 << 14)
183 #define ICSR_RESERVED1 (1 << 13)
184 #define ICSR_RESERVED0 (1 << 12)
185 #define ICSR_ALL_MASK (1 << 11)
186 #define ICSR_SPEED_MASK (1 << 10)
187 #define ICSR_DUPLEX_MASK (1 << 9)
188 #define ICSR_LINK_MASK (1 << 8)
189 #define ICSR_INTR_STATUS (1 << 3)
190 #define ICSR_SPEED_CHANGE (1 << 2)
191 #define ICSR_DUPLEX_CHANGE (1 << 1)
192 #define ICSR_LINK_CHANGE (1 << 0)
193 
194 //PHYSMR register
195 #define PHYSMR_SPEED (1 << 14)
196 #define PHYSMR_DUPLEX (1 << 13)
197 #define PHYSMR_AN_COMPLETE (1 << 11)
198 #define PHYSMR_LINK_UP (1 << 10)
199 #define PHYSMR_MDIX (1 << 9)
200 #define PHYSMR_POLARITY (1 << 8)
201 #define PHYSMR_JABBER (1 << 7)
202 #define PHYSMR_AN_ARBIT_STATE3 (1 << 3)
203 #define PHYSMR_AN_ARBIT_STATE2 (1 << 2)
204 #define PHYSMR_AN_ARBIT_STATE1 (1 << 1)
205 #define PHYSMR_AN_ARBIT_STATE0 (1 << 0)
206 
207 //IOSCR register
208 #define IOSCR_RMII_WITH_ER (1 << 7)
209 #define IOSCR_SEL_INTR32 (1 << 2)
210 
211 //PHYMCSSR register
212 #define PHYMCSSR_LINK_UP (1 << 8)
213 #define PHYMCSSR_FORCE_MDIX (1 << 3)
214 #define PHYMCSSR_OP_MODE2 (1 << 2)
215 #define PHYMCSSR_OP_MODE1 (1 << 1)
216 #define PHYMCSSR_OP_MODE0 (1 << 0)
217 
218 //Operation mode indication
219 #define PHYMCSSR_OP_MODE_MASK (7 << 0)
220 #define PHYMCSSR_OP_MODE_LINK_OFF (0 << 0)
221 #define PHYMCSSR_OP_MODE_10M_HD (1 << 0)
222 #define PHYMCSSR_OP_MODE_100M_HD (2 << 0)
223 #define PHYMCSSR_OP_MODE_10M_FD (5 << 0)
224 #define PHYMCSSR_OP_MODE_100_FD (6 << 0)
225 
226 //C++ guard
227 #ifdef __cplusplus
228  extern "C" {
229 #endif
230 
231 //IP101 Ethernet PHY driver
232 extern const PhyDriver ip101PhyDriver;
233 
234 //IP101 related functions
235 error_t ip101Init(NetInterface *interface);
236 
237 void ip101Tick(NetInterface *interface);
238 
239 void ip101EnableIrq(NetInterface *interface);
240 void ip101DisableIrq(NetInterface *interface);
241 
242 void ip101EventHandler(NetInterface *interface);
243 
244 void ip101WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
245 uint16_t ip101ReadPhyReg(NetInterface *interface, uint8_t address);
246 
247 void ip101DumpPhyReg(NetInterface *interface);
248 
249 //C++ guard
250 #ifdef __cplusplus
251  }
252 #endif
253 
254 #endif
void ip101DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
Definition: ip101_driver.c:246
void ip101EventHandler(NetInterface *interface)
IP101 event handler.
Definition: ip101_driver.c:140
void ip101Tick(NetInterface *interface)
IP101 timer handler.
Definition: ip101_driver.c:86
void ip101EnableIrq(NetInterface *interface)
Enable interrupts.
Definition: ip101_driver.c:120
void ip101WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
Definition: ip101_driver.c:204
error_t ip101Init(NetInterface *interface)
IP101 PHY transceiver initialization.
Definition: ip101_driver.c:58
PHY driver.
Definition: nic.h:196
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
void ip101DisableIrq(NetInterface *interface)
Disable interrupts.
Definition: ip101_driver.c:130
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
const PhyDriver ip101PhyDriver
IP101 Ethernet PHY driver.
Definition: ip101_driver.c:42
Network interface controller abstraction layer.
uint16_t ip101ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
Definition: ip101_driver.c:226