ksz8031_driver.h
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1 /**
2  * @file ksz8031_driver.h
3  * @brief KSZ8031 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _KSZ8031_DRIVER_H
30 #define _KSZ8031_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef KSZ8031_PHY_ADDR
37  #define KSZ8031_PHY_ADDR 0
38 #elif (KSZ8031_PHY_ADDR < 0 || KSZ8031_PHY_ADDR > 31)
39  #error KSZ8031_PHY_ADDR parameter is not valid
40 #endif
41 
42 //KSZ8031 registers
43 #define KSZ8031_PHY_REG_BMCR 0x00
44 #define KSZ8031_PHY_REG_BMSR 0x01
45 #define KSZ8031_PHY_REG_PHYIDR1 0x02
46 #define KSZ8031_PHY_REG_PHYIDR2 0x03
47 #define KSZ8031_PHY_REG_ANAR 0x04
48 #define KSZ8031_PHY_REG_ANLPAR 0x05
49 #define KSZ8031_PHY_REG_ANER 0x06
50 #define KSZ8031_PHY_REG_ANNPTR 0x07
51 #define KSZ8031_PHY_REG_LPNPAR 0x08
52 #define KSZ8031_PHY_REG_DRCON 0x10
53 #define KSZ8031_PHY_REG_AFECON1 0x11
54 #define KSZ8031_PHY_REG_RXERCTR 0x15
55 #define KSZ8031_PHY_REG_OMSO 0x16
56 #define KSZ8031_PHY_REG_OMSS 0x17
57 #define KSZ8031_PHY_REG_EXCON 0x18
58 #define KSZ8031_PHY_REG_ICSR 0x1B
59 #define KSZ8031_PHY_REG_LINKMDCS 0x1D
60 #define KSZ8031_PHY_REG_PHYCON1 0x1E
61 #define KSZ8031_PHY_REG_PHYCON2 0x1F
62 
63 //BMCR register
64 #define BMCR_RESET (1 << 15)
65 #define BMCR_LOOPBACK (1 << 14)
66 #define BMCR_SPEED_SEL (1 << 13)
67 #define BMCR_AN_EN (1 << 12)
68 #define BMCR_POWER_DOWN (1 << 11)
69 #define BMCR_ISOLATE (1 << 10)
70 #define BMCR_RESTART_AN (1 << 9)
71 #define BMCR_DUPLEX_MODE (1 << 8)
72 #define BMCR_COL_TEST (1 << 7)
73 
74 //BMSR register
75 #define BMSR_100BT4 (1 << 15)
76 #define BMSR_100BTX_FD (1 << 14)
77 #define BMSR_100BTX (1 << 13)
78 #define BMSR_10BT_FD (1 << 12)
79 #define BMSR_10BT (1 << 11)
80 #define BMSR_NO_PREAMBLE (1 << 6)
81 #define BMSR_AN_COMPLETE (1 << 5)
82 #define BMSR_REMOTE_FAULT (1 << 4)
83 #define BMSR_AN_ABLE (1 << 3)
84 #define BMSR_LINK_STATUS (1 << 2)
85 #define BMSR_JABBER_DETECT (1 << 1)
86 #define BMSR_EXTENDED_CAP (1 << 0)
87 
88 //ANAR register
89 #define ANAR_NEXT_PAGE (1 << 15)
90 #define ANAR_REMOTE_FAULT (1 << 13)
91 #define ANAR_PAUSE1 (1 << 11)
92 #define ANAR_PAUSE0 (1 << 10)
93 #define ANAR_100BT4 (1 << 9)
94 #define ANAR_100BTX_FD (1 << 8)
95 #define ANAR_100BTX (1 << 7)
96 #define ANAR_10BT_FD (1 << 6)
97 #define ANAR_10BT (1 << 5)
98 #define ANAR_SELECTOR4 (1 << 4)
99 #define ANAR_SELECTOR3 (1 << 3)
100 #define ANAR_SELECTOR2 (1 << 2)
101 #define ANAR_SELECTOR1 (1 << 1)
102 #define ANAR_SELECTOR0 (1 << 0)
103 
104 //ANLPAR register
105 #define ANLPAR_NEXT_PAGE (1 << 15)
106 #define ANLPAR_LP_ACK (1 << 14)
107 #define ANLPAR_REMOTE_FAULT (1 << 13)
108 #define ANLPAR_PAUSE1 (1 << 11)
109 #define ANLPAR_PAUSE0 (1 << 10)
110 #define ANLPAR_100BT4 (1 << 9)
111 #define ANLPAR_100BTX_FD (1 << 8)
112 #define ANLPAR_100BTX (1 << 7)
113 #define ANLPAR_10BT_FD (1 << 6)
114 #define ANLPAR_10BT (1 << 5)
115 #define ANLPAR_SELECTOR4 (1 << 4)
116 #define ANLPAR_SELECTOR3 (1 << 3)
117 #define ANLPAR_SELECTOR2 (1 << 2)
118 #define ANLPAR_SELECTOR1 (1 << 1)
119 #define ANLPAR_SELECTOR0 (1 << 0)
120 
121 //ANER register
122 #define ANER_PAR_DET_FAULT (1 << 4)
123 #define ANER_LP_NEXT_PAGE_ABLE (1 << 3)
124 #define ANER_NEXT_PAGE_ABLE (1 << 2)
125 #define ANER_PAGE_RECEIVED (1 << 1)
126 #define ANER_LP_AN_ABLE (1 << 0)
127 
128 //ANNPTR register
129 #define ANNPTR_NEXT_PAGE (1 << 15)
130 #define ANNPTR_MSG_PAGE (1 << 13)
131 #define ANNPTR_ACK2 (1 << 12)
132 #define ANNPTR_TOGGLE (1 << 11)
133 #define ANNPTR_MESSAGE10 (1 << 10)
134 #define ANNPTR_MESSAGE9 (1 << 9)
135 #define ANNPTR_MESSAGE8 (1 << 8)
136 #define ANNPTR_MESSAGE7 (1 << 7)
137 #define ANNPTR_MESSAGE6 (1 << 6)
138 #define ANNPTR_MESSAGE5 (1 << 5)
139 #define ANNPTR_MESSAGE4 (1 << 4)
140 #define ANNPTR_MESSAGE3 (1 << 3)
141 #define ANNPTR_MESSAGE2 (1 << 2)
142 #define ANNPTR_MESSAGE1 (1 << 1)
143 #define ANNPTR_MESSAGE0 (1 << 0)
144 
145 //LPNPAR register
146 #define LPNPAR_NEXT_PAGE (1 << 15)
147 #define LPNPAR_ACK (1 << 14)
148 #define LPNPAR_MSG_PAGE (1 << 13)
149 #define LPNPAR_ACK2 (1 << 12)
150 #define LPNPAR_TOGGLE (1 << 11)
151 #define LPNPAR_MESSAGE10 (1 << 10)
152 #define LPNPAR_MESSAGE9 (1 << 9)
153 #define LPNPAR_MESSAGE8 (1 << 8)
154 #define LPNPAR_MESSAGE7 (1 << 7)
155 #define LPNPAR_MESSAGE6 (1 << 6)
156 #define LPNPAR_MESSAGE5 (1 << 5)
157 #define LPNPAR_MESSAGE4 (1 << 4)
158 #define LPNPAR_MESSAGE3 (1 << 3)
159 #define LPNPAR_MESSAGE2 (1 << 2)
160 #define LPNPAR_MESSAGE1 (1 << 1)
161 #define LPNPAR_MESSAGE0 (1 << 0)
162 
163 //DRCON register
164 #define DRCON_PLL_OFF (1 << 4)
165 
166 //AFECON1 register
167 #define AFECON1_SLOW_OSC_MODE_EN (1 << 5)
168 
169 //OMSO register
170 #define OMSO_RMII_BTB_OVERRIDE (1 << 6)
171 #define OMSO_NAND_TREE_OVERRIDE (1 << 5)
172 #define OMSO_RMII_OVERRIDE (1 << 1)
173 
174 //OMSS register
175 #define OMSS_PHYAD2 (1 << 15)
176 #define OMSS_PHYAD1 (1 << 14)
177 #define OMSS_PHYAD0 (1 << 13)
178 #define OMSS_RMII_STATUS (1 << 1)
179 
180 //EXCON register
181 #define EXCON_EDPD_DIS (1 << 11)
182 
183 //ICSR register
184 #define ICSR_JABBER_IE (1 << 15)
185 #define ICSR_RECEIVE_ERROR_IE (1 << 14)
186 #define ICSR_PAGE_RECEIVED_IE (1 << 13)
187 #define ICSR_PAR_DET_FAULT_IE (1 << 12)
188 #define ICSR_LP_ACK_IE (1 << 11)
189 #define ICSR_LINK_DOWN_IE (1 << 10)
190 #define ICSR_REMOTE_FAULT_IE (1 << 9)
191 #define ICSR_LINK_UP_IE (1 << 8)
192 #define ICSR_JABBER_IF (1 << 7)
193 #define ICSR_RECEIVE_ERROR_IF (1 << 6)
194 #define ICSR_PAGE_RECEIVED_IF (1 << 5)
195 #define ICSR_PAR_DET_FAULT_IF (1 << 4)
196 #define ICSR_LP_ACK_IF (1 << 3)
197 #define ICSR_LINK_DOWN_IF (1 << 2)
198 #define ICSR_REMOTE_FAULT_IF (1 << 1)
199 #define ICSR_LINK_UP_IF (1 << 0)
200 
201 //LINKMDCS register
202 #define LINKMDCS_CABLE_DIAG_EN (1 << 15)
203 #define LINKMDCS_CABLE_DIAG_RES1 (1 << 14)
204 #define LINKMDCS_CABLE_DIAG_RES0 (1 << 13)
205 #define LINKMDCS_SHORT_CABLE (1 << 12)
206 #define LINKMDCS_CABLE_FAULT_CNT8 (1 << 8)
207 #define LINKMDCS_CABLE_FAULT_CNT7 (1 << 7)
208 #define LINKMDCS_CABLE_FAULT_CNT6 (1 << 6)
209 #define LINKMDCS_CABLE_FAULT_CNT5 (1 << 5)
210 #define LINKMDCS_CABLE_FAULT_CNT4 (1 << 4)
211 #define LINKMDCS_CABLE_FAULT_CNT3 (1 << 3)
212 #define LINKMDCS_CABLE_FAULT_CNT2 (1 << 2)
213 #define LINKMDCS_CABLE_FAULT_CNT1 (1 << 1)
214 #define LINKMDCS_CABLE_FAULT_CNT0 (1 << 0)
215 
216 //PHYCON1 register
217 #define PHYCON1_PAUSE_EN (1 << 9)
218 #define PHYCON1_LINK_STATUS (1 << 8)
219 #define PHYCON1_POL_STATUS (1 << 7)
220 #define PHYCON1_MDIX_STATE (1 << 5)
221 #define PHYCON1_ENERGY_DETECT (1 << 4)
222 #define PHYCON1_ISOLATE (1 << 3)
223 #define PHYCON1_OP_MODE2 (1 << 2)
224 #define PHYCON1_OP_MODE1 (1 << 1)
225 #define PHYCON1_OP_MODE0 (1 << 0)
226 
227 //Operation mode indication
228 #define PHYCON1_OP_MODE_MASK (7 << 0)
229 #define PHYCON1_OP_MODE_AN (0 << 0)
230 #define PHYCON1_OP_MODE_10BT (1 << 0)
231 #define PHYCON1_OP_MODE_100BTX (2 << 0)
232 #define PHYCON1_OP_MODE_10BT_FD (5 << 0)
233 #define PHYCON1_OP_MODE_100BTX_FD (6 << 0)
234 
235 //PHYCON2 register
236 #define PHYCON2_HP_MDIX (1 << 15)
237 #define PHYCON2_MDIX_SEL (1 << 14)
238 #define PHYCON2_PAIR_SWAP_DIS (1 << 13)
239 #define PHYCON2_FORCE_LINK (1 << 11)
240 #define PHYCON2_POWER_SAVING (1 << 10)
241 #define PHYCON2_INT_LEVEL (1 << 9)
242 #define PHYCON2_JABBER_EN (1 << 8)
243 #define PHYCON2_RMII_REF_CLK_SEL (1 << 7)
244 #define PHYCON2_LED_MODE1 (1 << 5)
245 #define PHYCON2_LED_MODE0 (1 << 4)
246 #define PHYCON2_TX_DIS (1 << 3)
247 #define PHYCON2_REMOTE_LOOPBACK (1 << 2)
248 #define PHYCON2_SCRAMBLER_DIS (1 << 0)
249 
250 //C++ guard
251 #ifdef __cplusplus
252  extern "C" {
253 #endif
254 
255 //KSZ8031 Ethernet PHY driver
256 extern const PhyDriver ksz8031PhyDriver;
257 
258 //KSZ8031 related functions
259 error_t ksz8031Init(NetInterface *interface);
260 
261 void ksz8031Tick(NetInterface *interface);
262 
263 void ksz8031EnableIrq(NetInterface *interface);
264 void ksz8031DisableIrq(NetInterface *interface);
265 
266 void ksz8031EventHandler(NetInterface *interface);
267 
268 void ksz8031WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
269 uint16_t ksz8031ReadPhyReg(NetInterface *interface, uint8_t address);
270 
271 void ksz8031DumpPhyReg(NetInterface *interface);
272 
273 //C++ guard
274 #ifdef __cplusplus
275  }
276 #endif
277 
278 #endif
void ksz8031EventHandler(NetInterface *interface)
KSZ8031 event handler.
void ksz8031WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
void ksz8031Tick(NetInterface *interface)
KSZ8031 timer handler.
uint16_t ksz8031ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
PHY driver.
Definition: nic.h:196
const PhyDriver ksz8031PhyDriver
KSZ8031 Ethernet PHY driver.
void ksz8031DisableIrq(NetInterface *interface)
Disable interrupts.
void ksz8031EnableIrq(NetInterface *interface)
Enable interrupts.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
error_t ksz8031Init(NetInterface *interface)
KSZ8031 PHY transceiver initialization.
void ksz8031DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
Network interface controller abstraction layer.