ksz8091_driver.h
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1 /**
2  * @file ksz8091_driver.h
3  * @brief KSZ8091 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _KSZ8091_DRIVER_H
30 #define _KSZ8091_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef KSZ8091_PHY_ADDR
37  #define KSZ8091_PHY_ADDR 7
38 #elif (KSZ8091_PHY_ADDR < 0 || KSZ8091_PHY_ADDR > 31)
39  #error KSZ8091_PHY_ADDR parameter is not valid
40 #endif
41 
42 //KSZ8091 registers
43 #define KSZ8091_PHY_REG_BMCR 0x00
44 #define KSZ8091_PHY_REG_BMSR 0x01
45 #define KSZ8091_PHY_REG_PHYIDR1 0x02
46 #define KSZ8091_PHY_REG_PHYIDR2 0x03
47 #define KSZ8091_PHY_REG_ANAR 0x04
48 #define KSZ8091_PHY_REG_ANLPAR 0x05
49 #define KSZ8091_PHY_REG_ANER 0x06
50 #define KSZ8091_PHY_REG_ANNPTR 0x07
51 #define KSZ8091_PHY_REG_LPNPAR 0x08
52 #define KSZ8091_PHY_REG_MMDCON 0x0D
53 #define KSZ8091_PHY_REG_MMDDATA 0x0E
54 #define KSZ8091_PHY_REG_DRC 0x10
55 #define KSZ8091_PHY_REG_AFECON1 0x11
56 #define KSZ8091_PHY_REG_AFECON4 0x13
57 #define KSZ8091_PHY_REG_RXERCTR 0x15
58 #define KSZ8091_PHY_REG_OMSO 0x16
59 #define KSZ8091_PHY_REG_OMSS 0x17
60 #define KSZ8091_PHY_REG_EXCON 0x18
61 #define KSZ8091_PHY_REG_ICSR 0x1B
62 #define KSZ8091_PHY_REG_LINKMDCS 0x1D
63 #define KSZ8091_PHY_REG_PHYCON1 0x1E
64 #define KSZ8091_PHY_REG_PHYCON2 0x1F
65 
66 //BMCR register
67 #define BMCR_RESET (1 << 15)
68 #define BMCR_LOOPBACK (1 << 14)
69 #define BMCR_SPEED_SEL (1 << 13)
70 #define BMCR_AN_EN (1 << 12)
71 #define BMCR_POWER_DOWN (1 << 11)
72 #define BMCR_ISOLATE (1 << 10)
73 #define BMCR_RESTART_AN (1 << 9)
74 #define BMCR_DUPLEX_MODE (1 << 8)
75 #define BMCR_COL_TEST (1 << 7)
76 
77 //BMSR register
78 #define BMSR_100BT4 (1 << 15)
79 #define BMSR_100BTX_FD (1 << 14)
80 #define BMSR_100BTX (1 << 13)
81 #define BMSR_10BT_FD (1 << 12)
82 #define BMSR_10BT (1 << 11)
83 #define BMSR_NO_PREAMBLE (1 << 6)
84 #define BMSR_AN_COMPLETE (1 << 5)
85 #define BMSR_REMOTE_FAULT (1 << 4)
86 #define BMSR_AN_ABLE (1 << 3)
87 #define BMSR_LINK_STATUS (1 << 2)
88 #define BMSR_JABBER_DETECT (1 << 1)
89 #define BMSR_EXTENDED_CAP (1 << 0)
90 
91 //ANAR register
92 #define ANAR_NEXT_PAGE (1 << 15)
93 #define ANAR_REMOTE_FAULT (1 << 13)
94 #define ANAR_PAUSE1 (1 << 11)
95 #define ANAR_PAUSE0 (1 << 10)
96 #define ANAR_100BT4 (1 << 9)
97 #define ANAR_100BTX_FD (1 << 8)
98 #define ANAR_100BTX (1 << 7)
99 #define ANAR_10BT_FD (1 << 6)
100 #define ANAR_10BT (1 << 5)
101 #define ANAR_SELECTOR4 (1 << 4)
102 #define ANAR_SELECTOR3 (1 << 3)
103 #define ANAR_SELECTOR2 (1 << 2)
104 #define ANAR_SELECTOR1 (1 << 1)
105 #define ANAR_SELECTOR0 (1 << 0)
106 
107 //ANLPAR register
108 #define ANLPAR_NEXT_PAGE (1 << 15)
109 #define ANLPAR_LP_ACK (1 << 14)
110 #define ANLPAR_REMOTE_FAULT (1 << 13)
111 #define ANLPAR_PAUSE1 (1 << 11)
112 #define ANLPAR_PAUSE0 (1 << 10)
113 #define ANLPAR_100BT4 (1 << 9)
114 #define ANLPAR_100BTX_FD (1 << 8)
115 #define ANLPAR_100BTX (1 << 7)
116 #define ANLPAR_10BT_FD (1 << 6)
117 #define ANLPAR_10BT (1 << 5)
118 #define ANLPAR_SELECTOR4 (1 << 4)
119 #define ANLPAR_SELECTOR3 (1 << 3)
120 #define ANLPAR_SELECTOR2 (1 << 2)
121 #define ANLPAR_SELECTOR1 (1 << 1)
122 #define ANLPAR_SELECTOR0 (1 << 0)
123 
124 //ANER register
125 #define ANER_PAR_DET_FAULT (1 << 4)
126 #define ANER_LP_NEXT_PAGE_ABLE (1 << 3)
127 #define ANER_NEXT_PAGE_ABLE (1 << 2)
128 #define ANER_PAGE_RECEIVED (1 << 1)
129 #define ANER_LP_AN_ABLE (1 << 0)
130 
131 //ANNPTR register
132 #define ANNPTR_NEXT_PAGE (1 << 15)
133 #define ANNPTR_MSG_PAGE (1 << 13)
134 #define ANNPTR_ACK2 (1 << 12)
135 #define ANNPTR_TOGGLE (1 << 11)
136 #define ANNPTR_MESSAGE10 (1 << 10)
137 #define ANNPTR_MESSAGE9 (1 << 9)
138 #define ANNPTR_MESSAGE8 (1 << 8)
139 #define ANNPTR_MESSAGE7 (1 << 7)
140 #define ANNPTR_MESSAGE6 (1 << 6)
141 #define ANNPTR_MESSAGE5 (1 << 5)
142 #define ANNPTR_MESSAGE4 (1 << 4)
143 #define ANNPTR_MESSAGE3 (1 << 3)
144 #define ANNPTR_MESSAGE2 (1 << 2)
145 #define ANNPTR_MESSAGE1 (1 << 1)
146 #define ANNPTR_MESSAGE0 (1 << 0)
147 
148 //LPNPAR register
149 #define LPNPAR_NEXT_PAGE (1 << 15)
150 #define LPNPAR_ACK (1 << 14)
151 #define LPNPAR_MSG_PAGE (1 << 13)
152 #define LPNPAR_ACK2 (1 << 12)
153 #define LPNPAR_TOGGLE (1 << 11)
154 #define LPNPAR_MESSAGE10 (1 << 10)
155 #define LPNPAR_MESSAGE9 (1 << 9)
156 #define LPNPAR_MESSAGE8 (1 << 8)
157 #define LPNPAR_MESSAGE7 (1 << 7)
158 #define LPNPAR_MESSAGE6 (1 << 6)
159 #define LPNPAR_MESSAGE5 (1 << 5)
160 #define LPNPAR_MESSAGE4 (1 << 4)
161 #define LPNPAR_MESSAGE3 (1 << 3)
162 #define LPNPAR_MESSAGE2 (1 << 2)
163 #define LPNPAR_MESSAGE1 (1 << 1)
164 #define LPNPAR_MESSAGE0 (1 << 0)
165 
166 //MMDCON register
167 #define MMDCON_OP_MODE1 (1 << 15)
168 #define MMDCON_OP_MODE0 (1 << 14)
169 #define MMDCON_DEVICE_ADDR4 (1 << 4)
170 #define MMDCON_DEVICE_ADDR3 (1 << 3)
171 #define MMDCON_DEVICE_ADDR2 (1 << 2)
172 #define MMDCON_DEVICE_ADDR1 (1 << 1)
173 #define MMDCON_DEVICE_ADDR0 (1 << 0)
174 
175 //DRC register
176 #define DRC_PLL_OFF (1 << 4)
177 
178 //AFECON1 register
179 #define AFECON1_SLOW_OSC_MODE_EN (1 << 5)
180 
181 //AFECON4 register
182 #define AFECON4_10BT_MODE (1 << 4)
183 
184 //OMSO register
185 #define OMSO_PME_ENABLE (1 << 15)
186 #define OMSO_BCAST_OFF_OVERRIDE (1 << 9)
187 #define OMSO_RMII_BTB_OVERRIDE (1 << 6)
188 #define OMSO_NAND_TREE_OVERRIDE (1 << 5)
189 #define OMSO_RMII_OVERRIDE (1 << 1)
190 
191 //OMSS register
192 #define OMSS_PHYAD2 (1 << 15)
193 #define OMSS_PHYAD1 (1 << 14)
194 #define OMSS_PHYAD0 (1 << 13)
195 #define OMSS_RMII_STATUS (1 << 1)
196 
197 //EXCON register
198 #define EXCON_EDPD_DIS (1 << 11)
199 
200 //ICSR register
201 #define ICSR_JABBER_IE (1 << 15)
202 #define ICSR_RECEIVE_ERROR_IE (1 << 14)
203 #define ICSR_PAGE_RECEIVED_IE (1 << 13)
204 #define ICSR_PAR_DET_FAULT_IE (1 << 12)
205 #define ICSR_LP_ACK_IE (1 << 11)
206 #define ICSR_LINK_DOWN_IE (1 << 10)
207 #define ICSR_REMOTE_FAULT_IE (1 << 9)
208 #define ICSR_LINK_UP_IE (1 << 8)
209 #define ICSR_JABBER_IF (1 << 7)
210 #define ICSR_RECEIVE_ERROR_IF (1 << 6)
211 #define ICSR_PAGE_RECEIVED_IF (1 << 5)
212 #define ICSR_PAR_DET_FAULT_IF (1 << 4)
213 #define ICSR_LP_ACK_IF (1 << 3)
214 #define ICSR_LINK_DOWN_IF (1 << 2)
215 #define ICSR_REMOTE_FAULT_IF (1 << 1)
216 #define ICSR_LINK_UP_IF (1 << 0)
217 
218 //LINKMDCS register
219 #define LINKMDCS_CABLE_DIAG_EN (1 << 15)
220 #define LINKMDCS_CABLE_DIAG_RES1 (1 << 14)
221 #define LINKMDCS_CABLE_DIAG_RES0 (1 << 13)
222 #define LINKMDCS_SHORT_CABLE (1 << 12)
223 #define LINKMDCS_CABLE_FAULT_CNT8 (1 << 8)
224 #define LINKMDCS_CABLE_FAULT_CNT7 (1 << 7)
225 #define LINKMDCS_CABLE_FAULT_CNT6 (1 << 6)
226 #define LINKMDCS_CABLE_FAULT_CNT5 (1 << 5)
227 #define LINKMDCS_CABLE_FAULT_CNT4 (1 << 4)
228 #define LINKMDCS_CABLE_FAULT_CNT3 (1 << 3)
229 #define LINKMDCS_CABLE_FAULT_CNT2 (1 << 2)
230 #define LINKMDCS_CABLE_FAULT_CNT1 (1 << 1)
231 #define LINKMDCS_CABLE_FAULT_CNT0 (1 << 0)
232 
233 //PHYCON1 register
234 #define PHYCON1_PAUSE_EN (1 << 9)
235 #define PHYCON1_LINK_STATUS (1 << 8)
236 #define PHYCON1_POL_STATUS (1 << 7)
237 #define PHYCON1_MDIX_STATE (1 << 5)
238 #define PHYCON1_ENERGY_DETECT (1 << 4)
239 #define PHYCON1_ISOLATE (1 << 3)
240 #define PHYCON1_OP_MODE2 (1 << 2)
241 #define PHYCON1_OP_MODE1 (1 << 1)
242 #define PHYCON1_OP_MODE0 (1 << 0)
243 
244 //Operation mode indication
245 #define PHYCON1_OP_MODE_MASK (7 << 0)
246 #define PHYCON1_OP_MODE_AN (0 << 0)
247 #define PHYCON1_OP_MODE_10BT (1 << 0)
248 #define PHYCON1_OP_MODE_100BTX (2 << 0)
249 #define PHYCON1_OP_MODE_10BT_FD (5 << 0)
250 #define PHYCON1_OP_MODE_100BTX_FD (6 << 0)
251 
252 //PHYCON2 register
253 #define PHYCON2_HP_MDIX (1 << 15)
254 #define PHYCON2_MDIX_SEL (1 << 14)
255 #define PHYCON2_PAIR_SWAP_DIS (1 << 13)
256 #define PHYCON2_FORCE_LINK (1 << 11)
257 #define PHYCON2_POWER_SAVING (1 << 10)
258 #define PHYCON2_INT_LEVEL (1 << 9)
259 #define PHYCON2_JABBER_EN (1 << 8)
260 #define PHYCON2_RMII_REF_CLK_SEL (1 << 7)
261 #define PHYCON2_LED_MODE1 (1 << 5)
262 #define PHYCON2_LED_MODE0 (1 << 4)
263 #define PHYCON2_TX_DIS (1 << 3)
264 #define PHYCON2_REMOTE_LOOPBACK (1 << 2)
265 #define PHYCON2_SCRAMBLER_DIS (1 << 0)
266 
267 //C++ guard
268 #ifdef __cplusplus
269  extern "C" {
270 #endif
271 
272 //KSZ8091 Ethernet PHY driver
273 extern const PhyDriver ksz8091PhyDriver;
274 
275 //KSZ8091 related functions
276 error_t ksz8091Init(NetInterface *interface);
277 
278 void ksz8091Tick(NetInterface *interface);
279 
280 void ksz8091EnableIrq(NetInterface *interface);
281 void ksz8091DisableIrq(NetInterface *interface);
282 
283 void ksz8091EventHandler(NetInterface *interface);
284 
285 void ksz8091WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
286 uint16_t ksz8091ReadPhyReg(NetInterface *interface, uint8_t address);
287 
288 void ksz8091DumpPhyReg(NetInterface *interface);
289 
290 //C++ guard
291 #ifdef __cplusplus
292  }
293 #endif
294 
295 #endif
const PhyDriver ksz8091PhyDriver
KSZ8091 Ethernet PHY driver.
void ksz8091EventHandler(NetInterface *interface)
KSZ8091 event handler.
void ksz8091WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
void ksz8091DisableIrq(NetInterface *interface)
Disable interrupts.
PHY driver.
Definition: nic.h:196
void ksz8091Tick(NetInterface *interface)
KSZ8091 timer handler.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
void ksz8091EnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint16_t ksz8091ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
error_t ksz8091Init(NetInterface *interface)
KSZ8091 PHY transceiver initialization.
Network interface controller abstraction layer.
void ksz8091DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.