ksz9893_driver.h
Go to the documentation of this file.
1 /**
2  * @file ksz9893_driver.h
3  * @brief KSZ9893 Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.2
29  **/
30 
31 #ifndef _KSZ9893_DRIVER_H
32 #define _KSZ9893_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //KSZ9893 ports
38 #define KSZ9893_PORT1 1
39 #define KSZ9893_PORT2 2
40 
41 //SPI command byte
42 #define KSZ9893_SPI_CMD_WRITE 0x40000000
43 #define KSZ9893_SPI_CMD_READ 0x60000000
44 #define KSZ9893_SPI_CMD_ADDR 0x001FFFE0
45 
46 //KSZ9893 PHY registers
47 #define KSZ9893_PHY_REG_BMCR 0x00
48 #define KSZ9893_PHY_REG_BMSR 0x01
49 #define KSZ9893_PHY_REG_PHYIDR1 0x02
50 #define KSZ9893_PHY_REG_PHYIDR2 0x03
51 #define KSZ9893_PHY_REG_ANAR 0x04
52 #define KSZ9893_PHY_REG_ANLPAR 0x05
53 #define KSZ9893_PHY_REG_ANER 0x06
54 #define KSZ9893_PHY_REG_ANNPTR 0x07
55 #define KSZ9893_PHY_REG_LPNPAR 0x08
56 #define KSZ9893_PHY_REG_1000BT_CTRL 0x09
57 #define KSZ9893_PHY_REG_1000BT_STATUS 0x0A
58 #define KSZ9893_PHY_REG_MMD_CTRL 0x0D
59 #define KSZ9893_PHY_REG_MMD_DATA 0x0E
60 #define KSZ9893_PHY_REG_EXT_STATUS 0x0F
61 #define KSZ9893_PHY_REG_RLB 0x11
62 #define KSZ9893_PHY_REG_LINKMDCD 0x12
63 #define KSZ9893_PHY_REG_DPMAPCSS 0x13
64 #define KSZ9893_PHY_REG_RXERCTR 0x15
65 #define KSZ9893_PHY_REG_ICSR 0x1B
66 #define KSZ9893_PHY_REG_AUTOMDI 0x1C
67 #define KSZ9893_PHY_REG_PHYCON 0x1F
68 
69 //BMCR register
70 #define BMCR_SOFT_RESET (1 << 15)
71 #define BMCR_LOOPBACK (1 << 14)
72 #define BMCR_SPEED_SEL_LSB (1 << 13)
73 #define BMCR_AN_EN (1 << 12)
74 #define BMCR_POWER_DOWN (1 << 11)
75 #define BMCR_ISOLATE (1 << 10)
76 #define BMCR_RESTART_AN (1 << 9)
77 #define BMCR_DUPLEX_MODE (1 << 8)
78 #define BMCR_COL_TEST (1 << 7)
79 #define BMCR_SPEED_SEL_MSB (1 << 6)
80 
81 //BMSR register
82 #define BMSR_100BT4 (1 << 15)
83 #define BMSR_100BTX_FD (1 << 14)
84 #define BMSR_100BTX_HD (1 << 13)
85 #define BMSR_10BT_FD (1 << 12)
86 #define BMSR_10BT_HD (1 << 11)
87 #define BMSR_EXTENDED_STATUS (1 << 8)
88 #define BMSR_MF_PREAMBLE_SUPPR (1 << 6)
89 #define BMSR_AN_COMPLETE (1 << 5)
90 #define BMSR_REMOTE_FAULT (1 << 4)
91 #define BMSR_AN_ABLE (1 << 3)
92 #define BMSR_LINK_STATUS (1 << 2)
93 #define BMSR_JABBER_DETECT (1 << 1)
94 #define BMSR_EXTENDED_CAP (1 << 0)
95 
96 //ANAR register
97 #define ANAR_NEXT_PAGE (1 << 15)
98 #define ANAR_REMOTE_FAULT (1 << 13)
99 #define ANAR_PAUSE1 (1 << 11)
100 #define ANAR_PAUSE0 (1 << 10)
101 #define ANAR_100BT4 (1 << 9)
102 #define ANAR_100BTX_FD (1 << 8)
103 #define ANAR_100BTX_HD (1 << 7)
104 #define ANAR_10BT_FD (1 << 6)
105 #define ANAR_10BT_HD (1 << 5)
106 #define ANAR_SELECTOR4 (1 << 4)
107 #define ANAR_SELECTOR3 (1 << 3)
108 #define ANAR_SELECTOR2 (1 << 2)
109 #define ANAR_SELECTOR1 (1 << 1)
110 #define ANAR_SELECTOR0 (1 << 0)
111 
112 //ANLPAR register
113 #define ANLPAR_NEXT_PAGE (1 << 15)
114 #define ANLPAR_LP_ACK (1 << 14)
115 #define ANLPAR_REMOTE_FAULT (1 << 13)
116 #define ANLPAR_PAUSE1 (1 << 11)
117 #define ANLPAR_PAUSE0 (1 << 10)
118 #define ANLPAR_100BT4 (1 << 9)
119 #define ANLPAR_100BTX_FD (1 << 8)
120 #define ANLPAR_100BTX_HD (1 << 7)
121 #define ANLPAR_10BT_FD (1 << 6)
122 #define ANLPAR_10BT_HD (1 << 5)
123 #define ANLPAR_SELECTOR4 (1 << 4)
124 #define ANLPAR_SELECTOR3 (1 << 3)
125 #define ANLPAR_SELECTOR2 (1 << 2)
126 #define ANLPAR_SELECTOR1 (1 << 1)
127 #define ANLPAR_SELECTOR0 (1 << 0)
128 
129 //ANER register
130 #define ANER_PAR_DET_FAULT (1 << 4)
131 #define ANER_LP_NEXT_PAGE_ABLE (1 << 3)
132 #define ANER_NEXT_PAGE_ABLE (1 << 2)
133 #define ANER_PAGE_RECEIVED (1 << 1)
134 #define ANER_LP_AN_ABLE (1 << 0)
135 
136 //ANNPTR register
137 #define ANNPTR_NEXT_PAGE (1 << 15)
138 #define ANNPTR_MSG_PAGE (1 << 13)
139 #define ANNPTR_ACK2 (1 << 12)
140 #define ANNPTR_TOGGLE (1 << 11)
141 #define ANNPTR_MESSAGE10 (1 << 10)
142 #define ANNPTR_MESSAGE9 (1 << 9)
143 #define ANNPTR_MESSAGE8 (1 << 8)
144 #define ANNPTR_MESSAGE7 (1 << 7)
145 #define ANNPTR_MESSAGE6 (1 << 6)
146 #define ANNPTR_MESSAGE5 (1 << 5)
147 #define ANNPTR_MESSAGE4 (1 << 4)
148 #define ANNPTR_MESSAGE3 (1 << 3)
149 #define ANNPTR_MESSAGE2 (1 << 2)
150 #define ANNPTR_MESSAGE1 (1 << 1)
151 #define ANNPTR_MESSAGE0 (1 << 0)
152 
153 //LPNPAR register
154 #define LPNPAR_NEXT_PAGE (1 << 15)
155 #define LPNPAR_ACK (1 << 14)
156 #define LPNPAR_MSG_PAGE (1 << 13)
157 #define LPNPAR_ACK2 (1 << 12)
158 #define LPNPAR_TOGGLE (1 << 11)
159 #define LPNPAR_MESSAGE10 (1 << 10)
160 #define LPNPAR_MESSAGE9 (1 << 9)
161 #define LPNPAR_MESSAGE8 (1 << 8)
162 #define LPNPAR_MESSAGE7 (1 << 7)
163 #define LPNPAR_MESSAGE6 (1 << 6)
164 #define LPNPAR_MESSAGE5 (1 << 5)
165 #define LPNPAR_MESSAGE4 (1 << 4)
166 #define LPNPAR_MESSAGE3 (1 << 3)
167 #define LPNPAR_MESSAGE2 (1 << 2)
168 #define LPNPAR_MESSAGE1 (1 << 1)
169 #define LPNPAR_MESSAGE0 (1 << 0)
170 
171 //1000BT_CTRL register
172 #define _1000BT_CTRL_TEST_MODE2 (1 << 15)
173 #define _1000BT_CTRL_TEST_MODE1 (1 << 14)
174 #define _1000BT_CTRL_TEST_MODE0 (1 << 13)
175 #define _1000BT_CTRL_MS_MAN_CONF_EN (1 << 12)
176 #define _1000BT_CTRL_MS_MAN_CONF_VAL (1 << 11)
177 #define _1000BT_CTRL_PORT_TYPE (1 << 10)
178 #define _1000BT_CTRL_1000BT_FD (1 << 9)
179 #define _1000BT_CTRL_1000BT_HD (1 << 8)
180 
181 //1000BT_STATUS register
182 #define _1000BT_STATUS_MS_CONF_FAULT (1 << 15)
183 #define _1000BT_STATUS_MS_CONF_RES (1 << 14)
184 #define _1000BT_STATUS_LOC_REC_STATUS (1 << 13)
185 #define _1000BT_STATUS_REM_REC_STATUS (1 << 12)
186 #define _1000BT_STATUS_LP_1000BT_FD (1 << 11)
187 #define _1000BT_STATUS_LP_1000BT_HD (1 << 10)
188 #define _1000BT_STATUS_IDLE_ERR_CTR7 (1 << 7)
189 #define _1000BT_STATUS_IDLE_ERR_CTR6 (1 << 6)
190 #define _1000BT_STATUS_IDLE_ERR_CTR5 (1 << 5)
191 #define _1000BT_STATUS_IDLE_ERR_CTR4 (1 << 4)
192 #define _1000BT_STATUS_IDLE_ERR_CTR3 (1 << 3)
193 #define _1000BT_STATUS_IDLE_ERR_CTR2 (1 << 2)
194 #define _1000BT_STATUS_IDLE_ERR_CTR1 (1 << 1)
195 #define _1000BT_STATUS_IDLE_ERR_CTR0 (1 << 0)
196 
197 //MMD_CTRL register
198 #define MMD_CTRL_DEVICE_OP_MODE1 (1 << 15)
199 #define MMD_CTRL_DEVICE_OP_MODE0 (1 << 14)
200 #define MMD_CTRL_DEVICE_ADDR4 (1 << 4)
201 #define MMD_CTRL_DEVICE_ADDR3 (1 << 3)
202 #define MMD_CTRL_DEVICE_ADDR2 (1 << 2)
203 #define MMD_CTRL_DEVICE_ADDR1 (1 << 1)
204 #define MMD_CTRL_DEVICE_ADDR0 (1 << 0)
205 
206 //EXT_STATUS register
207 #define EXT_STATUS_1000BX_FD (1 << 15)
208 #define EXT_STATUS_1000BX_HD (1 << 14)
209 #define EXT_STATUS_1000BT_FD (1 << 13)
210 #define EXT_STATUS_1000BT_HD (1 << 12)
211 
212 //RLB register
213 #define RLB_REMOTE_LOOPBACK (1 << 8)
214 
215 //LINKMDCD register
216 #define LINKMDCD_CDT_EN (1 << 15)
217 #define LINKMDCD_CDT_PAIR1 (1 << 13)
218 #define LINKMDCD_CDT_PAIR0 (1 << 12)
219 #define LINKMDCD_CDT_STATUS1 (1 << 9)
220 #define LINKMDCD_CDT_STATUS0 (1 << 8)
221 
222 //DPMAPCSS register
223 #define DPMAPCSS_1000BT_LINK_STATUS (1 << 2)
224 #define DPMAPCSS_100BTX_LINK_STATUS (1 << 1)
225 
226 //ICSR register
227 #define ICSR_JABBER_IE (1 << 15)
228 #define ICSR_RECEIVE_ERROR_IE (1 << 14)
229 #define ICSR_PAGE_RECEIVED_IE (1 << 13)
230 #define ICSR_PAR_DET_FAULT_IE (1 << 12)
231 #define ICSR_LP_ACK_IE (1 << 11)
232 #define ICSR_LINK_DOWN_IE (1 << 10)
233 #define ICSR_REMOTE_FAULT_IE (1 << 9)
234 #define ICSR_LINK_UP_IE (1 << 8)
235 #define ICSR_JABBER_IF (1 << 7)
236 #define ICSR_RECEIVE_ERROR_IF (1 << 6)
237 #define ICSR_PAGE_RECEIVED_IF (1 << 5)
238 #define ICSR_PAR_DET_FAULT_IF (1 << 4)
239 #define ICSR_LP_ACK_IF (1 << 3)
240 #define ICSR_LINK_DOWN_IF (1 << 2)
241 #define ICSR_REMOTE_FAULT_IF (1 << 1)
242 #define ICSR_LINK_UP_IF (1 << 0)
243 
244 //AUTOMDI register
245 #define AUTOMDI_MDI_SEL (1 << 7)
246 #define AUTOMDI_SWAP_OFF (1 << 6)
247 
248 //PHYCON register
249 #define PHYCON_JABBER_EN (1 << 9)
250 #define PHYCON_SPEED_1000BT (1 << 6)
251 #define PHYCON_SPEED_100BTX (1 << 5)
252 #define PHYCON_SPEED_10BT (1 << 4)
253 #define PHYCON_DUPLEX_STATUS (1 << 3)
254 #define PHYCON_1000BT_MS_STATUS (1 << 2)
255 
256 //KSZ9893 switch registers
257 #define KSZ9893_SW_REG_CHIP_ID0 0x0000
258 #define KSZ9893_SW_REG_CHIP_ID1 0x0001
259 #define KSZ9893_SW_REG_CHIP_ID2 0x0002
260 #define KSZ9893_SW_REG_CHIP_ID3 0x0003
261 #define KSZ9893_SW_REG_SWITCH_OP 0x0300
262 #define KSZ9893_SW_REG_PORT_OP_CTRL0(n) (0x0020 + ((n) * 0x1000))
263 #define KSZ9893_SW_REG_XMII_PORT_CTRL0(n) (0x0300 + ((n) * 0x1000))
264 #define KSZ9893_SW_REG_XMII_PORT_CTRL1(n) (0x0301 + ((n) * 0x1000))
265 #define KSZ9893_SW_REG_PORT_MSTP_STATE(n) (0x0B04 + ((n) * 0x1000))
266 
267 //Chip ID1 register
268 #define CHIP_ID1_CHIP_ID_MSB 0xFF
269 #define CHIP_ID1_CHIP_ID_MSB_DEFAULT 0x98
270 
271 //Chip ID2 register
272 #define CHIP_ID2_CHIP_ID_LSB 0xFF
273 #define CHIP_ID2_CHIP_ID_LSB_DEFAULT 0x93
274 
275 //Switch operation register
276 #define SWITCH_OP_DOUBLE_TAG_EN (1 << 7)
277 #define SWITCH_OP_SOFT_RESET (1 << 1)
278 #define SWITCH_OP_START_SWITCH (1 << 0)
279 
280 //Port operation control 0 register
281 #define PORT_OP_CTRL0_LOCAL_LOOPBACK (1 << 7)
282 #define PORT_OP_CTRL0_REMOTE_LOOPBACK (1 << 6)
283 #define PORT_OP_CTRL0_TAIL_TAG_EN (1 << 2)
284 #define PORT_OP_CTRL0_TX_QUEUE_SPLIT_EN1 (1 << 1)
285 #define PORT_OP_CTRL0_TX_QUEUE_SPLIT_EN0 (1 << 0)
286 
287 //XMII port control 0 register
288 #define XMII_PORT_CTRL0_PORT_DUPLEX (1 << 6)
289 #define XMII_PORT_CTRL0_PORT_TX_FLOW_CTRL_EN (1 << 5)
290 #define XMII_PORT_CTRL0_PORT_SPEED_10_100 (1 << 4)
291 #define XMII_PORT_CTRL0_PORT_RX_FLOW_CTRL_EN (1 << 3)
292 
293 //XMII port control 1 register
294 #define XMII_PORT_CTRL1_PORT_SPEED_1000 (1 << 6)
295 #define XMII_PORT_CTRL1_RGMII_ID_IG (1 << 4)
296 #define XMII_PORT_CTRL1_RGMII_ID_EG (1 << 3)
297 #define XMII_PORT_CTRL1_MII_RMII_MODE (1 << 2)
298 #define XMII_PORT_CTRL1_PORT_IF_TYPE1 (1 << 1)
299 #define XMII_PORT_CTRL1_PORT_IF_TYPE0 (1 << 0)
300 
301 //Port MSTP state register
302 #define PORT_MSTP_STATE_TRANSMIT_EN (1 << 2)
303 #define PORT_MSTP_STATE_RECEIVE_EN (1 << 1)
304 #define PORT_MSTP_STATE_LEARNING_DIS (1 << 0)
305 
306 //KSZ9893 PHY registers
307 #define KSZ9893_SW_REG_PORT_ETH_PHY(n, a) (0x0100 + ((n) * 0x1000) + ((a) * 2))
308 
309 //Tail tag encoding
310 #define KSZ9893_TAIL_TAG_ENCODE(port) (0x20 | ((port) & 0x03))
311 //Tail tag decoding
312 #define KSZ9893_TAIL_TAG_DECODE(tag) (((tag) & 0x01) + 1)
313 
314 //C++ guard
315 #ifdef __cplusplus
316  extern "C" {
317 #endif
318 
319 //KSZ9893 Ethernet switch driver
320 extern const PhyDriver ksz9893PhyDriver;
321 
322 //KSZ9893 related functions
323 error_t ksz9893Init(NetInterface *interface);
324 
325 bool_t ksz9893GetLinkState(NetInterface *interface, uint8_t port);
326 
327 void ksz9893Tick(NetInterface *interface);
328 
329 void ksz9893EnableIrq(NetInterface *interface);
330 void ksz9893DisableIrq(NetInterface *interface);
331 
332 void ksz9893EventHandler(NetInterface *interface);
333 
334 error_t ksz9893TagFrame(NetInterface *interface, NetBuffer *buffer,
335  size_t *offset, uint8_t port, uint16_t *type);
336 
337 error_t ksz9893UntagFrame(NetInterface *interface, uint8_t **frame,
338  size_t *length, uint8_t *port);
339 
340 void ksz9893WritePhyReg(NetInterface *interface, uint8_t port,
341  uint8_t address, uint16_t data);
342 
343 uint16_t ksz9893ReadPhyReg(NetInterface *interface, uint8_t port,
344  uint8_t address);
345 
346 void ksz9893DumpPhyReg(NetInterface *interface, uint8_t port);
347 
348 void ksz9893WriteSwitchReg(NetInterface *interface, uint16_t address,
349  uint8_t data);
350 
351 uint8_t ksz9893ReadSwitchReg(NetInterface *interface, uint16_t address);
352 
353 void ksz9893DumpSwitchReg(NetInterface *interface);
354 
355 //C++ guard
356 #ifdef __cplusplus
357  }
358 #endif
359 
360 #endif
void ksz9893DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
void ksz9893Tick(NetInterface *interface)
KSZ9893 timer handler.
void ksz9893DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
void ksz9893WriteSwitchReg(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register.
const PhyDriver ksz9893PhyDriver
KSZ9893 Ethernet switch driver.
void ksz9893DisableIrq(NetInterface *interface)
Disable interrupts.
char_t type
bool_t ksz9893GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
uint8_t ksz9893ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
PHY driver.
Definition: nic.h:199
error_t ksz9893Init(NetInterface *interface)
KSZ9893 Ethernet switch initialization.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t ksz9893UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
void ksz9893WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
void ksz9893EventHandler(NetInterface *interface)
KSZ9893 event handler.
uint16_t ksz9893ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:42
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint16_t port
Definition: dns_common.h:223
void ksz9893EnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t length
Definition: dtls_misc.h:142
int bool_t
Definition: compiler_port.h:49
Network interface controller abstraction layer.
error_t ksz9893TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.