lan8720_driver.h
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1 /**
2  * @file lan8720_driver.h
3  * @brief LAN8720 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _LAN8720_DRIVER_H
30 #define _LAN8720_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef LAN8720_PHY_ADDR
37  #define LAN8720_PHY_ADDR 0
38 #elif (LAN8720_PHY_ADDR < 0 || LAN8720_PHY_ADDR > 31)
39  #error LAN8720_PHY_ADDR parameter is not valid
40 #endif
41 
42 //LAN8720 registers
43 #define LAN8720_PHY_REG_BMCR 0x00
44 #define LAN8720_PHY_REG_BMSR 0x01
45 #define LAN8720_PHY_REG_PHYIDR1 0x02
46 #define LAN8720_PHY_REG_PHYIDR2 0x03
47 #define LAN8720_PHY_REG_ANAR 0x04
48 #define LAN8720_PHY_REG_ANLPAR 0x05
49 #define LAN8720_PHY_REG_ANER 0x06
50 #define LAN8720_PHY_REG_SRR 0x10
51 #define LAN8720_PHY_REG_MCSR 0x11
52 #define LAN8720_PHY_REG_SMR 0x12
53 #define LAN8720_PHY_REG_SECR 0x1A
54 #define LAN8720_PHY_REG_SCSIR 0x1B
55 #define LAN8720_PHY_REG_SITCR 0x1C
56 #define LAN8720_PHY_REG_ISR 0x1D
57 #define LAN8720_PHY_REG_IMR 0x1E
58 #define LAN8720_PHY_REG_PSCSR 0x1F
59 
60 //BMCR register
61 #define BMCR_RESET (1 << 15)
62 #define BMCR_LOOPBACK (1 << 14)
63 #define BMCR_SPEED_SEL (1 << 13)
64 #define BMCR_AN_EN (1 << 12)
65 #define BMCR_POWER_DOWN (1 << 11)
66 #define BMCR_ISOLATE (1 << 10)
67 #define BMCR_RESTART_AN (1 << 9)
68 #define BMCR_DUPLEX_MODE (1 << 8)
69 #define BMCR_COL_TEST (1 << 7)
70 
71 //BMSR register
72 #define BMSR_100BT4 (1 << 15)
73 #define BMSR_100BTX_FD (1 << 14)
74 #define BMSR_100BTX (1 << 13)
75 #define BMSR_10BT_FD (1 << 12)
76 #define BMSR_10BT (1 << 11)
77 #define BMSR_AN_COMPLETE (1 << 5)
78 #define BMSR_REMOTE_FAULT (1 << 4)
79 #define BMSR_AN_ABLE (1 << 3)
80 #define BMSR_LINK_STATUS (1 << 2)
81 #define BMSR_JABBER_DETECT (1 << 1)
82 #define BMSR_EXTENDED_CAP (1 << 0)
83 
84 //ANAR register
85 #define ANAR_NP (1 << 15)
86 #define ANAR_RF (1 << 13)
87 #define ANAR_PAUSE1 (1 << 11)
88 #define ANAR_PAUSE0 (1 << 10)
89 #define ANAR_100BT4 (1 << 9)
90 #define ANAR_100BTX_FD (1 << 8)
91 #define ANAR_100BTX (1 << 7)
92 #define ANAR_10BT_FD (1 << 6)
93 #define ANAR_10BT (1 << 5)
94 #define ANAR_SELECTOR4 (1 << 4)
95 #define ANAR_SELECTOR3 (1 << 3)
96 #define ANAR_SELECTOR2 (1 << 2)
97 #define ANAR_SELECTOR1 (1 << 1)
98 #define ANAR_SELECTOR0 (1 << 0)
99 
100 //ANLPAR register
101 #define ANLPAR_NP (1 << 15)
102 #define ANLPAR_ACK (1 << 14)
103 #define ANLPAR_RF (1 << 13)
104 #define ANLPAR_PAUSE (1 << 10)
105 #define ANLPAR_100BT4 (1 << 9)
106 #define ANLPAR_100BTX_FD (1 << 8)
107 #define ANLPAR_100BTX (1 << 7)
108 #define ANLPAR_10BT_FD (1 << 6)
109 #define ANLPAR_10BT (1 << 5)
110 #define ANLPAR_SELECTOR4 (1 << 4)
111 #define ANLPAR_SELECTOR3 (1 << 3)
112 #define ANLPAR_SELECTOR2 (1 << 2)
113 #define ANLPAR_SELECTOR1 (1 << 1)
114 #define ANLPAR_SELECTOR0 (1 << 0)
115 
116 //ANER register
117 #define ANER_PDF (1 << 4)
118 #define ANER_LP_NP_ABLE (1 << 3)
119 #define ANER_NP_ABLE (1 << 2)
120 #define ANER_PAGE_RX (1 << 1)
121 #define ANER_LP_AN_ABLE (1 << 0)
122 
123 //SRR register
124 #define SRR_SILICON_REVISON3 (1 << 9)
125 #define SRR_SILICON_REVISON2 (1 << 8)
126 #define SRR_SILICON_REVISON1 (1 << 7)
127 #define SRR_SILICON_REVISON0 (1 << 6)
128 
129 //MCSR register
130 #define MCSR_EDPWRDOWN (1 << 13)
131 #define MCSR_LOWSQEN (1 << 11)
132 #define MCSR_MDPREBP (1 << 10)
133 #define MCSR_FARLOOPBACK (1 << 9)
134 #define MCSR_ALTINT (1 << 6)
135 #define MCSR_PHYADBP (1 << 3)
136 #define MCSR_FORCE_GOOD_LINK_STATUS (1 << 2)
137 #define MCSR_ENERGYON (1 << 1)
138 
139 //SMR register
140 #define SMR_MODE2 (1 << 7)
141 #define SMR_MODE1 (1 << 6)
142 #define SMR_MODE0 (1 << 5)
143 #define SMR_PHYAD4 (1 << 4)
144 #define SMR_PHYAD3 (1 << 3)
145 #define SMR_PHYAD2 (1 << 2)
146 #define SMR_PHYAD1 (1 << 1)
147 #define SMR_PHYAD0 (1 << 0)
148 
149 //SCSIR register
150 #define SCSIR_AMDIXCTRL (1 << 15)
151 #define SCSIR_CH_SELECT (1 << 13)
152 #define SCSIR_SQEOFF (1 << 11)
153 #define SCSIR_XPOL (1 << 4)
154 
155 //ISR register
156 #define ISR_ENERGYON (1 << 7)
157 #define ISR_AN_COMPLETE (1 << 6)
158 #define ISR_REMOTE_FAULT (1 << 5)
159 #define ISR_LINK_DOWN (1 << 4)
160 #define ISR_AN_LP_ACK (1 << 3)
161 #define ISR_PD_FAULT (1 << 2)
162 #define ISR_AN_PAGE_RECEIVED (1 << 1)
163 
164 //IMR register
165 #define IMR_ENERGYON (1 << 7)
166 #define IMR_AN_COMPLETE (1 << 6)
167 #define IMR_REMOTE_FAULT (1 << 5)
168 #define IMR_LINK_DOWN (1 << 4)
169 #define IMR_AN_LP_ACK (1 << 3)
170 #define IMR_PD_FAULT (1 << 2)
171 #define IMR_AN_PAGE_RECEIVED (1 << 1)
172 
173 //PSCSR register
174 #define PSCSR_AUTODONE (1 << 12)
175 #define PSCSR_GPO2 (1 << 9)
176 #define PSCSR_GPO1 (1 << 8)
177 #define PSCSR_GPO0 (1 << 7)
178 #define PSCSR_ENABLE_4B5B (1 << 6)
179 #define PSCSR_HCDSPEED2 (1 << 4)
180 #define PSCSR_HCDSPEED1 (1 << 3)
181 #define PSCSR_HCDSPEED0 (1 << 2)
182 #define PSCSR_SCRAMBLE_DISABLE (1 << 0)
183 
184 //Speed indication
185 #define PSCSR_HCDSPEED_MASK (7 << 2)
186 #define PSCSR_HCDSPEED_10BT (1 << 2)
187 #define PSCSR_HCDSPEED_100BTX (2 << 2)
188 #define PSCSR_HCDSPEED_10BT_FD (5 << 2)
189 #define PSCSR_HCDSPEED_100BTX_FD (6 << 2)
190 
191 //C++ guard
192 #ifdef __cplusplus
193  extern "C" {
194 #endif
195 
196 //LAN8720 Ethernet PHY driver
197 extern const PhyDriver lan8720PhyDriver;
198 
199 //LAN8720 related functions
200 error_t lan8720Init(NetInterface *interface);
201 
202 void lan8720Tick(NetInterface *interface);
203 
204 void lan8720EnableIrq(NetInterface *interface);
205 void lan8720DisableIrq(NetInterface *interface);
206 
207 void lan8720EventHandler(NetInterface *interface);
208 
209 void lan8720WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
210 uint16_t lan8720ReadPhyReg(NetInterface *interface, uint8_t address);
211 
212 void lan8720DumpPhyReg(NetInterface *interface);
213 
214 //C++ guard
215 #ifdef __cplusplus
216  }
217 #endif
218 
219 #endif
error_t lan8720Init(NetInterface *interface)
LAN8720 PHY transceiver initialization.
void lan8720WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
void lan8720EventHandler(NetInterface *interface)
LAN8720 event handler.
void lan8720DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
void lan8720DisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t lan8720ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
PHY driver.
Definition: nic.h:196
void lan8720EnableIrq(NetInterface *interface)
Enable interrupts.
const PhyDriver lan8720PhyDriver
LAN8720 Ethernet PHY driver.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
void lan8720Tick(NetInterface *interface)
LAN8720 timer handler.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
Network interface controller abstraction layer.