lan8742_driver.h
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1 /**
2  * @file lan8742_driver.h
3  * @brief LAN8742 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _LAN8742_DRIVER_H
30 #define _LAN8742_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef LAN8742_PHY_ADDR
37  #define LAN8742_PHY_ADDR 0
38 #elif (LAN8742_PHY_ADDR < 0 || LAN8742_PHY_ADDR > 31)
39  #error LAN8742_PHY_ADDR parameter is not valid
40 #endif
41 
42 //LAN8742 registers
43 #define LAN8742_PHY_REG_BMCR 0x00
44 #define LAN8742_PHY_REG_BMSR 0x01
45 #define LAN8742_PHY_REG_PHYIDR1 0x02
46 #define LAN8742_PHY_REG_PHYIDR2 0x03
47 #define LAN8742_PHY_REG_ANAR 0x04
48 #define LAN8742_PHY_REG_ANLPAR 0x05
49 #define LAN8742_PHY_REG_ANER 0x06
50 #define LAN8742_PHY_REG_ANNPTR 0x07
51 #define LAN8742_PHY_REG_ANNPRR 0x08
52 #define LAN8742_PHY_REG_MMDACR 0x0D
53 #define LAN8742_PHY_REG_MMDAADR 0x0E
54 #define LAN8742_PHY_REG_ENCTR 0x10
55 #define LAN8742_PHY_REG_MCSR 0x11
56 #define LAN8742_PHY_REG_SMR 0x12
57 #define LAN8742_PHY_REG_TDRPDCR 0x18
58 #define LAN8742_PHY_REG_TDRCSR 0x19
59 #define LAN8742_PHY_REG_SECR 0x1A
60 #define LAN8742_PHY_REG_SCSIR 0x1B
61 #define LAN8742_PHY_REG_CLR 0x1C
62 #define LAN8742_PHY_REG_ISR 0x1D
63 #define LAN8742_PHY_REG_IMR 0x1E
64 #define LAN8742_PHY_REG_PSCSR 0x1F
65 
66 //BMCR register
67 #define BMCR_RESET (1 << 15)
68 #define BMCR_LOOPBACK (1 << 14)
69 #define BMCR_SPEED_SEL (1 << 13)
70 #define BMCR_AN_EN (1 << 12)
71 #define BMCR_POWER_DOWN (1 << 11)
72 #define BMCR_ISOLATE (1 << 10)
73 #define BMCR_RESTART_AN (1 << 9)
74 #define BMCR_DUPLEX_MODE (1 << 8)
75 #define BMCR_COL_TEST (1 << 7)
76 
77 //BMSR register
78 #define BMSR_100BT4 (1 << 15)
79 #define BMSR_100BTX_FD (1 << 14)
80 #define BMSR_100BTX (1 << 13)
81 #define BMSR_10BT_FD (1 << 12)
82 #define BMSR_10BT (1 << 11)
83 #define BMSR_100BT2_FD (1 << 10)
84 #define BMSR_100BT2 (1 << 9)
85 #define BMSR_EXTENTED_STATUS (1 << 8)
86 #define BMSR_AN_COMPLETE (1 << 5)
87 #define BMSR_REMOTE_FAULT (1 << 4)
88 #define BMSR_AN_ABLE (1 << 3)
89 #define BMSR_LINK_STATUS (1 << 2)
90 #define BMSR_JABBER_DETECT (1 << 1)
91 #define BMSR_EXTENDED_CAP (1 << 0)
92 
93 //ANAR register
94 #define ANAR_NP (1 << 15)
95 #define ANAR_RF (1 << 13)
96 #define ANAR_PAUSE1 (1 << 11)
97 #define ANAR_PAUSE0 (1 << 10)
98 #define ANAR_100BTX_FD (1 << 8)
99 #define ANAR_100BTX (1 << 7)
100 #define ANAR_10BT_FD (1 << 6)
101 #define ANAR_10BT (1 << 5)
102 #define ANAR_SELECTOR4 (1 << 4)
103 #define ANAR_SELECTOR3 (1 << 3)
104 #define ANAR_SELECTOR2 (1 << 2)
105 #define ANAR_SELECTOR1 (1 << 1)
106 #define ANAR_SELECTOR0 (1 << 0)
107 
108 //ANLPAR register
109 #define ANLPAR_NP (1 << 15)
110 #define ANLPAR_ACK (1 << 14)
111 #define ANLPAR_RF (1 << 13)
112 #define ANLPAR_PAUSE1 (1 << 11)
113 #define ANLPAR_PAUSE0 (1 << 10)
114 #define ANLPAR_100BT4 (1 << 9)
115 #define ANLPAR_100BTX_FD (1 << 8)
116 #define ANLPAR_100BTX (1 << 7)
117 #define ANLPAR_10BT_FD (1 << 6)
118 #define ANLPAR_10BT (1 << 5)
119 #define ANLPAR_SELECTOR4 (1 << 4)
120 #define ANLPAR_SELECTOR3 (1 << 3)
121 #define ANLPAR_SELECTOR2 (1 << 2)
122 #define ANLPAR_SELECTOR1 (1 << 1)
123 #define ANLPAR_SELECTOR0 (1 << 0)
124 
125 //ANER register
126 #define ANER_RX_NP_LOC_ABLE (1 << 6)
127 #define ANER_RX_NP_STOR_LOC (1 << 5)
128 #define ANER_PDF (1 << 4)
129 #define ANER_LP_NP_ABLE (1 << 3)
130 #define ANER_NP_ABLE (1 << 2)
131 #define ANER_PAGE_RX (1 << 1)
132 #define ANER_LP_AN_ABLE (1 << 0)
133 
134 //ANNPTR register
135 #define ANNPTR_NEXT_PAGE (1 << 15)
136 #define ANNPTR_MSG_PAGE (1 << 13)
137 #define ANNPTR_ACK2 (1 << 12)
138 #define ANNPTR_TOGGLE (1 << 11)
139 #define ANNPTR_MESSAGE10 (1 << 10)
140 #define ANNPTR_MESSAGE9 (1 << 9)
141 #define ANNPTR_MESSAGE8 (1 << 8)
142 #define ANNPTR_MESSAGE7 (1 << 7)
143 #define ANNPTR_MESSAGE6 (1 << 6)
144 #define ANNPTR_MESSAGE5 (1 << 5)
145 #define ANNPTR_MESSAGE4 (1 << 4)
146 #define ANNPTR_MESSAGE3 (1 << 3)
147 #define ANNPTR_MESSAGE2 (1 << 2)
148 #define ANNPTR_MESSAGE1 (1 << 1)
149 #define ANNPTR_MESSAGE0 (1 << 0)
150 
151 //ANNPRR register
152 #define ANNPRR_NEXT_PAGE (1 << 15)
153 #define ANNPRR_ACK (1 << 14)
154 #define ANNPRR_MSG_PAGE (1 << 13)
155 #define ANNPRR_ACK2 (1 << 12)
156 #define ANNPRR_TOGGLE (1 << 11)
157 #define ANNPRR_MESSAGE10 (1 << 10)
158 #define ANNPRR_MESSAGE9 (1 << 9)
159 #define ANNPRR_MESSAGE8 (1 << 8)
160 #define ANNPRR_MESSAGE7 (1 << 7)
161 #define ANNPRR_MESSAGE6 (1 << 6)
162 #define ANNPRR_MESSAGE5 (1 << 5)
163 #define ANNPRR_MESSAGE4 (1 << 4)
164 #define ANNPRR_MESSAGE3 (1 << 3)
165 #define ANNPRR_MESSAGE2 (1 << 2)
166 #define ANNPRR_MESSAGE1 (1 << 1)
167 #define ANNPRR_MESSAGE0 (1 << 0)
168 
169 //MMDACR register
170 #define MMDACR_FUNCTION1 (1 << 15)
171 #define MMDACR_FUNCTION0 (1 << 14)
172 #define MMDACR_DEVAD4 (1 << 4)
173 #define MMDACR_DEVAD3 (1 << 3)
174 #define MMDACR_DEVAD2 (1 << 2)
175 #define MMDACR_DEVAD1 (1 << 1)
176 #define MMDACR_DEVAD0 (1 << 0)
177 
178 //ENCTR register
179 #define ENCTR_EDPD_TX_NLP_EN (1 << 15)
180 #define ENCTR_EDPD_TX_NLP_ITS1 (1 << 14)
181 #define ENCTR_EDPD_TX_NLP_ITS0 (1 << 13)
182 #define ENCTR_EDPD_RX_NLP_WAKE_EN (1 << 12)
183 #define ENCTR_EDPD_RX_NLP_MIDS1 (1 << 11)
184 #define ENCTR_EDPD_RX_NLP_MIDS0 (1 << 10)
185 #define ENCTR_EDPD_EXT_CROSSOVER (1 << 1)
186 #define ENCTR_EXT_CROSSOVER_TIME (1 << 0)
187 
188 //MCSR register
189 #define MCSR_EDPWRDOWN (1 << 13)
190 #define MCSR_FARLOOPBACK (1 << 9)
191 #define MCSR_ALTINT (1 << 6)
192 #define MCSR_ENERGYON (1 << 1)
193 
194 //SMR register
195 #define SMR_MODE2 (1 << 7)
196 #define SMR_MODE1 (1 << 6)
197 #define SMR_MODE0 (1 << 5)
198 #define SMR_PHYAD4 (1 << 4)
199 #define SMR_PHYAD3 (1 << 3)
200 #define SMR_PHYAD2 (1 << 2)
201 #define SMR_PHYAD1 (1 << 1)
202 #define SMR_PHYAD0 (1 << 0)
203 
204 //TDRPDCR register
205 #define TDRPDCR_DELAY_IN (1 << 15)
206 #define TDRPDCR_LINE_BREAK_COUNTER2 (1 << 14)
207 #define TDRPDCR_LINE_BREAK_COUNTER1 (1 << 13)
208 #define TDRPDCR_LINE_BREAK_COUNTER0 (1 << 12)
209 #define TDRPDCR_PATTERN_HIGH5 (1 << 11)
210 #define TDRPDCR_PATTERN_HIGH4 (1 << 10)
211 #define TDRPDCR_PATTERN_HIGH3 (1 << 9)
212 #define TDRPDCR_PATTERN_HIGH2 (1 << 8)
213 #define TDRPDCR_PATTERN_HIGH1 (1 << 7)
214 #define TDRPDCR_PATTERN_HIGH0 (1 << 6)
215 #define TDRPDCR_PATTERN_LOW5 (1 << 5)
216 #define TDRPDCR_PATTERN_LOW4 (1 << 4)
217 #define TDRPDCR_PATTERN_LOW3 (1 << 3)
218 #define TDRPDCR_PATTERN_LOW2 (1 << 2)
219 #define TDRPDCR_PATTERN_LOW1 (1 << 1)
220 #define TDRPDCR_PATTERN_LOW0 (1 << 0)
221 
222 //TDRCSR register
223 #define TDRCSR_EN (1 << 15)
224 #define TDRCSR_AD_FILTER_EN (1 << 14)
225 #define TDRCSR_CH_CABLE_TYPE1 (1 << 10)
226 #define TDRCSR_CH_CABLE_TYPE0 (1 << 9)
227 #define TDRCSR_CH_STATUS (1 << 8)
228 #define TDRCSR_CH_LENGTH7 (1 << 7)
229 #define TDRCSR_CH_LENGTH6 (1 << 6)
230 #define TDRCSR_CH_LENGTH5 (1 << 5)
231 #define TDRCSR_CH_LENGTH4 (1 << 4)
232 #define TDRCSR_CH_LENGTH3 (1 << 3)
233 #define TDRCSR_CH_LENGTH2 (1 << 2)
234 #define TDRCSR_CH_LENGTH1 (1 << 1)
235 #define TDRCSR_CH_LENGTH0 (1 << 0)
236 
237 //SCSIR register
238 #define SCSIR_AMDIXCTRL (1 << 15)
239 #define SCSIR_CH_SELECT (1 << 13)
240 #define SCSIR_SQEOFF (1 << 11)
241 #define SCSIR_XPOL (1 << 4)
242 
243 //CLR register
244 #define CLR_CBLN3 (1 << 15)
245 #define CLR_CBLN2 (1 << 14)
246 #define CLR_CBLN1 (1 << 13)
247 #define CLR_CBLN0 (1 << 12)
248 
249 //ISR register
250 #define ISR_WOL (1 << 8)
251 #define ISR_ENERGYON (1 << 7)
252 #define ISR_AN_COMPLETE (1 << 6)
253 #define ISR_REMOTE_FAULT (1 << 5)
254 #define ISR_LINK_DOWN (1 << 4)
255 #define ISR_AN_LP_ACK (1 << 3)
256 #define ISR_PD_FAULT (1 << 2)
257 #define ISR_AN_PAGE_RECEIVED (1 << 1)
258 
259 //IMR register
260 #define IMR_WOL (1 << 8)
261 #define IMR_ENERGYON (1 << 7)
262 #define IMR_AN_COMPLETE (1 << 6)
263 #define IMR_REMOTE_FAULT (1 << 5)
264 #define IMR_LINK_DOWN (1 << 4)
265 #define IMR_AN_LP_ACK (1 << 3)
266 #define IMR_PD_FAULT (1 << 2)
267 #define IMR_AN_PAGE_RECEIVED (1 << 1)
268 
269 //PSCSR register
270 #define PSCSR_AUTODONE (1 << 12)
271 #define PSCSR_HCDSPEED2 (1 << 4)
272 #define PSCSR_HCDSPEED1 (1 << 3)
273 #define PSCSR_HCDSPEED0 (1 << 2)
274 
275 //Speed indication
276 #define PSCSR_HCDSPEED_MASK (7 << 2)
277 #define PSCSR_HCDSPEED_10BT (1 << 2)
278 #define PSCSR_HCDSPEED_100BTX (2 << 2)
279 #define PSCSR_HCDSPEED_10BT_FD (5 << 2)
280 #define PSCSR_HCDSPEED_100BTX_FD (6 << 2)
281 
282 //C++ guard
283 #ifdef __cplusplus
284  extern "C" {
285 #endif
286 
287 //LAN8742 Ethernet PHY driver
288 extern const PhyDriver lan8742PhyDriver;
289 
290 //LAN8742 related functions
291 error_t lan8742Init(NetInterface *interface);
292 
293 void lan8742Tick(NetInterface *interface);
294 
295 void lan8742EnableIrq(NetInterface *interface);
296 void lan8742DisableIrq(NetInterface *interface);
297 
298 void lan8742EventHandler(NetInterface *interface);
299 
300 void lan8742WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
301 uint16_t lan8742ReadPhyReg(NetInterface *interface, uint8_t address);
302 
303 void lan8742DumpPhyReg(NetInterface *interface);
304 
305 //C++ guard
306 #ifdef __cplusplus
307  }
308 #endif
309 
310 #endif
void lan8742EnableIrq(NetInterface *interface)
Enable interrupts.
void lan8742EventHandler(NetInterface *interface)
LAN8742 event handler.
const PhyDriver lan8742PhyDriver
LAN8742 Ethernet PHY driver.
error_t lan8742Init(NetInterface *interface)
LAN8742 PHY transceiver initialization.
void lan8742WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
PHY driver.
Definition: nic.h:196
void lan8742Tick(NetInterface *interface)
LAN8742 timer handler.
uint16_t lan8742ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
void lan8742DisableIrq(NetInterface *interface)
Disable interrupts.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void lan8742DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
Network interface controller abstraction layer.