Go to the documentation of this file.
31 #ifndef _MIMXRT1160_ETH1_DRIVER_H
32 #define _MIMXRT1160_ETH1_DRIVER_H
35 #ifndef MIMXRT1160_ETH1_TX_BUFFER_COUNT
36 #define MIMXRT1160_ETH1_TX_BUFFER_COUNT 8
37 #elif (MIMXRT1160_ETH1_TX_BUFFER_COUNT < 1)
38 #error MIMXRT1160_ETH1_TX_BUFFER_COUNT parameter is not valid
42 #ifndef MIMXRT1160_ETH1_TX_BUFFER_SIZE
43 #define MIMXRT1160_ETH1_TX_BUFFER_SIZE 1536
44 #elif (MIMXRT1160_ETH1_TX_BUFFER_SIZE != 1536)
45 #error MIMXRT1160_ETH1_TX_BUFFER_SIZE parameter is not valid
49 #ifndef MIMXRT1160_ETH1_RX_BUFFER_COUNT
50 #define MIMXRT1160_ETH1_RX_BUFFER_COUNT 8
51 #elif (MIMXRT1160_ETH1_RX_BUFFER_COUNT < 1)
52 #error MIMXRT1160_ETH1_RX_BUFFER_COUNT parameter is not valid
56 #ifndef MIMXRT1160_ETH1_RX_BUFFER_SIZE
57 #define MIMXRT1160_ETH1_RX_BUFFER_SIZE 1536
58 #elif (MIMXRT1160_ETH1_RX_BUFFER_SIZE != 1536)
59 #error MIMXRT1160_ETH1_RX_BUFFER_SIZE parameter is not valid
63 #ifndef MIMXRT1160_ETH1_IRQ_PRIORITY_GROUPING
64 #define MIMXRT1160_ETH1_IRQ_PRIORITY_GROUPING 3
65 #elif (MIMXRT1160_ETH1_IRQ_PRIORITY_GROUPING < 0)
66 #error MIMXRT1160_ETH1_IRQ_PRIORITY_GROUPING parameter is not valid
70 #ifndef MIMXRT1160_ETH1_IRQ_GROUP_PRIORITY
71 #define MIMXRT1160_ETH1_IRQ_GROUP_PRIORITY 12
72 #elif (MIMXRT1160_ETH1_IRQ_GROUP_PRIORITY < 0)
73 #error MIMXRT1160_ETH1_IRQ_GROUP_PRIORITY parameter is not valid
77 #ifndef MIMXRT1160_ETH1_IRQ_SUB_PRIORITY
78 #define MIMXRT1160_ETH1_IRQ_SUB_PRIORITY 0
79 #elif (MIMXRT1160_ETH1_IRQ_SUB_PRIORITY < 0)
80 #error MIMXRT1160_ETH1_IRQ_SUB_PRIORITY parameter is not valid
84 #ifndef MIMXRT1160_ETH1_RAM_SECTION
85 #define MIMXRT1160_ETH1_RAM_SECTION ".ram_no_cache"
89 #define ENET_TBD0_R 0x80000000
90 #define ENET_TBD0_TO1 0x40000000
91 #define ENET_TBD0_W 0x20000000
92 #define ENET_TBD0_TO2 0x10000000
93 #define ENET_TBD0_L 0x08000000
94 #define ENET_TBD0_TC 0x04000000
95 #define ENET_TBD0_DATA_LENGTH 0x0000FFFF
96 #define ENET_TBD1_DATA_POINTER 0xFFFFFFFF
97 #define ENET_TBD2_INT 0x40000000
98 #define ENET_TBD2_TS 0x20000000
99 #define ENET_TBD2_PINS 0x10000000
100 #define ENET_TBD2_IINS 0x08000000
101 #define ENET_TBD2_TXE 0x00008000
102 #define ENET_TBD2_UE 0x00002000
103 #define ENET_TBD2_EE 0x00001000
104 #define ENET_TBD2_FE 0x00000800
105 #define ENET_TBD2_LCE 0x00000400
106 #define ENET_TBD2_OE 0x00000200
107 #define ENET_TBD2_TSE 0x00000100
108 #define ENET_TBD4_BDU 0x80000000
109 #define ENET_TBD5_TIMESTAMP 0xFFFFFFFF
112 #define ENET_RBD0_E 0x80000000
113 #define ENET_RBD0_RO1 0x40000000
114 #define ENET_RBD0_W 0x20000000
115 #define ENET_RBD0_RO2 0x10000000
116 #define ENET_RBD0_L 0x08000000
117 #define ENET_RBD0_M 0x01000000
118 #define ENET_RBD0_BC 0x00800000
119 #define ENET_RBD0_MC 0x00400000
120 #define ENET_RBD0_LG 0x00200000
121 #define ENET_RBD0_NO 0x00100000
122 #define ENET_RBD0_CR 0x00040000
123 #define ENET_RBD0_OV 0x00020000
124 #define ENET_RBD0_TR 0x00010000
125 #define ENET_RBD0_DATA_LENGTH 0x0000FFFF
126 #define ENET_RBD1_DATA_POINTER 0xFFFFFFFF
127 #define ENET_RBD2_ME 0x80000000
128 #define ENET_RBD2_PE 0x04000000
129 #define ENET_RBD2_CE 0x02000000
130 #define ENET_RBD2_UC 0x01000000
131 #define ENET_RBD2_INT 0x00800000
132 #define ENET_RBD2_VPCP 0x0000E000
133 #define ENET_RBD2_ICE 0x00000020
134 #define ENET_RBD2_PCR 0x00000010
135 #define ENET_RBD2_VLAN 0x00000004
136 #define ENET_RBD2_IPV6 0x00000002
137 #define ENET_RBD2_FRAG 0x00000001
138 #define ENET_RBD3_HEADER_LENGTH 0xF8000000
139 #define ENET_RBD3_PROTOCOL_TYPE 0x00FF0000
140 #define ENET_RBD3_PAYLOAD_CHECKSUM 0x0000FFFF
141 #define ENET_RBD4_BDU 0x80000000
142 #define ENET_RBD5_TIMESTAMP 0xFFFFFFFF
Structure describing a buffer that spans multiple chunks.
error_t mimxrt1160Eth1Init(NetInterface *interface)
i.MX RT1160 Ethernet MAC initialization
uint32_t mimxrt1160Eth1CalcCrc(const void *data, size_t length)
CRC calculation.
void mimxrt1160Eth1EventHandler(NetInterface *interface)
i.MX RT1160 Ethernet MAC event handler
void mimxrt1160Eth1InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
error_t mimxrt1160Eth1UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void mimxrt1160Eth1EnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t mimxrt1160Eth1ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void mimxrt1160Eth1DisableIrq(NetInterface *interface)
Disable interrupts.
error_t mimxrt1160Eth1ReceivePacket(NetInterface *interface)
Receive a packet.
void mimxrt1160Eth1Tick(NetInterface *interface)
i.MX RT1160 Ethernet MAC timer handler
error_t mimxrt1160Eth1UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void mimxrt1160Eth1InitGpio(NetInterface *interface)
GPIO configuration.
const NicDriver mimxrt1160Eth1Driver
i.MX RT1160 Ethernet MAC driver (ENET instance)
error_t mimxrt1160Eth1SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void mimxrt1160Eth1WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.