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31 #ifndef _MIMXRT1170_ETH2_DRIVER_H
32 #define _MIMXRT1170_ETH2_DRIVER_H
38 #ifndef MIMXRT1170_ETH2_TX_BUFFER_COUNT
39 #define MIMXRT1170_ETH2_TX_BUFFER_COUNT 8
40 #elif (MIMXRT1170_ETH2_TX_BUFFER_COUNT < 1)
41 #error MIMXRT1170_ETH2_TX_BUFFER_COUNT parameter is not valid
45 #ifndef MIMXRT1170_ETH2_TX_BUFFER_SIZE
46 #define MIMXRT1170_ETH2_TX_BUFFER_SIZE 1536
47 #elif (MIMXRT1170_ETH2_TX_BUFFER_SIZE != 1536)
48 #error MIMXRT1170_ETH2_TX_BUFFER_SIZE parameter is not valid
52 #ifndef MIMXRT1170_ETH2_RX_BUFFER_COUNT
53 #define MIMXRT1170_ETH2_RX_BUFFER_COUNT 8
54 #elif (MIMXRT1170_ETH2_RX_BUFFER_COUNT < 1)
55 #error MIMXRT1170_ETH2_RX_BUFFER_COUNT parameter is not valid
59 #ifndef MIMXRT1170_ETH2_RX_BUFFER_SIZE
60 #define MIMXRT1170_ETH2_RX_BUFFER_SIZE 1536
61 #elif (MIMXRT1170_ETH2_RX_BUFFER_SIZE != 1536)
62 #error MIMXRT1170_ETH2_RX_BUFFER_SIZE parameter is not valid
66 #ifndef MIMXRT1170_ETH2_IRQ_PRIORITY_GROUPING
67 #define MIMXRT1170_ETH2_IRQ_PRIORITY_GROUPING 3
68 #elif (MIMXRT1170_ETH2_IRQ_PRIORITY_GROUPING < 0)
69 #error MIMXRT1170_ETH2_IRQ_PRIORITY_GROUPING parameter is not valid
73 #ifndef MIMXRT1170_ETH2_IRQ_GROUP_PRIORITY
74 #define MIMXRT1170_ETH2_IRQ_GROUP_PRIORITY 12
75 #elif (MIMXRT1170_ETH2_IRQ_GROUP_PRIORITY < 0)
76 #error MIMXRT1170_ETH2_IRQ_GROUP_PRIORITY parameter is not valid
80 #ifndef MIMXRT1170_ETH2_IRQ_SUB_PRIORITY
81 #define MIMXRT1170_ETH2_IRQ_SUB_PRIORITY 0
82 #elif (MIMXRT1170_ETH2_IRQ_SUB_PRIORITY < 0)
83 #error MIMXRT1170_ETH2_IRQ_SUB_PRIORITY parameter is not valid
87 #ifndef MIMXRT1170_ETH2_RAM_SECTION
88 #define MIMXRT1170_ETH2_RAM_SECTION ".ram_no_cache"
92 #define ENET_TBD0_R 0x80000000
93 #define ENET_TBD0_TO1 0x40000000
94 #define ENET_TBD0_W 0x20000000
95 #define ENET_TBD0_TO2 0x10000000
96 #define ENET_TBD0_L 0x08000000
97 #define ENET_TBD0_TC 0x04000000
98 #define ENET_TBD0_DATA_LENGTH 0x0000FFFF
99 #define ENET_TBD1_DATA_POINTER 0xFFFFFFFF
100 #define ENET_TBD2_INT 0x40000000
101 #define ENET_TBD2_TS 0x20000000
102 #define ENET_TBD2_PINS 0x10000000
103 #define ENET_TBD2_IINS 0x08000000
104 #define ENET_TBD2_TXE 0x00008000
105 #define ENET_TBD2_UE 0x00002000
106 #define ENET_TBD2_EE 0x00001000
107 #define ENET_TBD2_FE 0x00000800
108 #define ENET_TBD2_LCE 0x00000400
109 #define ENET_TBD2_OE 0x00000200
110 #define ENET_TBD2_TSE 0x00000100
111 #define ENET_TBD4_BDU 0x80000000
112 #define ENET_TBD5_TIMESTAMP 0xFFFFFFFF
115 #define ENET_RBD0_E 0x80000000
116 #define ENET_RBD0_RO1 0x40000000
117 #define ENET_RBD0_W 0x20000000
118 #define ENET_RBD0_RO2 0x10000000
119 #define ENET_RBD0_L 0x08000000
120 #define ENET_RBD0_M 0x01000000
121 #define ENET_RBD0_BC 0x00800000
122 #define ENET_RBD0_MC 0x00400000
123 #define ENET_RBD0_LG 0x00200000
124 #define ENET_RBD0_NO 0x00100000
125 #define ENET_RBD0_CR 0x00040000
126 #define ENET_RBD0_OV 0x00020000
127 #define ENET_RBD0_TR 0x00010000
128 #define ENET_RBD0_DATA_LENGTH 0x0000FFFF
129 #define ENET_RBD1_DATA_POINTER 0xFFFFFFFF
130 #define ENET_RBD2_ME 0x80000000
131 #define ENET_RBD2_PE 0x04000000
132 #define ENET_RBD2_CE 0x02000000
133 #define ENET_RBD2_UC 0x01000000
134 #define ENET_RBD2_INT 0x00800000
135 #define ENET_RBD2_VPCP 0x0000E000
136 #define ENET_RBD2_ICE 0x00000020
137 #define ENET_RBD2_PCR 0x00000010
138 #define ENET_RBD2_VLAN 0x00000004
139 #define ENET_RBD2_IPV6 0x00000002
140 #define ENET_RBD2_FRAG 0x00000001
141 #define ENET_RBD3_HEADER_LENGTH 0xF8000000
142 #define ENET_RBD3_PROTOCOL_TYPE 0x00FF0000
143 #define ENET_RBD3_PAYLOAD_CHECKSUM 0x0000FFFF
144 #define ENET_RBD4_BDU 0x80000000
145 #define ENET_RBD5_TIMESTAMP 0xFFFFFFFF
error_t mimxrt1170Eth2UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t mimxrt1170Eth2UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
const NicDriver mimxrt1170Eth2Driver
i.MX RT1170 Ethernet MAC driver (ENET_1G instance)
Structure describing a buffer that spans multiple chunks.
void mimxrt1170Eth2WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t mimxrt1170Eth2Init(NetInterface *interface)
i.MX RT1170 Ethernet MAC initialization
void mimxrt1170Eth2Tick(NetInterface *interface)
i.MX RT1170 Ethernet MAC timer handler
uint16_t mimxrt1170Eth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void mimxrt1170Eth2InitBufferDesc(NetInterface *interface)
Initialize buffer descriptors.
error_t mimxrt1170Eth2SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
error_t mimxrt1170Eth2ReceivePacket(NetInterface *interface)
Receive a packet.
uint32_t mimxrt1170Eth2CalcCrc(const void *data, size_t length)
CRC calculation.
void mimxrt1170Eth2InitGpio(NetInterface *interface)
GPIO configuration.
void mimxrt1170Eth2EnableIrq(NetInterface *interface)
Enable interrupts.
void mimxrt1170Eth2DisableIrq(NetInterface *interface)
Disable interrupts.
void mimxrt1170Eth2EventHandler(NetInterface *interface)
i.MX RT1170 Ethernet MAC event handler
Network interface controller abstraction layer.