sja1105_driver.h
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1 /**
2  * @file sja1105_driver.h
3  * @brief SJA1105 5-port Ethernet switch driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.4
29  **/
30 
31 #ifndef _SJA1105_DRIVER_H
32 #define _SJA1105_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Port identifiers
38 #define SJA1105_PORT0 1
39 #define SJA1105_PORT1 2
40 #define SJA1105_PORT2 3
41 #define SJA1105_PORT3 4
42 #define SJA1105_PORT4 5
43 
44 //SPI control word
45 #define SJA1105_SPI_CTRL_WRITE 0x80000000
46 #define SJA1105_SPI_CTRL_READ 0x00000000
47 #define SJA1105_SPI_CTRL_RC 0x7E000000
48 #define SJA1105_SPI_CTRL_ADDR 0x01FFFFF0
49 
50 //SJA1105 memory map
51 #define SJA1105_ETH_DYN_BASE 0x00000000
52 #define SJA1105_ETH_STATIC_BASE 0x00020000
53 #define SJA1105_CGU_BASE 0x00100000
54 #define SJA1105_RGU_BASE 0x00100400
55 #define SJA1105_ACU_BASE 0x00100800
56 #define SJA1105_SGMII_BASE 0x00180000
57 
58 //SJA1105 SPI registers
59 #define SJA1105_DEVICE_ID 0x000000
60 #define SJA1105_INIT_DEV_CONFIG_FLAG 0x000001
61 #define SJA1105_VL_ROUTE_PARTITION_STATUS 0x000002
62 #define SJA1105_GENERAL_STATUS1 0x000003
63 #define SJA1105_GENERAL_STATUS2 0x000004
64 #define SJA1105_GENERAL_STATUS3 0x000005
65 #define SJA1105_GENERAL_STATUS4 0x000006
66 #define SJA1105_GENERAL_STATUS5 0x000007
67 #define SJA1105_GENERAL_STATUS6 0x000008
68 #define SJA1105_GENERAL_STATUS7 0x000009
69 #define SJA1105_GENERAL_STATUS8 0x00000A
70 #define SJA1105_GENERAL_STATUS9 0x00000B
71 #define SJA1105_GENERAL_STATUS10 0x00000C
72 #define SJA1105_GENERAL_STATUS11 0x00000D
73 #define SJA1105_RAM_PARITY_CHECK_CONFIG0 0x00000E
74 #define SJA1105_RAM_PARITY_CHECK_CONFIG1 0x00000F
75 #define SJA1105_PORT_STATUS_CTRL0 0x000010
76 #define SJA1105_VL_STATUS_CTRL 0x000011
77 #define SJA1105_PORT_STATUS_CTRL1 0x000012
78 #define SJA1105_PTP_CTRL2 0x000013
79 #define SJA1105_PTP_CTRL3 0x000014
80 #define SJA1105_PTP_CTRL4 0x000015
81 #define SJA1105_PTP_CTRL5 0x000016
82 #define SJA1105_PTP_CTRL6 0x000017
83 #define SJA1105_PTP_CTRL1 0x000018
84 #define SJA1105_PTP_CTRL7 0x000019
85 #define SJA1105_PTP_CTRL8 0x00001A
86 #define SJA1105_PTP_CTRL9 0x00001B
87 #define SJA1105_PTP_CTRL10 0x00001C
88 #define SJA1105_PTP_CTRL11 0x00001D
89 #define SJA1105_PTP_CTRL12 0x00001E
90 #define SJA1105_PTP_CTRL13 0x00001F
91 #define SJA1105_PTP_CTRL14 0x000020
92 #define SJA1105_L2_ADDR_LUT_RECONFIG1 0x000024
93 #define SJA1105_L2_ADDR_LUT_RECONFIG2 0x000025
94 #define SJA1105_L2_ADDR_LUT_RECONFIG3 0x000026
95 #define SJA1105_L2_ADDR_LUT_RECONFIG4 0x000027
96 #define SJA1105_L2_ADDR_LUT_RECONFIG5 0x000028
97 #define SJA1105_L2_ADDR_LUT_RECONFIG0 0x000029
98 #define SJA1105_L2_FWD_TABLE_RECONFIG1 0x00002A
99 #define SJA1105_L2_FWD_TABLE_RECONFIG2 0x00002B
100 #define SJA1105_L2_FWD_TABLE_RECONFIG0 0x00002C
101 #define SJA1105_VLAN_LUT_RECONFIG1 0x00002D
102 #define SJA1105_VLAN_LUT_RECONFIG2 0x00002E
103 #define SJA1105_VLAN_LUT_RECONFIG0 0x000030
104 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG1 0x000032
105 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG2 0x000033
106 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG3 0x000034
107 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG4 0x000035
108 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG5 0x000036
109 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG0 0x000037
110 #define SJA1105_RETAGGING_TABLE_RECONFIG1 0x000038
111 #define SJA1105_RETAGGING_TABLE_RECONFIG2 0x000039
112 #define SJA1105_RETAGGING_TABLE_RECONFIG0 0x00003A
113 #define SJA1105_GENERAL_PARAMS_RECONFIG1 0x00003B
114 #define SJA1105_GENERAL_PARAMS_RECONFIG2 0x00003C
115 #define SJA1105_GENERAL_PARAMS_RECONFIG3 0x00003D
116 #define SJA1105_GENERAL_PARAMS_RECONFIG4 0x00003E
117 #define SJA1105_GENERAL_PARAMS_RECONFIG5 0x00003F
118 #define SJA1105_GENERAL_PARAMS_RECONFIG6 0x000040
119 #define SJA1105_GENERAL_PARAMS_RECONFIG7 0x000041
120 #define SJA1105_GENERAL_PARAMS_RECONFIG8 0x000042
121 #define SJA1105_GENERAL_PARAMS_RECONFIG9 0x000043
122 #define SJA1105_GENERAL_PARAMS_RECONFIG10 0x000044
123 #define SJA1105_GENERAL_PARAMS_RECONFIG11 0x000045
124 #define SJA1105_GENERAL_PARAMS_RECONFIG0 0x000046
125 #define SJA1105_VL_LUT_RECONFIG1 0x000047
126 #define SJA1105_VL_LUT_RECONFIG2 0x000048
127 #define SJA1105_VL_LUT_RECONFIG3 0x000049
128 #define SJA1105_VL_LUT_RECONFIG0 0x00004A
129 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG1 0x00004B
130 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2 0x00004C
131 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG3 0x00004D
132 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4 0x00004E
133 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG5 0x00004F
134 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG6 0x000050
135 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG7 0x000051
136 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG8 0x000052
137 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG0 0x000053
138 #define SJA1105_L2_LOOKUP_PARAMS1 0x000054
139 #define SJA1105_L2_LOOKUP_PARAMS2 0x000055
140 #define SJA1105_L2_LOOKUP_PARAMS3 0x000056
141 #define SJA1105_L2_LOOKUP_PARAMS4 0x000057
142 #define SJA1105_L2_LOOKUP_PARAMS0 0x000058
143 #define SJA1105_SYNC_ENGINE_STATUS0 0x00005A
144 #define SJA1105_SYNC_ENGINE_STATUS1 0x00005B
145 #define SJA1105_SYNC_ENGINE_STATUS2 0x00005C
146 #define SJA1105_SYNC_ENGINE_STATUS3 0x00005D
147 #define SJA1105_SYNC_ENGINE_STATUS4 0x00005E
148 #define SJA1105_SYNC_ENGINE_STATUS5 0x00005F
149 #define SJA1105_SYNC_ENGINE_STATUS6 0x000060
150 #define SJA1105_SYNC_ENGINE_STATUS7 0x000061
151 #define SJA1105_SYNC_ENGINE_STATUS8 0x000062
152 #define SJA1105_SYNC_ENGINE_STATUS9 0x000063
153 #define SJA1105_SYNC_ENGINE_STATUS10 0x000064
154 #define SJA1105_SYNC_ENGINE_STATUS11 0x000065
155 #define SJA1105_SYNC_ENGINE_STATUS12 0x000066
156 #define SJA1105_SYNC_ENGINE_STATUS13 0x000067
157 #define SJA1105_SYNC_ENGINE_STATUS14 0x000068
158 #define SJA1105_SYNC_ENGINE_STATUS15 0x000069
159 #define SJA1105_SYNC_ENGINE_STATUS16 0x00006A
160 #define SJA1105_SYNC_ENGINE_STATUS17 0x00006B
161 #define SJA1105_SYNC_ENGINE_STATUS18 0x00006C
162 #define SJA1105_SYNC_ENGINE_STATUS19 0x00006D
163 #define SJA1105_SYNC_ENGINE_STATUS20 0x00006E
164 #define SJA1105_SYNC_ENGINE_STATUS21 0x00006F
165 #define SJA1105_SYNC_ENGINE_STATUS23 0x000070
166 #define SJA1105_SYNC_ENGINE_STATUS24 0x000071
167 #define SJA1105_VL_MEM_PARTI_STATUS0 0x000080
168 #define SJA1105_VL_MEM_PARTI_STATUS1 0x000081
169 #define SJA1105_VL_MEM_PARTI_STATUS2 0x000082
170 #define SJA1105_VL_MEM_PARTI_STATUS3 0x000083
171 #define SJA1105_VL_MEM_PARTI_STATUS4 0x000084
172 #define SJA1105_VL_MEM_PARTI_STATUS5 0x000085
173 #define SJA1105_VL_MEM_PARTI_STATUS6 0x000086
174 #define SJA1105_VL_MEM_PARTI_STATUS7 0x000087
175 #define SJA1105_PTP_TS0 0x0000C0
176 #define SJA1105_PTPEGR_TS0 0x0000C1
177 #define SJA1105_PTP_TS1 0x0000C2
178 #define SJA1105_PTPEGR_TS1 0x0000C3
179 #define SJA1105_PTP_TS2 0x0000C4
180 #define SJA1105_PTPEGR_TS2 0x0000C5
181 #define SJA1105_PTP_TS3 0x0000C6
182 #define SJA1105_PTPEGR_TS3 0x0000C7
183 #define SJA1105_PTP_TS4 0x0000C8
184 #define SJA1105_PTPEGR_TS4 0x0000C9
185 #define SJA1105_PTP_TS5 0x0000CA
186 #define SJA1105_PTPEGR_TS5 0x0000CB
187 #define SJA1105_PTP_TS6 0x0000CC
188 #define SJA1105_PTPEGR_TS6 0x0000CD
189 #define SJA1105_PTP_TS7 0x0000CE
190 #define SJA1105_PTPEGR_TS7 0x0000CF
191 #define SJA1105_PTP_TS8 0x0000D0
192 #define SJA1105_PTPEGR_TS8 0x0000D1
193 #define SJA1105_PTP_TS9 0x0000D2
194 #define SJA1105_PTPEGR_TS9 0x0000D3
195 #define SJA1105_L2_MEM_PART_STATUS0 0x000100
196 #define SJA1105_L2_MEM_PART_STATUS1 0x000101
197 #define SJA1105_L2_MEM_PART_STATUS2 0x000102
198 #define SJA1105_L2_MEM_PART_STATUS3 0x000103
199 #define SJA1105_L2_MEM_PART_STATUS4 0x000104
200 #define SJA1105_L2_MEM_PART_STATUS5 0x000105
201 #define SJA1105_L2_MEM_PART_STATUS6 0x000106
202 #define SJA1105_L2_MEM_PART_STATUS7 0x000107
203 #define SJA1105_PORT0_MAC_DIAG_CNT 0x000200
204 #define SJA1105_PORT0_MAC_DIAG_FLAGS 0x000201
205 #define SJA1105_PORT1_MAC_DIAG_CNT 0x000202
206 #define SJA1105_PORT1_MAC_DIAG_FLAGS 0x000203
207 #define SJA1105_PORT2_MAC_DIAG_CNT 0x000204
208 #define SJA1105_PORT2_MAC_DIAG_FLAGS 0x000205
209 #define SJA1105_PORT3_MAC_DIAG_CNT 0x000206
210 #define SJA1105_PORT3_MAC_DIAG_FLAGS 0x000207
211 #define SJA1105_PORT4_MAC_DIAG_CNT 0x000208
212 #define SJA1105_PORT4_MAC_DIAG_FLAGS 0x000209
213 #define SJA1105_PORT0_N_TXBYTE 0x000400
214 #define SJA1105_PORT0_N_TXBYTESH 0x000401
215 #define SJA1105_PORT0_N_TXFRM 0x000402
216 #define SJA1105_PORT0_N_TXFRMSH 0x000403
217 #define SJA1105_PORT0_N_RXBYTE 0x000404
218 #define SJA1105_PORT0_N_RXBYTESH 0x000405
219 #define SJA1105_PORT0_N_RXFRM 0x000406
220 #define SJA1105_PORT0_N_RXFRMSH 0x000407
221 #define SJA1105_PORT0_N_POLERR 0x000408
222 #define SJA1105_PORT0_N_CTPOLERR 0x000409
223 #define SJA1105_PORT0_N_VLNOTFOUND 0x00040A
224 #define SJA1105_PORT0_N_CRCERR 0x00040B
225 #define SJA1105_PORT0_N_SIZEERR 0x00040C
226 #define SJA1105_PORT0_N_UNRELEASED 0x00040D
227 #define SJA1105_PORT0_N_VLANERR 0x00040E
228 #define SJA1105_PORT0_N_N664ERR 0x00040F
229 #define SJA1105_PORT1_N_TXBYTE 0x000410
230 #define SJA1105_PORT1_N_TXBYTESH 0x000411
231 #define SJA1105_PORT1_N_TXFRM 0x000412
232 #define SJA1105_PORT1_N_TXFRMSH 0x000413
233 #define SJA1105_PORT1_N_RXBYTE 0x000414
234 #define SJA1105_PORT1_N_RXBYTESH 0x000415
235 #define SJA1105_PORT1_N_RXFRM 0x000416
236 #define SJA1105_PORT1_N_RXFRMSH 0x000417
237 #define SJA1105_PORT1_N_POLERR 0x000418
238 #define SJA1105_PORT1_N_CTPOLERR 0x000419
239 #define SJA1105_PORT1_N_VLNOTFOUND 0x00041A
240 #define SJA1105_PORT1_N_CRCERR 0x00041B
241 #define SJA1105_PORT1_N_SIZEERR 0x00041C
242 #define SJA1105_PORT1_N_UNRELEASED 0x00041D
243 #define SJA1105_PORT1_N_VLANERR 0x00041E
244 #define SJA1105_PORT1_N_N664ERR 0x00041F
245 #define SJA1105_PORT2_N_TXBYTE 0x000420
246 #define SJA1105_PORT2_N_TXBYTESH 0x000421
247 #define SJA1105_PORT2_N_TXFRM 0x000422
248 #define SJA1105_PORT2_N_TXFRMSH 0x000423
249 #define SJA1105_PORT2_N_RXBYTE 0x000424
250 #define SJA1105_PORT2_N_RXBYTESH 0x000425
251 #define SJA1105_PORT2_N_RXFRM 0x000426
252 #define SJA1105_PORT2_N_RXFRMSH 0x000427
253 #define SJA1105_PORT2_N_POLERR 0x000428
254 #define SJA1105_PORT2_N_CTPOLERR 0x000429
255 #define SJA1105_PORT2_N_VLNOTFOUND 0x00042A
256 #define SJA1105_PORT2_N_CRCERR 0x00042B
257 #define SJA1105_PORT2_N_SIZEERR 0x00042C
258 #define SJA1105_PORT2_N_UNRELEASED 0x00042D
259 #define SJA1105_PORT2_N_VLANERR 0x00042E
260 #define SJA1105_PORT2_N_N664ERR 0x00042F
261 #define SJA1105_PORT3_N_TXBYTE 0x000430
262 #define SJA1105_PORT3_N_TXBYTESH 0x000431
263 #define SJA1105_PORT3_N_TXFRM 0x000432
264 #define SJA1105_PORT3_N_TXFRMSH 0x000433
265 #define SJA1105_PORT3_N_RXBYTE 0x000434
266 #define SJA1105_PORT3_N_RXBYTESH 0x000435
267 #define SJA1105_PORT3_N_RXFRM 0x000436
268 #define SJA1105_PORT3_N_RXFRMSH 0x000437
269 #define SJA1105_PORT3_N_POLERR 0x000438
270 #define SJA1105_PORT3_N_CTPOLERR 0x000439
271 #define SJA1105_PORT3_N_VLNOTFOUND 0x00043A
272 #define SJA1105_PORT3_N_CRCERR 0x00043B
273 #define SJA1105_PORT3_N_SIZEERR 0x00043C
274 #define SJA1105_PORT3_N_UNRELEASED 0x00043D
275 #define SJA1105_PORT3_N_VLANERR 0x00043E
276 #define SJA1105_PORT3_N_N664ERR 0x00043F
277 #define SJA1105_PORT4_N_TXBYTE 0x000440
278 #define SJA1105_PORT4_N_TXBYTESH 0x000441
279 #define SJA1105_PORT4_N_TXFRM 0x000442
280 #define SJA1105_PORT4_N_TXFRMSH 0x000443
281 #define SJA1105_PORT4_N_RXBYTE 0x000444
282 #define SJA1105_PORT4_N_RXBYTESH 0x000445
283 #define SJA1105_PORT4_N_RXFRM 0x000446
284 #define SJA1105_PORT4_N_RXFRMSH 0x000447
285 #define SJA1105_PORT4_N_POLERR 0x000448
286 #define SJA1105_PORT4_N_CTPOLERR 0x000449
287 #define SJA1105_PORT4_N_VLNOTFOUND 0x00044A
288 #define SJA1105_PORT4_N_CRCERR 0x00044B
289 #define SJA1105_PORT4_N_SIZEERR 0x00044C
290 #define SJA1105_PORT4_N_UNRELEASED 0x00044D
291 #define SJA1105_PORT4_N_VLANERR 0x00044E
292 #define SJA1105_PORT4_N_N664ERR 0x00044F
293 #define SJA1105_PORT0_N_NOT_REACH 0x000600
294 #define SJA1105_PORT0_N_EGR_DISABLED 0x000601
295 #define SJA1105_PORT0_N_PART_DROP 0x000602
296 #define SJA1105_PORT0_N_QFULL 0x000603
297 #define SJA1105_PORT0_QLEVEL0 0x000604
298 #define SJA1105_PORT0_QLEVEL1 0x000605
299 #define SJA1105_PORT0_QLEVEL2 0x000606
300 #define SJA1105_PORT0_QLEVEL3 0x000607
301 #define SJA1105_PORT0_QLEVEL4 0x000608
302 #define SJA1105_PORT0_QLEVEL5 0x000609
303 #define SJA1105_PORT0_QLEVEL6 0x00060A
304 #define SJA1105_PORT0_QLEVEL7 0x00060B
305 #define SJA1105_PORT1_N_NOT_REACH 0x000610
306 #define SJA1105_PORT1_N_EGR_DISABLED 0x000611
307 #define SJA1105_PORT1_N_PART_DROP 0x000612
308 #define SJA1105_PORT1_N_QFULL 0x000613
309 #define SJA1105_PORT1_QLEVEL0 0x000614
310 #define SJA1105_PORT1_QLEVEL1 0x000615
311 #define SJA1105_PORT1_QLEVEL2 0x000616
312 #define SJA1105_PORT1_QLEVEL3 0x000617
313 #define SJA1105_PORT1_QLEVEL4 0x000618
314 #define SJA1105_PORT1_QLEVEL5 0x000619
315 #define SJA1105_PORT1_QLEVEL6 0x00061A
316 #define SJA1105_PORT1_QLEVEL7 0x00061B
317 #define SJA1105_PORT2_N_NOT_REACH 0x000620
318 #define SJA1105_PORT2_N_EGR_DISABLED 0x000621
319 #define SJA1105_PORT2_N_PART_DROP 0x000622
320 #define SJA1105_PORT2_N_QFULL 0x000623
321 #define SJA1105_PORT2_QLEVEL0 0x000624
322 #define SJA1105_PORT2_QLEVEL1 0x000625
323 #define SJA1105_PORT2_QLEVEL2 0x000626
324 #define SJA1105_PORT2_QLEVEL3 0x000627
325 #define SJA1105_PORT2_QLEVEL4 0x000628
326 #define SJA1105_PORT2_QLEVEL5 0x000629
327 #define SJA1105_PORT2_QLEVEL6 0x00062A
328 #define SJA1105_PORT2_QLEVEL7 0x00062B
329 #define SJA1105_PORT3_N_NOT_REACH 0x000630
330 #define SJA1105_PORT3_N_EGR_DISABLED 0x000631
331 #define SJA1105_PORT3_N_PART_DROP 0x000632
332 #define SJA1105_PORT3_N_QFULL 0x000633
333 #define SJA1105_PORT3_QLEVEL0 0x000634
334 #define SJA1105_PORT3_QLEVEL1 0x000635
335 #define SJA1105_PORT3_QLEVEL2 0x000636
336 #define SJA1105_PORT3_QLEVEL3 0x000637
337 #define SJA1105_PORT3_QLEVEL4 0x000638
338 #define SJA1105_PORT3_QLEVEL5 0x000639
339 #define SJA1105_PORT3_QLEVEL6 0x00063A
340 #define SJA1105_PORT3_QLEVEL7 0x00063B
341 #define SJA1105_PORT4_N_NOT_REACH 0x000640
342 #define SJA1105_PORT4_N_EGR_DISABLED 0x000641
343 #define SJA1105_PORT4_N_PART_DROP 0x000642
344 #define SJA1105_PORT4_N_QFULL 0x000643
345 #define SJA1105_PORT4_QLEVEL0 0x000644
346 #define SJA1105_PORT4_QLEVEL1 0x000645
347 #define SJA1105_PORT4_QLEVEL2 0x000646
348 #define SJA1105_PORT4_QLEVEL3 0x000647
349 #define SJA1105_PORT4_QLEVEL4 0x000648
350 #define SJA1105_PORT4_QLEVEL5 0x000649
351 #define SJA1105_PORT4_QLEVEL6 0x00064A
352 #define SJA1105_PORT4_QLEVEL7 0x00064B
353 #define SJA1105_VL_MEM_PART_ERR_CNT0 0x000800
354 #define SJA1105_VL_MEM_PART_ERR_CNT1 0x000801
355 #define SJA1105_VL_MEM_PART_ERR_CNT2 0x000802
356 #define SJA1105_VL_MEM_PART_ERR_CNT3 0x000803
357 #define SJA1105_VL_MEM_PART_ERR_CNT4 0x000804
358 #define SJA1105_VL_MEM_PART_ERR_CNT5 0x000805
359 #define SJA1105_VL_MEM_PART_ERR_CNT6 0x000806
360 #define SJA1105_VL_MEM_PART_ERR_CNT7 0x000807
361 #define SJA1105_L2_MEM_PART_ERR_CNT0 0x001000
362 #define SJA1105_L2_MEM_PART_ERR_CNT1 0x001001
363 #define SJA1105_L2_MEM_PART_ERR_CNT2 0x001002
364 #define SJA1105_L2_MEM_PART_ERR_CNT3 0x001003
365 #define SJA1105_L2_MEM_PART_ERR_CNT4 0x001004
366 #define SJA1105_L2_MEM_PART_ERR_CNT5 0x001005
367 #define SJA1105_L2_MEM_PART_ERR_CNT6 0x001006
368 #define SJA1105_L2_MEM_PART_ERR_CNT7 0x001007
369 #define SJA1105_PORT0_N_RX_BCAST 0x001400
370 #define SJA1105_PORT0_N_RX_MCAST 0x001401
371 #define SJA1105_PORT0_N_RX_BYTES_64 0x001402
372 #define SJA1105_PORT0_N_RX_BYTES_65_127 0x001403
373 #define SJA1105_PORT0_N_RX_BYTES_128_255 0x001404
374 #define SJA1105_PORT0_N_RX_BYTES_256_511 0x001405
375 #define SJA1105_PORT0_N_RX_BYTES_512_1023 0x001406
376 #define SJA1105_PORT0_N_RX_BYTES_1024_1518 0x001407
377 #define SJA1105_PORT0_N_TX_BCAST 0x001408
378 #define SJA1105_PORT0_N_TX_MCAST 0x001409
379 #define SJA1105_PORT0_N_TX_BYTES_64 0x00140A
380 #define SJA1105_PORT0_N_TX_BYTES_65_127 0x00140B
381 #define SJA1105_PORT0_N_TX_BYTES_128_255 0x00140C
382 #define SJA1105_PORT0_N_TX_BYTES_256_511 0x00140D
383 #define SJA1105_PORT0_N_TX_BYTES_512_1023 0x00140E
384 #define SJA1105_PORT0_N_TX_BYTES_1024_1518 0x00140F
385 #define SJA1105_PORT0_N_DROPS_UTAG 0x001410
386 #define SJA1105_PORT0_N_DROPS_SITAG 0x001411
387 #define SJA1105_PORT0_N_DROPS_SOTAG 0x001412
388 #define SJA1105_PORT0_N_DROPS_DTAG 0x001413
389 #define SJA1105_PORT0_N_DROPS_ILL_DTAG 0x001414
390 #define SJA1105_PORT0_N_DROPS_EMPTY_ROUTE 0x001415
391 #define SJA1105_PORT0_N_DROPS_NOLEARN 0x001416
392 #define SJA1105_PORT1_N_RX_BCAST 0x001418
393 #define SJA1105_PORT1_N_RX_MCAST 0x001419
394 #define SJA1105_PORT1_N_RX_BYTES_64 0x00141A
395 #define SJA1105_PORT1_N_RX_BYTES_65_127 0x00141B
396 #define SJA1105_PORT1_N_RX_BYTES_128_255 0x00141C
397 #define SJA1105_PORT1_N_RX_BYTES_256_511 0x00141D
398 #define SJA1105_PORT1_N_RX_BYTES_512_1023 0x00141E
399 #define SJA1105_PORT1_N_RX_BYTES_1024_1518 0x00141F
400 #define SJA1105_PORT1_N_TX_BCAST 0x001420
401 #define SJA1105_PORT1_N_TX_MCAST 0x001421
402 #define SJA1105_PORT1_N_TX_BYTES_64 0x001422
403 #define SJA1105_PORT1_N_TX_BYTES_65_127 0x001423
404 #define SJA1105_PORT1_N_TX_BYTES_128_255 0x001424
405 #define SJA1105_PORT1_N_TX_BYTES_256_511 0x001425
406 #define SJA1105_PORT1_N_TX_BYTES_512_1023 0x001426
407 #define SJA1105_PORT1_N_TX_BYTES_1024_1518 0x001427
408 #define SJA1105_PORT1_N_DROPS_UTAG 0x001428
409 #define SJA1105_PORT1_N_DROPS_SITAG 0x001429
410 #define SJA1105_PORT1_N_DROPS_SOTAG 0x00142A
411 #define SJA1105_PORT1_N_DROPS_DTAG 0x00142B
412 #define SJA1105_PORT1_N_DROPS_ILL_DTAG 0x00142C
413 #define SJA1105_PORT1_N_DROPS_EMPTY_ROUTE 0x00142D
414 #define SJA1105_PORT1_N_DROPS_NOLEARN 0x00142E
415 #define SJA1105_PORT2_N_RX_BCAST 0x001430
416 #define SJA1105_PORT2_N_RX_MCAST 0x001431
417 #define SJA1105_PORT2_N_RX_BYTES_64 0x001432
418 #define SJA1105_PORT2_N_RX_BYTES_65_127 0x001433
419 #define SJA1105_PORT2_N_RX_BYTES_128_255 0x001434
420 #define SJA1105_PORT2_N_RX_BYTES_256_511 0x001435
421 #define SJA1105_PORT2_N_RX_BYTES_512_1023 0x001436
422 #define SJA1105_PORT2_N_RX_BYTES_1024_1518 0x001437
423 #define SJA1105_PORT2_N_TX_BCAST 0x001438
424 #define SJA1105_PORT2_N_TX_MCAST 0x001439
425 #define SJA1105_PORT2_N_TX_BYTES_64 0x00143A
426 #define SJA1105_PORT2_N_TX_BYTES_65_127 0x00143B
427 #define SJA1105_PORT2_N_TX_BYTES_128_255 0x00143C
428 #define SJA1105_PORT2_N_TX_BYTES_256_511 0x00143D
429 #define SJA1105_PORT2_N_TX_BYTES_512_1023 0x00143E
430 #define SJA1105_PORT2_N_TX_BYTES_1024_1518 0x00143F
431 #define SJA1105_PORT2_N_DROPS_UTAG 0x001440
432 #define SJA1105_PORT2_N_DROPS_SITAG 0x001441
433 #define SJA1105_PORT2_N_DROPS_SOTAG 0x001442
434 #define SJA1105_PORT2_N_DROPS_DTAG 0x001443
435 #define SJA1105_PORT2_N_DROPS_ILL_DTAG 0x001444
436 #define SJA1105_PORT2_N_DROPS_EMPTY_ROUTE 0x001445
437 #define SJA1105_PORT2_N_DROPS_NOLEARN 0x001446
438 #define SJA1105_PORT3_N_RX_BCAST 0x001448
439 #define SJA1105_PORT3_N_RX_MCAST 0x001449
440 #define SJA1105_PORT3_N_RX_BYTES_64 0x00144A
441 #define SJA1105_PORT3_N_RX_BYTES_65_127 0x00144B
442 #define SJA1105_PORT3_N_RX_BYTES_128_255 0x00144C
443 #define SJA1105_PORT3_N_RX_BYTES_256_511 0x00144D
444 #define SJA1105_PORT3_N_RX_BYTES_512_1023 0x00144E
445 #define SJA1105_PORT3_N_RX_BYTES_1024_1518 0x00144F
446 #define SJA1105_PORT3_N_TX_BCAST 0x001450
447 #define SJA1105_PORT3_N_TX_MCAST 0x001451
448 #define SJA1105_PORT3_N_TX_BYTES_64 0x001452
449 #define SJA1105_PORT3_N_TX_BYTES_65_127 0x001453
450 #define SJA1105_PORT3_N_TX_BYTES_128_255 0x001454
451 #define SJA1105_PORT3_N_TX_BYTES_256_511 0x001455
452 #define SJA1105_PORT3_N_TX_BYTES_512_1023 0x001456
453 #define SJA1105_PORT3_N_TX_BYTES_1024_1518 0x001457
454 #define SJA1105_PORT3_N_DROPS_UTAG 0x001458
455 #define SJA1105_PORT3_N_DROPS_SITAG 0x001459
456 #define SJA1105_PORT3_N_DROPS_SOTAG 0x00145A
457 #define SJA1105_PORT3_N_DROPS_DTAG 0x00145B
458 #define SJA1105_PORT3_N_DROPS_ILL_DTAG 0x00145C
459 #define SJA1105_PORT3_N_DROPS_EMPTY_ROUTE 0x00145D
460 #define SJA1105_PORT3_N_DROPS_NOLEARN 0x00145E
461 #define SJA1105_PORT4_N_RX_BCAST 0x001460
462 #define SJA1105_PORT4_N_RX_MCAST 0x001461
463 #define SJA1105_PORT4_N_RX_BYTES_64 0x001462
464 #define SJA1105_PORT4_N_RX_BYTES_65_127 0x001463
465 #define SJA1105_PORT4_N_RX_BYTES_128_255 0x001464
466 #define SJA1105_PORT4_N_RX_BYTES_256_511 0x001465
467 #define SJA1105_PORT4_N_RX_BYTES_512_1023 0x001466
468 #define SJA1105_PORT4_N_RX_BYTES_1024_1518 0x001467
469 #define SJA1105_PORT4_N_TX_BCAST 0x001468
470 #define SJA1105_PORT4_N_TX_MCAST 0x001469
471 #define SJA1105_PORT4_N_TX_BYTES_64 0x00146A
472 #define SJA1105_PORT4_N_TX_BYTES_65_127 0x00146B
473 #define SJA1105_PORT4_N_TX_BYTES_128_255 0x00146C
474 #define SJA1105_PORT4_N_TX_BYTES_256_511 0x00146D
475 #define SJA1105_PORT4_N_TX_BYTES_512_1023 0x00146E
476 #define SJA1105_PORT4_N_TX_BYTES_1024_1518 0x00146F
477 #define SJA1105_PORT4_N_DROPS_UTAG 0x001470
478 #define SJA1105_PORT4_N_DROPS_SITAG 0x001471
479 #define SJA1105_PORT4_N_DROPS_SOTAG 0x001472
480 #define SJA1105_PORT4_N_DROPS_DTAG 0x001473
481 #define SJA1105_PORT4_N_DROPS_ILL_DTAG 0x001474
482 #define SJA1105_PORT4_N_DROPS_EMPTY_ROUTE 0x001475
483 #define SJA1105_PORT4_N_DROPS_NOLEARN 0x001476
484 #define SJA1105_L2_FWD_PARAMS_RECONFIG0 0x008000
485 #define SJA1105_L2_FWD_PARAMS_RECONFIG1 0x008001
486 #define SJA1105_L2_FWD_PARAMS_RECONFIG2 0x008002
487 #define SJA1105_AVB_PARAMS_RECONFIG1 0x008003
488 #define SJA1105_AVB_PARAMS_RECONFIG2 0x008004
489 #define SJA1105_AVB_PARAMS_RECONFIG3 0x008005
490 #define SJA1105_AVB_PARAMS_RECONFIG4 0x008006
491 #define SJA1105_AVB_PARAMS_RECONFIG0 0x008007
492 #define SJA1105_VIRTUAL_LINK_STATUS0 0x010000
493 #define SJA1105_VIRTUAL_LINK_STATUS1 0x010001
494 #define SJA1105_RFRQ 0x100005
495 #define SJA1105_XO66M_0_C 0x100006
496 #define SJA1105_PLL_0_S 0x100007
497 #define SJA1105_PLL_0_C 0x100008
498 #define SJA1105_PLL_1_S 0x100009
499 #define SJA1105_PLL_1_C 0x10000A
500 #define SJA1105_IDIV_0_C 0x10000B
501 #define SJA1105_IDIV_1_C 0x10000C
502 #define SJA1105_IDIV_2_C 0x10000D
503 #define SJA1105_IDIV_3_C 0x10000E
504 #define SJA1105_IDIV_4_C 0x10000F
505 #define SJA1105_MII_TX_CLK_0 0x100013
506 #define SJA1105_MII_RX_CLK_0 0x100014
507 #define SJA1105_RMII_REF_CLK_0 0x100015
508 #define SJA1105_RGMII_TX_CLK_0 0x100016
509 #define SJA1105_EXT_TX_CLK_0 0x100017
510 #define SJA1105_EXT_RX_CLK_0 0x100018
511 #define SJA1105_MII_TX_CLK_1 0x100019
512 #define SJA1105_MII_RX_CLK_1 0x10001A
513 #define SJA1105_RMII_REF_CLK_1 0x10001B
514 #define SJA1105_RGMII_TX_CLK_1 0x10001C
515 #define SJA1105_EXT_TX_CLK_1 0x10001D
516 #define SJA1105_EXT_RX_CLK_1 0x10001E
517 #define SJA1105_MII_TX_CLK_2 0x10001F
518 #define SJA1105_MII_RX_CLK_2 0x100020
519 #define SJA1105_RMII_REF_CLK_2 0x100021
520 #define SJA1105_RGMII_TX_CLK_2 0x100022
521 #define SJA1105_EXT_TX_CLK_2 0x100023
522 #define SJA1105_EXT_RX_CLK_2 0x100024
523 #define SJA1105_MII_TX_CLK_3 0x100025
524 #define SJA1105_MII_RX_CLK_3 0x100026
525 #define SJA1105_RMII_REF_CLK_3 0x100027
526 #define SJA1105_RGMII_TX_CLK_3 0x100028
527 #define SJA1105_EXT_TX_CLK_3 0x100029
528 #define SJA1105_EXT_RX_CLK_3 0x10002A
529 #define SJA1105_MII_TX_CLK_4 0x10002B
530 #define SJA1105_MII_RX_CLK_4 0x10002C
531 #define SJA1105_RMII_REF_CLK_4 0x10002D
532 #define SJA1105_RGMII_TX_CLK_4 0x10002E
533 #define SJA1105_EXT_TX_CLK_4 0x10002F
534 #define SJA1105_EXT_RX_CLK_4 0x100030
535 #define SJA1105_RESET_CTRL 0x100440
536 #define SJA1105_RGU_UNIT_DISABLE 0x1007FD
537 #define SJA1105_CFG_PAD_MII0_TX 0x100800
538 #define SJA1105_CFG_PAD_MII0_RX 0x100801
539 #define SJA1105_CFG_PAD_MII1_TX 0x100802
540 #define SJA1105_CFG_PAD_MII1_RX 0x100803
541 #define SJA1105_CFG_PAD_MII2_TX 0x100804
542 #define SJA1105_CFG_PAD_MII2_RX 0x100805
543 #define SJA1105_CFG_PAD_MII3_TX 0x100806
544 #define SJA1105_CFG_PAD_MII3_RX 0x100807
545 #define SJA1105_CFG_PAD_MII4_TX 0x100808
546 #define SJA1105_CFG_PAD_MII4_RX 0x100809
547 #define SJA1105_CFG_PAD_MII0_ID 0x100810
548 #define SJA1105_CFG_PAD_MII1_ID 0x100811
549 #define SJA1105_CFG_PAD_MII2_ID 0x100812
550 #define SJA1105_CFG_PAD_MII3_ID 0x100813
551 #define SJA1105_CFG_PAD_MII4_ID 0x100814
552 #define SJA1105_CFG_PAD_MISC 0x100840
553 #define SJA1105_CFG_PAD_SPI 0x100880
554 #define SJA1105_CFG_PAD_JTAG 0x100881
555 #define SJA1105_PORT_STATUS_MII0 0x100900
556 #define SJA1105_PORT_STATUS_MII1 0x100901
557 #define SJA1105_PORT_STATUS_MII2 0x100902
558 #define SJA1105_PORT_STATUS_MII3 0x100903
559 #define SJA1105_PORT_STATUS_MII4 0x100904
560 #define SJA1105_TS_CONFIG 0x100A00
561 #define SJA1105_TS_STATUS 0x100A01
562 #define SJA1105_PROD_CFG 0x100BC0
563 #define SJA1105_PROD_ID 0x100BC3
564 #define SJA1105_ACU_UNIT_DISABLE 0x100BFD
565 #define SJA1105_BASIC_CONTROL 0x1F0000
566 #define SJA1105_BASIC_STATUS 0x1F0001
567 #define SJA1105_PHY_IDENTIFIER_1 0x1F0002
568 #define SJA1105_PHY_IDENTIFIER_2 0x1F0003
569 #define SJA1105_AUTONEG_ADV 0x1F0004
570 #define SJA1105_AUTONEG_LP_BABL 0x1F0005
571 #define SJA1105_AUTONEG_EXPN 0x1F0006
572 #define SJA1105_EXTENDED_STATUS 0x1F000F
573 #define SJA1105_DIGITAL_CONTROL_1 0x1F8000
574 #define SJA1105_AUTONEG_CONTROL 0x1F8001
575 #define SJA1105_AUTONEG_INTR_STATUS 0x1F8002
576 #define SJA1105_TEST_CONTROL 0x1F8003
577 #define SJA1105_DEBUG_CONTROL 0x1F8005
578 #define SJA1105_DIGITAL_STATUS 0x1F8010
579 #define SJA1105_ICG_ERROR_CNT 0x1F8011
580 #define SJA1105_TX_BOOST_CONTROL 0x1F8030
581 #define SJA1105_TX_ATTN_CONTROL 0x1F8031
582 #define SJA1105_TX_EDGE_CONTROL 0x1F8033
583 #define SJA1105_RX_EQ_CONTROL 0x1F8051
584 #define SJA1105_LEVEL_CONTROL 0x1F8090
585 #define SJA1105_DIGITAL_CONTROL_2 0x1F80E1
586 #define SJA1105_DIGITAL_ERROR_CNT 0x1F80E2
587 
588 //SJA1105 SPI register access macros
589 #define SJA1105_PORTn_MAC_DIAG_CNT(port) (0x000200 + ((port) * 0x000002))
590 #define SJA1105_PORTn_MAC_DIAG_FLAGS(port) (0x000201 + ((port) * 0x000002))
591 #define SJA1105_PORTn_N_TXBYTE(port) (0x000400 + ((port) * 0x000010))
592 #define SJA1105_PORTn_N_TXBYTESH(port) (0x000401 + ((port) * 0x000010))
593 #define SJA1105_PORTn_N_TXFRM(port) (0x000402 + ((port) * 0x000010))
594 #define SJA1105_PORTn_N_TXFRMSH(port) (0x000403 + ((port) * 0x000010))
595 #define SJA1105_PORTn_N_RXBYTE(port) (0x000404 + ((port) * 0x000010))
596 #define SJA1105_PORTn_N_RXBYTESH(port) (0x000405 + ((port) * 0x000010))
597 #define SJA1105_PORTn_N_RXFRM(port) (0x000406 + ((port) * 0x000010))
598 #define SJA1105_PORTn_N_RXFRMSH(port) (0x000407 + ((port) * 0x000010))
599 #define SJA1105_PORTn_N_POLERR(port) (0x000408 + ((port) * 0x000010))
600 #define SJA1105_PORTn_N_CTPOLERR(port) (0x000409 + ((port) * 0x000010))
601 #define SJA1105_PORTn_N_VLNOTFOUND(port) (0x00040A + ((port) * 0x000010))
602 #define SJA1105_PORTn_N_CRCERR(port) (0x00040B + ((port) * 0x000010))
603 #define SJA1105_PORTn_N_SIZEERR(port) (0x00040C + ((port) * 0x000010))
604 #define SJA1105_PORTn_N_UNRELEASED(port) (0x00040D + ((port) * 0x000010))
605 #define SJA1105_PORTn_N_VLANERR(port) (0x00040E + ((port) * 0x000010))
606 #define SJA1105_PORTn_N_N664ERR(port) (0x00040F + ((port) * 0x000010))
607 #define SJA1105_PORTn_N_NOT_REACH(port) (0x000600 + ((port) * 0x000010))
608 #define SJA1105_PORTn_N_EGR_DISABLED(port) (0x000601 + ((port) * 0x000010))
609 #define SJA1105_PORTn_N_PART_DROP(port) (0x000602 + ((port) * 0x000010))
610 #define SJA1105_PORTn_N_QFULL(port) (0x000603 + ((port) * 0x000010))
611 #define SJA1105_PORTn_QLEVEL0(port) (0x000604 + ((port) * 0x000010))
612 #define SJA1105_PORTn_QLEVEL1(port) (0x000605 + ((port) * 0x000010))
613 #define SJA1105_PORTn_QLEVEL2(port) (0x000606 + ((port) * 0x000010))
614 #define SJA1105_PORTn_QLEVEL3(port) (0x000607 + ((port) * 0x000010))
615 #define SJA1105_PORTn_QLEVEL4(port) (0x000608 + ((port) * 0x000010))
616 #define SJA1105_PORTn_QLEVEL5(port) (0x000609 + ((port) * 0x000010))
617 #define SJA1105_PORTn_QLEVEL6(port) (0x00060A + ((port) * 0x000010))
618 #define SJA1105_PORTn_QLEVEL7(port) (0x00060B + ((port) * 0x000010))
619 #define SJA1105_PORTn_N_RX_BCAST(port) (0x001400 + ((port) * 0x000018))
620 #define SJA1105_PORTn_N_RX_MCAST(port) (0x001401 + ((port) * 0x000018))
621 #define SJA1105_PORTn_N_RX_BYTES_64(port) (0x001402 + ((port) * 0x000018))
622 #define SJA1105_PORTn_N_RX_BYTES_65_127(port) (0x001403 + ((port) * 0x000018))
623 #define SJA1105_PORTn_N_RX_BYTES_128_255(port) (0x001404 + ((port) * 0x000018))
624 #define SJA1105_PORTn_N_RX_BYTES_256_511(port) (0x001405 + ((port) * 0x000018))
625 #define SJA1105_PORTn_N_RX_BYTES_512_1023(port) (0x001406 + ((port) * 0x000018))
626 #define SJA1105_PORTn_N_RX_BYTES_1024_1518(port) (0x001407 + ((port) * 0x000018))
627 #define SJA1105_PORTn_N_TX_BCAST(port) (0x001408 + ((port) * 0x000018))
628 #define SJA1105_PORTn_N_TX_MCAST(port) (0x001409 + ((port) * 0x000018))
629 #define SJA1105_PORTn_N_TX_BYTES_64(port) (0x00140A + ((port) * 0x000018))
630 #define SJA1105_PORTn_N_TX_BYTES_65_127(port) (0x00140B + ((port) * 0x000018))
631 #define SJA1105_PORTn_N_TX_BYTES_128_255(port) (0x00140C + ((port) * 0x000018))
632 #define SJA1105_PORTn_N_TX_BYTES_256_511(port) (0x00140D + ((port) * 0x000018))
633 #define SJA1105_PORTn_N_TX_BYTES_512_1023(port) (0x00140E + ((port) * 0x000018))
634 #define SJA1105_PORTn_N_TX_BYTES_1024_1518(port) (0x00140F + ((port) * 0x000018))
635 #define SJA1105_PORTn_N_DROPS_UTAG(port) (0x001410 + ((port) * 0x000018))
636 #define SJA1105_PORTn_N_DROPS_SITAG(port) (0x001411 + ((port) * 0x000018))
637 #define SJA1105_PORTn_N_DROPS_SOTAG(port) (0x001412 + ((port) * 0x000018))
638 #define SJA1105_PORTn_N_DROPS_DTAG(port) (0x001413 + ((port) * 0x000018))
639 #define SJA1105_PORTn_N_DROPS_ILL_DTAG(port) (0x001414 + ((port) * 0x000018))
640 #define SJA1105_PORTn_N_DROPS_EMPTY_ROUTE(port) (0x001415 + ((port) * 0x000018))
641 #define SJA1105_PORTn_N_DROPS_NOLEARN(port) (0x001416 + ((port) * 0x000018))
642 #define SJA1105_IDIV_x_C(port) (0x10000B + ((port) * 0x000001))
643 #define SJA1105_MII_TX_CLK_x(port) (0x100013 + ((port) * 0x000006))
644 #define SJA1105_MII_RX_CLK_x(port) (0x100014 + ((port) * 0x000006))
645 #define SJA1105_RMII_REF_CLK_x(port) (0x100015 + ((port) * 0x000006))
646 #define SJA1105_RGMII_TX_CLK_x(port) (0x100016 + ((port) * 0x000006))
647 #define SJA1105_EXT_TX_CLK_x(port) (0x100017 + ((port) * 0x000006))
648 #define SJA1105_EXT_RX_CLK_x(port) (0x100018 + ((port) * 0x000006))
649 #define SJA1105_CFG_PAD_MIIx_TX(port) (0x100800 + ((port) * 0x000002))
650 #define SJA1105_CFG_PAD_MIIx_RX(port) (0x100801 + ((port) * 0x000002))
651 #define SJA1105_CFG_PAD_MIIx_ID(port) (0x100810 + ((port) * 0x000001))
652 #define SJA1105_PORT_STATUS_MIIx(port) (0x100900 + ((port) * 0x000001))
653 
654 //Device ID register
655 #define SJA1105_DEVICE_ID_SJA1105PEL 0xAF00030E
656 #define SJA1105_DEVICE_ID_SJA1105QEL 0xAE00030E
657 #define SJA1105_DEVICE_ID_SJA1105REL 0xAF00030E
658 #define SJA1105_DEVICE_ID_SJA1105SEL 0xAE00030E
659 
660 //Initial Device Configuration Flag register
661 #define SJA1105_INIT_DEV_CONFIG_FLAG_CONFIGS 0x80000000
662 #define SJA1105_INIT_DEV_CONFIG_FLAG_CRCCHKL 0x40000000
663 #define SJA1105_INIT_DEV_CONFIG_FLAG_IDS 0x20000000
664 #define SJA1105_INIT_DEV_CONFIG_FLAG_CRCCHKG 0x10000000
665 #define SJA1105_INIT_DEV_CONFIG_FLAG_NSLOT 0x0000000F
666 
667 //VL Route/Partition Status register
668 #define SJA1105_VL_ROUTE_PARTITION_STATUS_VLIND 0xFFFF0000
669 #define SJA1105_VL_ROUTE_PARTITION_STATUS_VLPARIND 0x0000FF00
670 #define SJA1105_VL_ROUTE_PARTITION_STATUS_VLROUTES 0x00000002
671 #define SJA1105_VL_ROUTE_PARTITION_STATUS_VLPARTS 0x00000001
672 
673 //General Status 1 register
674 #define SJA1105_GENERAL_STATUS1_MACADDRL 0xFFFF0000
675 #define SJA1105_GENERAL_STATUS1_PORTENF 0x0000FF00
676 #define SJA1105_GENERAL_STATUS1_FWDS 0x00000010
677 #define SJA1105_GENERAL_STATUS1_MACFDS 0x00000008
678 #define SJA1105_GENERAL_STATUS1_ENFFDS 0x00000004
679 #define SJA1105_GENERAL_STATUS1_L2BUSYFDS 0x00000002
680 #define SJA1105_GENERAL_STATUS1_L2BUSYS 0x00000001
681 
682 //General Status 2 register
683 #define SJA1105_GENERAL_STATUS2_MACADDRU 0xFFFFFFFF
684 
685 //General Status 3 register
686 #define SJA1105_GENERAL_STATUS3_MACADDHCL 0xFFFF0000
687 #define SJA1105_GENERAL_STATUS3_VLANIDHC 0x0000FFF0
688 #define SJA1105_GENERAL_STATUS3_CONFLICT 0x00000001
689 
690 //General Status 4 register
691 #define SJA1105_GENERAL_STATUS4_MACADDHCU 0xFFFFFFFF
692 
693 //General Status 5 register
694 #define SJA1105_GENERAL_STATUS5_WPVLANID 0xFFFF0000
695 #define SJA1105_GENERAL_STATUS5_PORT 0x0000FF00
696 #define SJA1105_GENERAL_STATUS5_VLANBUSYS 0x00000010
697 #define SJA1105_GENERAL_STATUS5_WRONGPORTS 0x00000008
698 #define SJA1105_GENERAL_STATUS5_VNOTFOUNDS 0x00000004
699 
700 //General Status 6 register
701 #define SJA1105_GENERAL_STATUS6_VLID 0xFFFF0000
702 #define SJA1105_GENERAL_STATUS6_PORTVL 0x0000FF00
703 #define SJA1105_GENERAL_STATUS6_VLNOTFOUND 0x00000001
704 
705 //General Status 7 register
706 #define SJA1105_GENERAL_STATUS7_EMPTYS 0x80000000
707 #define SJA1105_GENERAL_STATUS7_HANDLES 0x7FFFFFFF
708 
709 //General Status 8 register
710 #define SJA1105_GENERAL_STATUS8_HLWMARK 0x7FFFFFFF
711 
712 //General Status 9 register
713 #define SJA1105_GENERAL_STATUS9_PORT 0x0000FF00
714 #define SJA1105_GENERAL_STATUS9_FWDS 0x00000002
715 #define SJA1105_GENERAL_STATUS9_PARTS 0x00000001
716 
717 //General Status 10 register
718 #define SJA1105_GENERAL_STATUS10_RAMPARERRL 0x007FFFFF
719 
720 //General Status 11 register
721 #define SJA1105_GENERAL_STATUS11_RAMPARERRU 0x0000001F
722 
723 //Timestamp x register
724 #define SJA1105_PTP_TSx_UPDATE 0x00000001
725 
726 //Synchronization Engine Status 0 register
727 #define SJA1105_SYNC_ENGINE_STATUS0_SYNCSTATE 0xFFFFFFFF
728 #define SJA1105_SYNC_ENGINE_STATUS0_SYNCSTATE_INIT 0x00000000
729 #define SJA1105_SYNC_ENGINE_STATUS0_SYNCSTATE_INTEGRATE 0x00000001
730 #define SJA1105_SYNC_ENGINE_STATUS0_SYNCSTATE_UNSYNC 0x00000002
731 #define SJA1105_SYNC_ENGINE_STATUS0_SYNCSTATE_WAIT_4_CYCLE_START 0x00000003
732 #define SJA1105_SYNC_ENGINE_STATUS0_SYNCSTATE_CA_ENABLED 0x00000004
733 #define SJA1105_SYNC_ENGINE_STATUS0_SYNCSTATE_WAIT_FOR_IN 0x00000005
734 #define SJA1105_SYNC_ENGINE_STATUS0_SYNCSTATE_TENTATIVE_SYNC 0x00000006
735 #define SJA1105_SYNC_ENGINE_STATUS0_SYNCSTATE_SYNC 0x00000007
736 #define SJA1105_SYNC_ENGINE_STATUS0_SYNCSTATE_STABLE 0x00000008
737 
738 //Synchronization Engine Status 1 register
739 #define SJA1105_SYNC_ENGINE_STATUS1_INTEGCY 0xFFFFFFFF
740 
741 //Synchronization Engine Status 2 register
742 #define SJA1105_SYNC_ENGINE_STATUS2_ACTCORR 0xFFFFFFFF
743 
744 //Synchronization Engine Status 3 register
745 #define SJA1105_SYNC_ENGINE_STATUS3_MAXCORR 0xFFFFFFFF
746 
747 //Synchronization Engine Status 4 register
748 #define SJA1105_SYNC_ENGINE_STATUS4_MINCORR 0xFFFFFFFF
749 
750 //Synchronization Engine Status 5 register
751 #define SJA1105_SYNC_ENGINE_STATUS5_SYNCLOSS 0x0000FFFF
752 
753 //Synchronization Engine Status 6 register
754 #define SJA1105_SYNC_ENGINE_STATUS6_LOCMEM 0x000000FF
755 
756 //Synchronization Engine Status 7 register
757 #define SJA1105_SYNC_ENGINE_STATUS7_MINMEMVAR 0x000000FF
758 
759 //Synchronization Engine Status 8 register
760 #define SJA1105_SYNC_ENGINE_STATUS8_MAXMEMVAR 0x000000FF
761 
762 //Synchronization Engine Status 9 register
763 #define SJA1105_SYNC_ENGINE_STATUS9_LOCASYNMEM1 0x00FF0000
764 #define SJA1105_SYNC_ENGINE_STATUS9_LOCASYNMEM0 0x000000FF
765 
766 //Synchronization Engine Status 10 register
767 #define SJA1105_SYNC_ENGINE_STATUS10_MINASYNMEM 0x000000FF
768 
769 //Synchronization Engine Status 11 register
770 #define SJA1105_SYNC_ENGINE_STATUS11_MAXASYNMEM 0x000000FF
771 
772 //Synchronization Engine Status 12 register
773 #define SJA1105_SYNC_ENGINE_STATUS12_CAMEM 0x000000FF
774 
775 //Synchronization Engine Status 13 register
776 #define SJA1105_SYNC_ENGINE_STATUS13_SYSNMEM 0x000000FF
777 
778 //Synchronization Engine Status 14 register
779 #define SJA1105_SYNC_ENGINE_STATUS14_MOFFSET0 0xFFFFFFFF
780 
781 //Synchronization Engine Status 15 register
782 #define SJA1105_SYNC_ENGINE_STATUS15_MOFFSET1 0xFFFFFFFF
783 
784 //Synchronization Engine Status 16 register
785 #define SJA1105_SYNC_ENGINE_STATUS16_MOFFSET2 0xFFFFFFFF
786 
787 //Synchronization Engine Status 17 register
788 #define SJA1105_SYNC_ENGINE_STATUS17_MOFFSET3 0xFFFFFFFF
789 
790 //Synchronization Engine Status 18 register
791 #define SJA1105_SYNC_ENGINE_STATUS18_MOFFSET4 0xFFFFFFFF
792 
793 //Synchronization Engine Status 19 register
794 #define SJA1105_SYNC_ENGINE_STATUS19_MOFFSET5 0xFFFFFFFF
795 
796 //Synchronization Engine Status 20 register
797 #define SJA1105_SYNC_ENGINE_STATUS20_MOFFSET6 0xFFFFFFFF
798 
799 //Synchronization Engine Status 21 register
800 #define SJA1105_SYNC_ENGINE_STATUS21_MOFFSET7 0xFFFFFFFF
801 
802 //Synchronization Engine Status 23 register
803 #define SJA1105_SYNC_ENGINE_STATUS23_TIMER 0x3FFFFFFF
804 
805 //Synchronization Engine Status 24 register
806 #define SJA1105_SYNC_ENGINE_STATUS24_CLOCK 0x07FFFFFF
807 
808 //VL Memory Partition Status x register
809 #define SJA1105_VL_MEM_PARTI_STATUSx_PARTDRPVL 0x80000000
810 #define SJA1105_VL_MEM_PARTI_STATUSx_PARTSPCVL 0x7FFFFFFF
811 
812 //VL memory Partition Error Counter x register
813 #define SJA1105_VL_MEM_PART_ERR_CNTx_PARTDRPCNTVL 0xFFFFFFFF
814 
815 //L2 Memory Partition Status x register
816 #define SJA1105_L2_MEM_PART_STATUSx_L2PARTS 0x80000000
817 #define SJA1105_L2_MEM_PART_STATUSx_L2PSPC 0x7FFFFFFF
818 
819 //L2 Memory Partition Error Counter x register
820 #define SJA1105_L2_MEM_PART_ERR_CNTx_PARTDROP 0xFFFFFFFF
821 
822 //Port N MAC-level Diagnostic Counters register
823 #define SJA1105_PORTn_MAC_DIAG_CNT_N_RUNT 0xFF000000
824 #define SJA1105_PORTn_MAC_DIAG_CNT_N_SOFERR 0x00FF0000
825 #define SJA1105_PORTn_MAC_DIAG_CNT_N_ALIGNERR 0x0000FF00
826 #define SJA1105_PORTn_MAC_DIAG_CNT_N_MIIERR 0x000000FF
827 
828 //Port N MAC-level Diagnostic Flags register
829 #define SJA1105_PORTn_MAC_DIAG_FLAGS_TYPEERR 0x08000000
830 #define SJA1105_PORTn_MAC_DIAG_FLAGS_SIZEERR 0x04000000
831 #define SJA1105_PORTn_MAC_DIAG_FLAGS_TCTIMEOUT 0x02000000
832 #define SJA1105_PORTn_MAC_DIAG_FLAGS_PRIORERR 0x01000000
833 #define SJA1105_PORTn_MAC_DIAG_FLAGS_NOMASTER 0x00800000
834 #define SJA1105_PORTn_MAC_DIAG_FLAGS_MEMOV 0x00400000
835 #define SJA1105_PORTn_MAC_DIAG_FLAGS_MEMERR 0x00200000
836 #define SJA1105_PORTn_MAC_DIAG_FLAGS_INVTYP 0x00080000
837 #define SJA1105_PORTn_MAC_DIAG_FLAGS_INTCYOV 0x00040000
838 #define SJA1105_PORTn_MAC_DIAG_FLAGS_DOMERR 0x00020000
839 #define SJA1105_PORTn_MAC_DIAG_FLAGS_PCFBAGDROP 0x00010000
840 #define SJA1105_PORTn_MAC_DIAG_FLAGS_SPCPRIOR 0x0000F000
841 #define SJA1105_PORTn_MAC_DIAG_FLAGS_AGEPRIOR 0x00000F00
842 #define SJA1105_PORTn_MAC_DIAG_FLAGS_PORTDROP 0x00000040
843 #define SJA1105_PORTn_MAC_DIAG_FLAGS_LENDROP 0x00000020
844 #define SJA1105_PORTn_MAC_DIAG_FLAGS_BAGDROP 0x00000010
845 #define SJA1105_PORTn_MAC_DIAG_FLAGS_POLIECERR 0x00000008
846 #define SJA1105_PORTn_MAC_DIAG_FLAGS_DRPNONA664ERR 0x00000004
847 #define SJA1105_PORTn_MAC_DIAG_FLAGS_SPCERR 0x00000002
848 #define SJA1105_PORTn_MAC_DIAG_FLAGS_AGEDRP 0x00000001
849 
850 //Port N QLEVEL0 register
851 #define SJA1105_PORTn_QLEVEL0_QLEVEL_HWM 0x01FF0000
852 #define SJA1105_PORTn_QLEVEL0_QLEVEL 0x000001FF
853 
854 //Port N QLEVEL1 register
855 #define SJA1105_PORTn_QLEVEL1_QLEVEL_HWM 0x01FF0000
856 #define SJA1105_PORTn_QLEVEL1_QLEVEL 0x000001FF
857 
858 //Port N QLEVEL2 register
859 #define SJA1105_PORTn_QLEVEL2_QLEVEL_HWM 0x01FF0000
860 #define SJA1105_PORTn_QLEVEL2_QLEVEL 0x000001FF
861 
862 //Port N QLEVEL3 register
863 #define SJA1105_PORTn_QLEVEL3_QLEVEL_HWM 0x01FF0000
864 #define SJA1105_PORTn_QLEVEL3_QLEVEL 0x000001FF
865 
866 //Port N QLEVEL4 register
867 #define SJA1105_PORTn_QLEVEL4_QLEVEL_HWM 0x01FF0000
868 #define SJA1105_PORTn_QLEVEL4_QLEVEL 0x000001FF
869 
870 //Port N QLEVEL5 register
871 #define SJA1105_PORTn_QLEVEL5_QLEVEL_HWM 0x01FF0000
872 #define SJA1105_PORTn_QLEVEL5_QLEVEL 0x000001FF
873 
874 //Port N QLEVEL6 register
875 #define SJA1105_PORTn_QLEVEL6_QLEVEL_HWM 0x01FF0000
876 #define SJA1105_PORTn_QLEVEL6_QLEVEL 0x000001FF
877 
878 //Port N QLEVEL7 register
879 #define SJA1105_PORTn_QLEVEL7_QLEVEL_HWM 0x01FF0000
880 #define SJA1105_PORTn_QLEVEL7_QLEVEL 0x000001FF
881 
882 //Virtual Link Status 0 register
883 #define SJA1105_VIRTUAL_LINK_STATUS0_TIMINGERR 0xFFFF0000
884 #define SJA1105_VIRTUAL_LINK_STATUS0_UNRELEASED 0x0000FFFF
885 
886 //Virtual Link Status 1 register
887 #define SJA1105_VIRTUAL_LINK_STATUS1_LENGTHERR 0x0000FFFF
888 
889 //RAM Parity Check Configuration 0 register
890 #define SJA1105_RAM_PARITY_CHECK_CONFIG0_RPARINITL 0x007FFFFF
891 
892 //RAM Parity Check Configuration 1 register
893 #define SJA1105_RAM_PARITY_CHECK_CONFIG1_RPARINITU 0x0000001F
894 
895 //Ethernet Port Status Control 0 register
896 #define SJA1105_PORT_STATUS_CTRL0_CLEARPORT 0x0000001F
897 
898 //VL Status Control register
899 #define SJA1105_VL_STATUS_CTRL_CLEARVLS 0x0000001F
900 
901 //Ethernet Port Status Control 1 register
902 #define SJA1105_PORT_STATUS_CTRL1_INHIBITTX 0x0000001F
903 
904 //PTP Control 1 register
905 #define SJA1105_PTP_CTRL1_VALID 0x80000000
906 #define SJA1105_PTP_CTRL1_PTPSTRTSCH 0x40000000
907 #define SJA1105_PTP_CTRL1_PTPSTOPSCH 0x20000000
908 #define SJA1105_PTP_CTRL1_STARTPTPCP 0x10000000
909 #define SJA1105_PTP_CTRL1_STOPPTPCP 0x08000000
910 #define SJA1105_PTP_CTRL1_CASSYNC 0x04000000
911 #define SJA1105_PTP_CTRL1_RESPTP 0x00000008
912 #define SJA1105_PTP_CTRL1_CORRCLK4TS 0x00000004
913 #define SJA1105_PTP_CTRL1_PTPCLKSUB 0x00000002
914 #define SJA1105_PTP_CTRL1_PTPCLKADD 0x00000001
915 
916 //PTP Control 2 register
917 #define SJA1105_PTP_CTRL2_PTPSCHTML 0xFFFFFFFF
918 
919 //PTP Control 3 register
920 #define SJA1105_PTP_CTRL3_PTPSCHTMU 0xFFFFFFFF
921 
922 //PTP Control 4 register
923 #define SJA1105_PTP_CTRL4_PTPPINSTL 0xFFFFFFFF
924 
925 //PTP Control 5 register
926 #define SJA1105_PTP_CTRL5_PTPPINSTU 0xFFFFFFFF
927 
928 //PTP Control 6 register
929 #define SJA1105_PTP_CTRL6_PTPPINDUR 0xFFFFFFFF
930 
931 //PTP Control 7 register
932 #define SJA1105_PTP_CTRL7_PTPCLKVALL 0xFFFFFFFF
933 
934 //PTP Control 8 register
935 #define SJA1105_PTP_CTRL8_PTPCLKVALU 0xFFFFFFFF
936 
937 //PTP Control 9 register
938 #define SJA1105_PTP_CTRL9_PTPCLKRATE 0xFFFFFFFF
939 
940 //PTP Control 10 register
941 #define SJA1105_PTP_CTRL10_PTPTSCLKL 0xFFFFFFFF
942 
943 //PTP Control 11 register
944 #define SJA1105_PTP_CTRL11_PTPTSCLKU 0xFFFFFFFF
945 
946 //PTP Control 12 register
947 #define SJA1105_PTP_CTRL12_PTPCLKCORP 0xFFFFFFFF
948 
949 //PTP Control 13 register
950 #define SJA1105_PTP_CTRL13_PTPSYNCTSL 0xFFFFFFFF
951 
952 //PTP Control 14 register
953 #define SJA1105_PTP_CTRL14_PTPSYNCTSU 0xFFFFFFFF
954 
955 //L2 Address Lookup Table Reconfiguration 0 register
956 #define SJA1105_L2_ADDR_LUT_RECONFIG0_VALID 0x80000000
957 #define SJA1105_L2_ADDR_LUT_RECONFIG0_RDWRSET 0x40000000
958 #define SJA1105_L2_ADDR_LUT_RECONFIG0_ERRORS 0x20000000
959 #define SJA1105_L2_ADDR_LUT_RECONFIG0_LOCKEDS 0x10000000
960 #define SJA1105_L2_ADDR_LUT_RECONFIG0_VALIDENT 0x08000000
961 #define SJA1105_L2_ADDR_LUT_RECONFIG0_MGMTROUTE 0x04000000
962 #define SJA1105_L2_ADDR_LUT_RECONFIG0_HOSTCMD 0x03800000
963 #define SJA1105_L2_ADDR_LUT_RECONFIG0_HOSTCMD_SEARCH 0x00800000
964 #define SJA1105_L2_ADDR_LUT_RECONFIG0_HOSTCMD_READ 0x01000000
965 #define SJA1105_L2_ADDR_LUT_RECONFIG0_HOSTCMD_WRITE 0x01800000
966 #define SJA1105_L2_ADDR_LUT_RECONFIG0_HOSTCMD_INVALIDATE 0x02000000
967 
968 //L2 Address Lookup Table Reconfiguration 1 register
969 #define SJA1105_L2_ADDR_LUT_RECONFIG1_ENTRY_25_0 0xFFFFFFC0
970 
971 //L2 Address Lookup Table Reconfiguration 2 register
972 #define SJA1105_L2_ADDR_LUT_RECONFIG2_ENTRY_57_26 0xFFFFFFC0
973 
974 //L2 Address Lookup Table Reconfiguration 3 register
975 #define SJA1105_L2_ADDR_LUT_RECONFIG3_ENTRY_89_58 0xFFFFFFC0
976 
977 //L2 Address Lookup Table Reconfiguration 4 register
978 #define SJA1105_L2_ADDR_LUT_RECONFIG4_ENTRY_121_90 0xFFFFFFC0
979 
980 //L2 Address Lookup Table Reconfiguration 5 register
981 #define SJA1105_L2_ADDR_LUT_RECONFIG5_ENTRY_153_122 0xFFFFFFC0
982 
983 //L2 Forwarding Table Reconfiguration 0 register
984 #define SJA1105_L2_FWD_TABLE_RECONFIG0_VALID 0x80000000
985 #define SJA1105_L2_FWD_TABLE_RECONFIG0_ERRORS 0x40000000
986 #define SJA1105_L2_FWD_TABLE_RECONFIG0_RDWRSET 0x20000000
987 #define SJA1105_L2_FWD_TABLE_RECONFIG0_INDEX 0x0000001F
988 
989 //L2 Forwarding Table Reconfiguration 1 register
990 #define SJA1105_L2_FWD_TABLE_RECONFIG1_ENTRY_31_25 0xFE000000
991 
992 //L2 Forwarding Table Reconfiguration 2 register
993 #define SJA1105_L2_FWD_TABLE_RECONFIG2_ENTRY_63_32 0xFFFFFFFF
994 
995 //VLAN Lookup Table Reconfiguration 0 register
996 #define SJA1105_VLAN_LUT_RECONFIG0_VALID 0x80000000
997 #define SJA1105_VLAN_LUT_RECONFIG0_RDWRSET 0x40000000
998 #define SJA1105_VLAN_LUT_RECONFIG0_VALIDENT 0x08000000
999 
1000 //VLAN Lookup Table Reconfiguration 1 register
1001 #define SJA1105_VLAN_LUT_RECONFIG1_ENTRY_4_0 0xF8000000
1002 
1003 //VLAN Lookup Table Reconfiguration 2 register
1004 #define SJA1105_VLAN_LUT_RECONFIG2_ENTRY_36_5 0xFFFFFFFF
1005 
1006 //MAC Configuration Table Reconfiguration 0 register
1007 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG0_VALID 0x80000000
1008 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG0_ERRORS 0x40000000
1009 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG0_RDWRSET 0x20000000
1010 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG0_PORTIDX 0x00000007
1011 
1012 //MAC Configuration Table Reconfiguration 1 register
1013 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG1_ENTRY_18_0 0xFFFFE000
1014 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG1_INGRESS 0x80000000
1015 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG1_MIRRCIE 0x40000000
1016 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG1_MIRRCETAG 0x20000000
1017 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG1_INGMIRRVID 0x1FFE0000
1018 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG1_INGMIRRPCP 0x0001C000
1019 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG1_INGMIRRDEI 0x00002000
1020 
1021 //MAC Configuration Table Reconfiguration 2 register
1022 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_ENTRY_50_19 0xFFFFFFFF
1023 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_MAXAGE_LSB 0xFE000000
1024 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_VLANPRIO 0x01C00000
1025 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_VLANID 0x003FFC00
1026 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_ING_MIRR 0x00000200
1027 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_EGR_MIRR 0x00000100
1028 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_DRPNONA664 0x00000080
1029 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_DRPDTAG 0x00000040
1030 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_DRPSOTAG 0x00000020
1031 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_DRPSITAG 0x00000010
1032 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_DRPUNTAG 0x00000008
1033 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_RETAG 0x00000004
1034 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_DYN_LEARN 0x00000002
1035 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG2_EGRESS 0x00000001
1036 
1037 //MAC Configuration Table Reconfiguration 3 register
1038 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG3_ENTRY_82_51 0xFFFFFFFF
1039 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG3_TP_DELIN_LSB 0xFFFE0000
1040 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG3_TP_DELOUT 0x0001FFFE
1041 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG3_MAXAGE_MSB 0x00000001
1042 
1043 //MAC Configuration Table Reconfiguration 4 register
1044 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_ENTRY_114_83 0xFFFFFFFF
1045 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_BASE1_LSB 0xF0000000
1046 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_ENABLED1 0x08000000
1047 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_TOP0 0x07FC0000
1048 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_BASE0 0x0003FE00
1049 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_ENABLED0 0x00000100
1050 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_IFG 0x000000F8
1051 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_SPEED 0x00000006
1052 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_SPEED_1GBPS 0x00000002
1053 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_SPEED_100MBPS 0x00000004
1054 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_SPEED_10MBPS 0x00000006
1055 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG4_TP_DELIN_MSB 0x00000001
1056 
1057 //MAC Configuration Table Reconfiguration 5 register
1058 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG5_ENTRY_146_115 0xFFFFFFFF
1059 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG5_TOP2_LSB 0xFF000000
1060 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG5_BASE2 0x00FF8000
1061 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG5_ENABLED2 0x00004000
1062 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG5_TOP1 0x00003FE0
1063 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG5_BASE1_MSB 0x0000001F
1064 
1065 //MAC Configuration Table Reconfiguration 6 register
1066 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG6_ENTRY_178_147 0xFFFFFFFF
1067 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG6_TOP4_LSB 0xC0000000
1068 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG6_BASE4 0x3FE00000
1069 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG6_ENABLED4 0x00100000
1070 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG6_TOP3 0x000FF800
1071 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG6_BASE3 0x000007FC
1072 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG6_ENABLED3 0x00000002
1073 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG6_TOP2_MSB 0x00000001
1074 
1075 //MAC Configuration Table Reconfiguration 7 register
1076 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG7_ENTRY_210_179 0xFFFFFFFF
1077 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG7_BASE6_LSB 0xF8000000
1078 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG7_ENABLED6 0x04000000
1079 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG7_TOP5 0x03FE0000
1080 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG7_BASE5 0x0001FF00
1081 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG7_ENABLED5 0x00000080
1082 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG7_TOP4_MSB 0x0000007F
1083 
1084 //MAC Configuration Table Reconfiguration 8 register
1085 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG8_ENTRY_242_211 0xFFFFFFFF
1086 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG8_TOP7 0xFF800000
1087 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG8_BASE7 0x007FC000
1088 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG8_ENABLED7 0x00002000
1089 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG8_TOP6 0x00001FF0
1090 #define SJA1105_MAC_CONFIG_TABLE_RECONFIG8_BASE6_MSB 0x0000000F
1091 
1092 //Retagging Table Reconfiguration 0 register
1093 #define SJA1105_RETAGGING_TABLE_RECONFIG0_VALID 0x80000000
1094 #define SJA1105_RETAGGING_TABLE_RECONFIG0_ERRORS 0x40000000
1095 #define SJA1105_RETAGGING_TABLE_RECONFIG0_VALIDENT 0x20000000
1096 #define SJA1105_RETAGGING_TABLE_RECONFIG0_RDWRSET 0x10000000
1097 #define SJA1105_RETAGGING_TABLE_RECONFIG0_INDEX 0x0000003F
1098 
1099 //Retagging Table Reconfiguration 1 register
1100 #define SJA1105_RETAGGING_TABLE_RECONFIG1_ENTRY_8_0 0xFF800000
1101 
1102 //Retagging Table Reconfiguration 2 register
1103 #define SJA1105_RETAGGING_TABLE_RECONFIG2_ENTRY_40_9 0xFFFFFFFF
1104 
1105 //General Parameters Reconfiguration 0 register
1106 #define SJA1105_GENERAL_PARAMS_RECONFIG0_VALID 0x80000000
1107 #define SJA1105_GENERAL_PARAMS_RECONFIG0_ERRORS 0x40000000
1108 #define SJA1105_GENERAL_PARAMS_RECONFIG0_MIRR_ERR 0x20000000
1109 #define SJA1105_GENERAL_PARAMS_RECONFIG0_RDWRSET 0x10000000
1110 
1111 //General Parameters Reconfiguration 1 register
1112 #define SJA1105_GENERAL_PARAMS_RECONFIG1_ENTRY_9_0 0xFFC00000
1113 
1114 //General Parameters Reconfiguration 2 register
1115 #define SJA1105_GENERAL_PARAMS_RECONFIG2_ENTRY_41_10 0xFFFFFFFF
1116 
1117 //General Parameters Reconfiguration 3 register
1118 #define SJA1105_GENERAL_PARAMS_RECONFIG3_ENTRY_73_42 0xFFFFFFFF
1119 
1120 //General Parameters Reconfiguration 4 register
1121 #define SJA1105_GENERAL_PARAMS_RECONFIG4_ENTRY_105_74 0xFFFFFFFF
1122 
1123 //General Parameters Reconfiguration 5 register
1124 #define SJA1105_GENERAL_PARAMS_RECONFIG5_ENTRY_137_106 0xFFFFFFFF
1125 
1126 //General Parameters Reconfiguration 6 register
1127 #define SJA1105_GENERAL_PARAMS_RECONFIG6_ENTRY_169_138 0xFFFFFFFF
1128 
1129 //General Parameters Reconfiguration 7 register
1130 #define SJA1105_GENERAL_PARAMS_RECONFIG7_ENTRY_201_170 0xFFFFFFFF
1131 
1132 //General Parameters Reconfiguration 8 register
1133 #define SJA1105_GENERAL_PARAMS_RECONFIG8_ENTRY_233_202 0xFFFFFFFF
1134 
1135 //General Parameters Reconfiguration 9 register
1136 #define SJA1105_GENERAL_PARAMS_RECONFIG9_ENTRY_265_234 0xFFFFFFFF
1137 
1138 //General Parameters Reconfiguration 10 register
1139 #define SJA1105_GENERAL_PARAMS_RECONFIG10_ENTRY_297_266 0xFFFFFFFF
1140 
1141 //General Parameters Reconfiguration 11 register
1142 #define SJA1105_GENERAL_PARAMS_RECONFIG11_ENTRY_329_298 0xFFFFFFFF
1143 
1144 //VL Lookup Table Reconfiguration 0 register
1145 #define SJA1105_VL_LUT_RECONFIG0_VALID 0x80000000
1146 #define SJA1105_VL_LUT_RECONFIG0_ERRORS 0x40000000
1147 #define SJA1105_VL_LUT_RECONFIG0_RDWRSET 0x20000000
1148 #define SJA1105_VL_LUT_RECONFIG0_INDEX 0x000003FF
1149 
1150 //VL Lookup Table Reconfiguration 1 register
1151 #define SJA1105_VL_LUT_RECONFIG1_ENTRY_7_0 0xFF000000
1152 
1153 //VL Lookup Table Reconfiguration 2 register
1154 #define SJA1105_VL_LUT_RECONFIG2_ENTRY_39_8 0xFFFFFFFF
1155 
1156 //VL Lookup Table Reconfiguration 3 register
1157 #define SJA1105_VL_LUT_RECONFIG3_ENTRY_71_40 0xFFFFFFFF
1158 
1159 //L2 Lookup Parameters 0 register
1160 #define SJA1105_L2_LOOKUP_PARAMS0_VALID 0x80000000
1161 #define SJA1105_L2_LOOKUP_PARAMS0_RDWRSET 0x40000000
1162 
1163 //L2 Lookup Parameters 1 register
1164 #define SJA1105_L2_LOOKUP_PARAMS1_ENTRY_9_0 0xFFC00000
1165 
1166 //L2 Lookup Parameters 2 register
1167 #define SJA1105_L2_LOOKUP_PARAMS2_ENTRY_41_10 0xFFFFFFFF
1168 
1169 //L2 Lookup Parameters 3 register
1170 #define SJA1105_L2_LOOKUP_PARAMS3_ENTRY_73_42 0xFFFFFFFF
1171 
1172 //L2 Lookup Parameters 4 register
1173 #define SJA1105_L2_LOOKUP_PARAMS4_ENTRY_105_74 0xFFFFFFFF
1174 
1175 //AVB Parameters Reconfiguration 0 register
1176 #define SJA1105_AVB_PARAMS_RECONFIG0_VALID 0x80000000
1177 #define SJA1105_AVB_PARAMS_RECONFIG0_ERRORS 0x40000000
1178 #define SJA1105_AVB_PARAMS_RECONFIG0_RDWRSET 0x20000000
1179 
1180 //AVB Parameters Reconfiguration 1 register
1181 #define SJA1105_AVB_PARAMS_RECONFIG1_ENTRY_1_0 0xC0000000
1182 
1183 //AVB Parameters Reconfiguration 2 register
1184 #define SJA1105_AVB_PARAMS_RECONFIG2_ENTRY_33_2 0xFFFFFFFF
1185 
1186 //AVB Parameters Reconfiguration 3 register
1187 #define SJA1105_AVB_PARAMS_RECONFIG3_ENTRY_65_34 0xFFFFFFFF
1188 
1189 //AVB Parameters Reconfiguration 4 register
1190 #define SJA1105_AVB_PARAMS_RECONFIG4_ENTRY_97_66 0xFFFFFFFF
1191 
1192 //Credit-Based Shaping Reconfiguration 0 register
1193 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG0_VALID 0x80000000
1194 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG0_RDWRSET 0x40000000
1195 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG0_ERRORS 0x20000000
1196 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG0_CBSIDX 0x0000000F
1197 
1198 //Credit-Based Shaping Reconfiguration 1 register
1199 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG1_ENTRY_5_0 0xFC000000
1200 
1201 //Credit-Based Shaping Reconfiguration 2 register
1202 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG2_ENTRY_37_6 0xFFFFFFFF
1203 
1204 //Credit-Based Shaping Reconfiguration 3 register
1205 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG3_ENTRY_69_38 0xFFFFFFFF
1206 
1207 //Credit-Based Shaping Reconfiguration 4 register
1208 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG4_ENTRY_101_70 0xFFFFFFFF
1209 
1210 //Credit-Based Shaping Reconfiguration 5 register
1211 #define SJA1105_CREDIT_BASED_SHAPING_RECONFIG5_ENTRY_133_102 0xFFFFFFFF
1212 
1213 //L2 Forwarding Parameters Reconfiguration 0 register
1214 #define SJA1105_L2_FWD_PARAMS_RECONFIG0_ENTRY_18_0 0xFFFFE000
1215 
1216 //L2 Forwarding Parameters Reconfiguration 1 register
1217 #define SJA1105_L2_FWD_PARAMS_RECONFIG1_ENTRY_50_19 0xFFFFFFFF
1218 
1219 //L2 Forwarding Parameters Reconfiguration 2 register
1220 #define SJA1105_L2_FWD_PARAMS_RECONFIG2_ENTRY_82_51 0xFFFFFFFF
1221 
1222 //Reset Control register
1223 #define SJA1105_RESET_CTRL_SWITCH_RST 0x00000100
1224 #define SJA1105_RESET_CTRL_CFG_RST 0x00000080
1225 #define SJA1105_RESET_CTRL_CAR_RST 0x00000020
1226 #define SJA1105_RESET_CTRL_OTP_RST 0x00000010
1227 #define SJA1105_RESET_CTRL_WARM_RST 0x00000008
1228 #define SJA1105_RESET_CTRL_COLD_RST 0x00000004
1229 #define SJA1105_RESET_CTRL_POR_RST 0x00000002
1230 
1231 //RGU Unit Disable register
1232 #define SJA1105_RGU_UNIT_DISABLE_DISABLE_FLAG 0x00000001
1233 
1234 //PLLx Status register
1235 #define SJA1105_PLL_x_S_LOCK 0x00000001
1236 
1237 //PLLx Control register
1238 #define SJA1105_PLL_x_C_PLLCLKSRC 0x1F000000
1239 #define SJA1105_PLL_x_C_PLLCLKSRC_XO66M_0 0x0A000000
1240 #define SJA1105_PLL_x_C_MSEL 0x00FF0000
1241 #define SJA1105_PLL_x_C_MSEL_DIV1 0x00000000
1242 #define SJA1105_PLL_x_C_MSEL_DIV2 0x00010000
1243 #define SJA1105_PLL_x_C_MSEL_DIV3 0x00020000
1244 #define SJA1105_PLL_x_C_MSEL_DIV4 0x00030000
1245 #define SJA1105_PLL_x_C_NSEL 0x00003000
1246 #define SJA1105_PLL_x_C_NSEL_DIV1 0x00000000
1247 #define SJA1105_PLL_x_C_NSEL_DIV2 0x00001000
1248 #define SJA1105_PLL_x_C_NSEL_DIV3 0x00002000
1249 #define SJA1105_PLL_x_C_NSEL_DIV4 0x00003000
1250 #define SJA1105_PLL_x_C_AUTOBLOCK 0x00000800
1251 #define SJA1105_PLL_x_C_PSEL 0x00000300
1252 #define SJA1105_PLL_x_C_PSEL_DIV1 0x00000000
1253 #define SJA1105_PLL_x_C_PSEL_DIV2 0x00000100
1254 #define SJA1105_PLL_x_C_PSEL_DIV3 0x00000200
1255 #define SJA1105_PLL_x_C_PSEL_DIV4 0x00000300
1256 #define SJA1105_PLL_x_C_DIRECT 0x00000080
1257 #define SJA1105_PLL_x_C_FBSEL 0x00000040
1258 #define SJA1105_PLL_x_C_P23EN 0x00000004
1259 #define SJA1105_PLL_x_C_BYPASS 0x00000002
1260 #define SJA1105_PLL_x_C_PD 0x00000001
1261 
1262 //IDIVx Control register
1263 #define SJA1105_IDIV_x_C_CLKSRC 0x1F000000
1264 #define SJA1105_IDIV_x_C_CLKSRC_XO66M_0 0x0A000000
1265 #define SJA1105_IDIV_x_C_AUTOBLOCK 0x00000800
1266 #define SJA1105_IDIV_x_C_IDIV 0x000003FC
1267 #define SJA1105_IDIV_x_C_IDIV_DIV1 0x00000000
1268 #define SJA1105_IDIV_x_C_IDIV_DIV2 0x00000004
1269 #define SJA1105_IDIV_x_C_IDIV_DIV3 0x00000008
1270 #define SJA1105_IDIV_x_C_IDIV_DIV4 0x0000000C
1271 #define SJA1105_IDIV_x_C_IDIV_DIV5 0x00000010
1272 #define SJA1105_IDIV_x_C_IDIV_DIV6 0x00000014
1273 #define SJA1105_IDIV_x_C_IDIV_DIV7 0x00000018
1274 #define SJA1105_IDIV_x_C_IDIV_DIV8 0x0000001C
1275 #define SJA1105_IDIV_x_C_IDIV_DIV9 0x00000020
1276 #define SJA1105_IDIV_x_C_IDIV_DIV10 0x00000024
1277 #define SJA1105_IDIV_x_C_PD 0x00000001
1278 
1279 //MIIx Clock Control register
1280 #define SJA1105_MIIx_CLK_CTRL_CLKSRC 0x1F000000
1281 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_TX_CLK_0 0x00000000
1282 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_RX_CLK_0 0x01000000
1283 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_TX_CLK_1 0x02000000
1284 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_RX_CLK_1 0x03000000
1285 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_TX_CLK_2 0x04000000
1286 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_RX_CLK_2 0x05000000
1287 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_TX_CLK_3 0x06000000
1288 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_RX_CLK_3 0x07000000
1289 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_TX_CLK_4 0x08000000
1290 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_RX_CLK_4 0x09000000
1291 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_XO66M_0 0x0A000000
1292 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_PLL0 0x0B000000
1293 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_PLL0_120 0x0C000000
1294 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_PLL0_240 0x0D000000
1295 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_PLL1 0x0E000000
1296 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_PLL1_120 0x0F000000
1297 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_PLL1_240 0x10000000
1298 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_IDIV0 0x11000000
1299 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_IDIV1 0x12000000
1300 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_IDIV2 0x13000000
1301 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_IDIV3 0x14000000
1302 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_IDIV4 0x15000000
1303 #define SJA1105_MIIx_CLK_CTRL_AUTOBLOCK 0x00000800
1304 #define SJA1105_MIIx_CLK_CTRL_PD 0x00000001
1305 
1306 //Internal clock selection
1307 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_TX_CLK_x(n) (((n) * 2) << 24)
1308 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_RX_CLK_x(n) (((n) * 2 + 0x01) << 24)
1309 #define SJA1105_MIIx_CLK_CTRL_CLKSRC_IDIVx(n) (((n) + 0x11) << 24)
1310 
1311 //CFG_PAD_MIIx_TX register
1312 #define SJA1105_CFG_PAD_MIIx_TX_D32_OS 0x18000000
1313 #define SJA1105_CFG_PAD_MIIx_TX_D32_OS_LOW 0x00000000
1314 #define SJA1105_CFG_PAD_MIIx_TX_D32_OS_MEDIUM 0x08000000
1315 #define SJA1105_CFG_PAD_MIIx_TX_D32_OS_FAST 0x10000000
1316 #define SJA1105_CFG_PAD_MIIx_TX_D32_OS_HIGH 0x18000000
1317 #define SJA1105_CFG_PAD_MIIx_TX_D32_IPUD 0x03000000
1318 #define SJA1105_CFG_PAD_MIIx_TX_D32_IPUD_PULL_UP 0x00000000
1319 #define SJA1105_CFG_PAD_MIIx_TX_D32_IPUD_REPEATER 0x01000000
1320 #define SJA1105_CFG_PAD_MIIx_TX_D32_IPUD_PLAIN 0x02000000
1321 #define SJA1105_CFG_PAD_MIIx_TX_D32_IPUD_PULL_DOWN 0x03000000
1322 #define SJA1105_CFG_PAD_MIIx_TX_D10_OS 0x00180000
1323 #define SJA1105_CFG_PAD_MIIx_TX_D10_OS_LOW 0x00000000
1324 #define SJA1105_CFG_PAD_MIIx_TX_D10_OS_MEDIUM 0x00080000
1325 #define SJA1105_CFG_PAD_MIIx_TX_D10_OS_FAST 0x00100000
1326 #define SJA1105_CFG_PAD_MIIx_TX_D10_OS_HIGH 0x00180000
1327 #define SJA1105_CFG_PAD_MIIx_TX_D10_IPUD 0x00030000
1328 #define SJA1105_CFG_PAD_MIIx_TX_D10_IPUD_PULL_UP 0x00000000
1329 #define SJA1105_CFG_PAD_MIIx_TX_D10_IPUD_REPEATER 0x00010000
1330 #define SJA1105_CFG_PAD_MIIx_TX_D10_IPUD_PLAIN 0x00020000
1331 #define SJA1105_CFG_PAD_MIIx_TX_D10_IPUD_PULL_DOWN 0x00030000
1332 #define SJA1105_CFG_PAD_MIIx_TX_CTRL_OS 0x00001800
1333 #define SJA1105_CFG_PAD_MIIx_TX_CTRL_OS_LOW 0x00000000
1334 #define SJA1105_CFG_PAD_MIIx_TX_CTRL_OS_MEDIUM 0x00000800
1335 #define SJA1105_CFG_PAD_MIIx_TX_CTRL_OS_FAST 0x00001000
1336 #define SJA1105_CFG_PAD_MIIx_TX_CTRL_OS_HIGH 0x00001800
1337 #define SJA1105_CFG_PAD_MIIx_TX_CTRL_IPUD 0x00000300
1338 #define SJA1105_CFG_PAD_MIIx_TX_CTRL_IPUD_PULL_UP 0x00000000
1339 #define SJA1105_CFG_PAD_MIIx_TX_CTRL_IPUD_REPEATER 0x00000100
1340 #define SJA1105_CFG_PAD_MIIx_TX_CTRL_IPUD_PLAIN 0x00000200
1341 #define SJA1105_CFG_PAD_MIIx_TX_CTRL_IPUD_PULL_DOWN 0x00000300
1342 #define SJA1105_CFG_PAD_MIIx_TX_CLK_OS 0x00000018
1343 #define SJA1105_CFG_PAD_MIIx_TX_CLK_OS_LOW 0x00000000
1344 #define SJA1105_CFG_PAD_MIIx_TX_CLK_OS_MEDIUM 0x00000008
1345 #define SJA1105_CFG_PAD_MIIx_TX_CLK_OS_FAST 0x00000010
1346 #define SJA1105_CFG_PAD_MIIx_TX_CLK_OS_HIGH 0x00000018
1347 #define SJA1105_CFG_PAD_MIIx_TX_CLK_IH 0x00000004
1348 #define SJA1105_CFG_PAD_MIIx_TX_CLK_IPUD 0x00000003
1349 #define SJA1105_CFG_PAD_MIIx_TX_CLK_IPUD_PULL_UP 0x00000000
1350 #define SJA1105_CFG_PAD_MIIx_TX_CLK_IPUD_REPEATER 0x00000001
1351 #define SJA1105_CFG_PAD_MIIx_TX_CLK_IPUD_PLAIN 0x00000002
1352 #define SJA1105_CFG_PAD_MIIx_TX_CLK_IPUD_PULL_DOWN 0x00000003
1353 
1354 //CFG_PAD_MIIx_RX register
1355 #define SJA1105_CFG_PAD_MIIx_RX_D32_IH 0x04000000
1356 #define SJA1105_CFG_PAD_MIIx_RX_D32_IPUD 0x03000000
1357 #define SJA1105_CFG_PAD_MIIx_RX_D32_IPUD_PULL_UP 0x00000000
1358 #define SJA1105_CFG_PAD_MIIx_RX_D32_IPUD_REPEATER 0x01000000
1359 #define SJA1105_CFG_PAD_MIIx_RX_D32_IPUD_PLAIN 0x02000000
1360 #define SJA1105_CFG_PAD_MIIx_RX_D32_IPUD_PULL_DOWN 0x03000000
1361 #define SJA1105_CFG_PAD_MIIx_RX_D10_IH 0x00040000
1362 #define SJA1105_CFG_PAD_MIIx_RX_D10_IPUD 0x00030000
1363 #define SJA1105_CFG_PAD_MIIx_RX_D10_IPUD_PULL_UP 0x00000000
1364 #define SJA1105_CFG_PAD_MIIx_RX_D10_IPUD_REPEATER 0x00010000
1365 #define SJA1105_CFG_PAD_MIIx_RX_D10_IPUD_PLAIN 0x00020000
1366 #define SJA1105_CFG_PAD_MIIx_RX_D10_IPUD_PULL_DOWN 0x00030000
1367 #define SJA1105_CFG_PAD_MIIx_RX_CTRL_IH 0x00000400
1368 #define SJA1105_CFG_PAD_MIIx_RX_CTRL_IPUD 0x00000300
1369 #define SJA1105_CFG_PAD_MIIx_RX_CTRL_IPUD_PULL_UP 0x00000000
1370 #define SJA1105_CFG_PAD_MIIx_RX_CTRL_IPUD_REPEATER 0x00000100
1371 #define SJA1105_CFG_PAD_MIIx_RX_CTRL_IPUD_PLAIN 0x00000200
1372 #define SJA1105_CFG_PAD_MIIx_RX_CTRL_IPUD_PULL_DOWN 0x00000300
1373 #define SJA1105_CFG_PAD_MIIx_RX_CLK_OS 0x00000018
1374 #define SJA1105_CFG_PAD_MIIx_RX_CLK_OS_LOW 0x00000000
1375 #define SJA1105_CFG_PAD_MIIx_RX_CLK_OS_MEDIUM 0x00000008
1376 #define SJA1105_CFG_PAD_MIIx_RX_CLK_OS_FAST 0x00000010
1377 #define SJA1105_CFG_PAD_MIIx_RX_CLK_OS_HIGH 0x00000018
1378 #define SJA1105_CFG_PAD_MIIx_RX_CLK_IH 0x00000004
1379 #define SJA1105_CFG_PAD_MIIx_RX_CLK_IPUD 0x00000003
1380 #define SJA1105_CFG_PAD_MIIx_RX_CLK_IPUD_PULL_UP 0x00000000
1381 #define SJA1105_CFG_PAD_MIIx_RX_CLK_IPUD_REPEATER 0x00000001
1382 #define SJA1105_CFG_PAD_MIIx_RX_CLK_IPUD_PLAIN 0x00000002
1383 #define SJA1105_CFG_PAD_MIIx_RX_CLK_IPUD_PULL_DOWN 0x00000003
1384 
1385 //CFG_PAD_MIIx_ID register
1386 #define SJA1105_CFG_PAD_MIIx_ID_RXC_STABLE_OVR 0x00008000
1387 #define SJA1105_CFG_PAD_MIIx_ID_RXC_DELAY 0x00007C00
1388 #define SJA1105_CFG_PAD_MIIx_ID_RXC_DELAY_DEFAULT 0x00002000
1389 #define SJA1105_CFG_PAD_MIIx_ID_RXC_BYPASS 0x00000200
1390 #define SJA1105_CFG_PAD_MIIx_ID_RXC_PD 0x00000100
1391 #define SJA1105_CFG_PAD_MIIx_ID_TXC_STABLE_OVR 0x00000080
1392 #define SJA1105_CFG_PAD_MIIx_ID_TXC_DELAY 0x0000007C
1393 #define SJA1105_CFG_PAD_MIIx_ID_TXC_DELAY_DEFAULT 0x00000020
1394 #define SJA1105_CFG_PAD_MIIx_ID_TXC_BYPASS 0x00000002
1395 #define SJA1105_CFG_PAD_MIIx_ID_TXC_PD 0x00000001
1396 
1397 //CFG_PAD_MISC register
1398 #define SJA1105_CFG_PAD_MISC_PTPCLK_OS 0x00180000
1399 #define SJA1105_CFG_PAD_MISC_PTPCLK_OS_LOW 0x00000000
1400 #define SJA1105_CFG_PAD_MISC_PTPCLK_OS_MEDIUM 0x00080000
1401 #define SJA1105_CFG_PAD_MISC_PTPCLK_OS_FAST 0x00100000
1402 #define SJA1105_CFG_PAD_MISC_PTPCLK_OS_HIGH 0x00180000
1403 #define SJA1105_CFG_PAD_MISC_PTPCLK_IH 0x00040000
1404 #define SJA1105_CFG_PAD_MISC_PTPCLK_IPUD 0x00030000
1405 #define SJA1105_CFG_PAD_MISC_PTPCLK_IPUD_PULL_UP 0x00000000
1406 #define SJA1105_CFG_PAD_MISC_PTPCLK_IPUD_REPEATER 0x00010000
1407 #define SJA1105_CFG_PAD_MISC_PTPCLK_IPUD_PLAIN 0x00020000
1408 #define SJA1105_CFG_PAD_MISC_PTPCLK_IPUD_PULL_DOWN 0x00030000
1409 #define SJA1105_CFG_PAD_MISC_RSTN_IH 0x00000400
1410 #define SJA1105_CFG_PAD_MISC_RSTN_IPUD 0x00000300
1411 #define SJA1105_CFG_PAD_MISC_RSTN_IPUD_PULL_UP 0x00000000
1412 #define SJA1105_CFG_PAD_MISC_RSTN_IPUD_REPEATER 0x00000100
1413 #define SJA1105_CFG_PAD_MISC_RSTN_IPUD_PLAIN 0x00000200
1414 #define SJA1105_CFG_PAD_MISC_RSTN_IPUD_PULL_DOWN 0x00000300
1415 #define SJA1105_CFG_PAD_MISC_CLKOUT_EN 0x00000020
1416 #define SJA1105_CFG_PAD_MISC_CLKOUT_OS 0x00000018
1417 #define SJA1105_CFG_PAD_MISC_CLKOUT_OS_LOW 0x00000000
1418 #define SJA1105_CFG_PAD_MISC_CLKOUT_OS_MEDIUM 0x00000008
1419 #define SJA1105_CFG_PAD_MISC_CLKOUT_OS_FAST 0x00000010
1420 #define SJA1105_CFG_PAD_MISC_CLKOUT_OS_HIGH 0x00000018
1421 #define SJA1105_CFG_PAD_MISC_CLKOUT_IPUD 0x00000003
1422 #define SJA1105_CFG_PAD_MISC_CLKOUT_IPUD_PULL_UP 0x00000000
1423 #define SJA1105_CFG_PAD_MISC_CLKOUT_IPUD_REPEATER 0x00000001
1424 #define SJA1105_CFG_PAD_MISC_CLKOUT_IPUD_PLAIN 0x00000002
1425 #define SJA1105_CFG_PAD_MISC_CLKOUT_IPUD_PULL_DOWN 0x00000003
1426 
1427 //CFG_PAD_SPI register
1428 #define SJA1105_CFG_PAD_SPI_SDO_OS 0x18000000
1429 #define SJA1105_CFG_PAD_SPI_SDO_OS_LOW 0x00000000
1430 #define SJA1105_CFG_PAD_SPI_SDO_OS_MEDIUM 0x08000000
1431 #define SJA1105_CFG_PAD_SPI_SDO_OS_FAST 0x10000000
1432 #define SJA1105_CFG_PAD_SPI_SDO_OS_HIGH 0x18000000
1433 #define SJA1105_CFG_PAD_SPI_SDO_IPUD 0x03000000
1434 #define SJA1105_CFG_PAD_SPI_SDO_IPUD_PULL_UP 0x00000000
1435 #define SJA1105_CFG_PAD_SPI_SDO_IPUD_REPEATER 0x01000000
1436 #define SJA1105_CFG_PAD_SPI_SDO_IPUD_PLAIN 0x02000000
1437 #define SJA1105_CFG_PAD_SPI_SDO_IPUD_PULL_DOWN 0x03000000
1438 #define SJA1105_CFG_PAD_SPI_SDI_IH 0x00040000
1439 #define SJA1105_CFG_PAD_SPI_SDI_IPUD 0x00030000
1440 #define SJA1105_CFG_PAD_SPI_SDI_IPUD_PULL_UP 0x00000000
1441 #define SJA1105_CFG_PAD_SPI_SDI_IPUD_REPEATER 0x00010000
1442 #define SJA1105_CFG_PAD_SPI_SDI_IPUD_PLAIN 0x00020000
1443 #define SJA1105_CFG_PAD_SPI_SDI_IPUD_PULL_DOWN 0x00030000
1444 #define SJA1105_CFG_PAD_SPI_SSN_IH 0x00000400
1445 #define SJA1105_CFG_PAD_SPI_SSN_IPUD 0x00000300
1446 #define SJA1105_CFG_PAD_SPI_SSN_IPUD_PULL_UP 0x00000000
1447 #define SJA1105_CFG_PAD_SPI_SSN_IPUD_REPEATER 0x00000100
1448 #define SJA1105_CFG_PAD_SPI_SSN_IPUD_PLAIN 0x00000200
1449 #define SJA1105_CFG_PAD_SPI_SSN_IPUD_PULL_DOWN 0x00000300
1450 #define SJA1105_CFG_PAD_SPI_SCK_IH 0x00000004
1451 #define SJA1105_CFG_PAD_SPI_SCK_IH_PULL_UP 0x00000000
1452 #define SJA1105_CFG_PAD_SPI_SCK_IH_REPEATER 0x00000004
1453 #define SJA1105_CFG_PAD_SPI_SCK_IH_PLAIN 0x00000008
1454 #define SJA1105_CFG_PAD_SPI_SCK_IH_PULL_DOWN 0x0000000C
1455 
1456 //CFG_PAD_JTAG register
1457 #define SJA1105_CFG_PAD_JTAG_TDO_IPUD 0x03000000
1458 #define SJA1105_CFG_PAD_JTAG_TDO_IPUD_PULL_UP 0x00000000
1459 #define SJA1105_CFG_PAD_JTAG_TDO_IPUD_REPEATER 0x01000000
1460 #define SJA1105_CFG_PAD_JTAG_TDO_IPUD_PLAIN 0x02000000
1461 #define SJA1105_CFG_PAD_JTAG_TDO_IPUD_PULL_DOWN 0x03000000
1462 #define SJA1105_CFG_PAD_JTAG_TDI_IPUD 0x00030000
1463 #define SJA1105_CFG_PAD_JTAG_TDI_IPUD_PULL_UP 0x00000000
1464 #define SJA1105_CFG_PAD_JTAG_TDI_IPUD_REPEATER 0x00010000
1465 #define SJA1105_CFG_PAD_JTAG_TDI_IPUD_PLAIN 0x00020000
1466 #define SJA1105_CFG_PAD_JTAG_TDI_IPUD_PULL_DOWN 0x00030000
1467 #define SJA1105_CFG_PAD_JTAG_TRSTNTMS_IPUD 0x00000300
1468 #define SJA1105_CFG_PAD_JTAG_TRSTNTMS_IPUD_PULL_UP 0x00000000
1469 #define SJA1105_CFG_PAD_JTAG_TRSTNTMS_IPUD_REPEATER 0x00000100
1470 #define SJA1105_CFG_PAD_JTAG_TRSTNTMS_IPUD_PLAIN 0x00000200
1471 #define SJA1105_CFG_PAD_JTAG_TRSTNTMS_IPUD_PULL_DOWN 0x00000300
1472 #define SJA1105_CFG_PAD_JTAG_TCK_IPUD 0x00000003
1473 #define SJA1105_CFG_PAD_JTAG_TCK_IPUD_PULL_UP 0x00000000
1474 #define SJA1105_CFG_PAD_JTAG_TCK_IPUD_REPEATER 0x00000001
1475 #define SJA1105_CFG_PAD_JTAG_TCK_IPUD_PLAIN 0x00000002
1476 #define SJA1105_CFG_PAD_JTAG_TCK_IPUD_PULL_DOWN 0x00000003
1477 
1478 //PORT_STATUS_MIIx register
1479 #define SJA1105_PORT_STATUS_MIIx_RXC_ID_FREQ_MODE 0x00300000
1480 #define SJA1105_PORT_STATUS_MIIx_RXC_ID_FREQ_MODE_2_5MHZ 0x00000000
1481 #define SJA1105_PORT_STATUS_MIIx_RXC_ID_FREQ_MODE_25MHZ 0x00100000
1482 #define SJA1105_PORT_STATUS_MIIx_RXC_ID_FREQ_MODE_50MHZ 0x00200000
1483 #define SJA1105_PORT_STATUS_MIIx_RXC_ID_FREQ_MODE_125MHZ 0x00300000
1484 #define SJA1105_PORT_STATUS_MIIx_RXC_ID_CTL_MODE 0x000C0000
1485 #define SJA1105_PORT_STATUS_MIIx_RXC_ID_CTL_MODE_BYPASS 0x00000000
1486 #define SJA1105_PORT_STATUS_MIIx_RXC_ID_CTL_MODE_DELAYED 0x00040000
1487 #define SJA1105_PORT_STATUS_MIIx_RXC_ID_CTL_MODE_DISABLED 0x00080000
1488 #define SJA1105_PORT_STATUS_MIIx_RXC_ID_STABLE 0x00020000
1489 #define SJA1105_PORT_STATUS_MIIx_RXC_ID_PD 0x00010000
1490 #define SJA1105_PORT_STATUS_MIIx_TXC_ID_FREQ_MODE 0x00003000
1491 #define SJA1105_PORT_STATUS_MIIx_TXC_ID_FREQ_MODE_2_5MHZ 0x00000000
1492 #define SJA1105_PORT_STATUS_MIIx_TXC_ID_FREQ_MODE_25MHZ 0x00001000
1493 #define SJA1105_PORT_STATUS_MIIx_TXC_ID_FREQ_MODE_50MHZ 0x00002000
1494 #define SJA1105_PORT_STATUS_MIIx_TXC_ID_FREQ_MODE_125MHZ 0x00003000
1495 #define SJA1105_PORT_STATUS_MIIx_TXC_ID_CTL_MODE 0x00000C00
1496 #define SJA1105_PORT_STATUS_MIIx_TXC_ID_CTL_MODE_BYPASS 0x00000000
1497 #define SJA1105_PORT_STATUS_MIIx_TXC_ID_CTL_MODE_DELAYED 0x00000400
1498 #define SJA1105_PORT_STATUS_MIIx_TXC_ID_CTL_MODE_DISABLED 0x00000800
1499 #define SJA1105_PORT_STATUS_MIIx_TXC_ID_STABLE 0x00000200
1500 #define SJA1105_PORT_STATUS_MIIx_TXC_ID_PD 0x00000100
1501 #define SJA1105_PORT_STATUS_MIIx_SPEED 0x00000018
1502 #define SJA1105_PORT_STATUS_MIIx_SPEED_10MBPS 0x00000000
1503 #define SJA1105_PORT_STATUS_MIIx_SPEED_100MBPS 0x00000008
1504 #define SJA1105_PORT_STATUS_MIIx_SPEED_1GBPS 0x00000010
1505 #define SJA1105_PORT_STATUS_MIIx_MODE 0x00000007
1506 #define SJA1105_PORT_STATUS_MIIx_MODE_MII_MAC 0x00000000
1507 #define SJA1105_PORT_STATUS_MIIx_MODE_RMII_MAC 0x00000001
1508 #define SJA1105_PORT_STATUS_MIIx_MODE_MII_PHY 0x00000004
1509 #define SJA1105_PORT_STATUS_MIIx_MODE_RMII_PHY 0x00000005
1510 #define SJA1105_PORT_STATUS_MIIx_MODE_RGMII 0x00000002
1511 #define SJA1105_PORT_STATUS_MIIx_MODE_SGMII 0x00000003
1512 #define SJA1105_PORT_STATUS_MIIx_MODE_INACTIVE 0x00000007
1513 
1514 //TS_CONFIG register
1515 #define SJA1105_TS_CONFIG_PD 0x00000040
1516 #define SJA1105_TS_CONFIG_THRESHOLD 0x0000003F
1517 #define SJA1105_TS_CONFIG_THRESHOLD_DEFAULT 0x00000025
1518 
1519 //TS_STATUS register
1520 #define SJA1105_TS_STATUS_EXCEEDED 0x00000001
1521 
1522 //PROD_CFG register
1523 #define SJA1105_PROD_CFG_DISABLE_TTETH 0x00000001
1524 
1525 //PROD_ID register
1526 #define SJA1105_PROD_ID_PART_NR 0x000FFFF0
1527 #define SJA1105_PROD_ID_PART_NR_SJA1105P 0x0009A840
1528 #define SJA1105_PROD_ID_PART_NR_SJA1105Q 0x0009A850
1529 #define SJA1105_PROD_ID_PART_NR_SJA1105R 0x0009A860
1530 #define SJA1105_PROD_ID_PART_NR_SJA1105S 0x0009A870
1531 #define SJA1105_PROD_ID_VERSION 0x0000000F
1532 #define SJA1105_PROD_ID_VERSION_DEFAULT 0x00000001
1533 
1534 //ACU Unit Disable register
1535 #define SJA1105_ACU_UNIT_DISABLE_DISABLE_FLAG 0x00000001
1536 
1537 //BASIC_CONTROL register
1538 #define SJA1105_BASIC_CONTROL_RESET 0x8000
1539 #define SJA1105_BASIC_CONTROL_LOOPBACK 0x4000
1540 #define SJA1105_BASIC_CONTROL_SPEED_SEL_LSB 0x2000
1541 #define SJA1105_BASIC_CONTROL_AUTONEG_ENABLE 0x1000
1542 #define SJA1105_BASIC_CONTROL_POWER_DOWN 0x0800
1543 #define SJA1105_BASIC_CONTROL_RE_AUTONEG 0x0200
1544 #define SJA1105_BASIC_CONTROL_DUPLEX_MODE 0x0100
1545 #define SJA1105_BASIC_CONTROL_SPEED_SEL_MSB 0x0040
1546 
1547 //BASIC_STATUS register
1548 #define SJA1105_BASIC_STATUS_100BT4 0x8000
1549 #define SJA1105_BASIC_STATUS_100BTX_FD 0x4000
1550 #define SJA1105_BASIC_STATUS_100BTX_HD 0x2000
1551 #define SJA1105_BASIC_STATUS_10BT_FD 0x1000
1552 #define SJA1105_BASIC_STATUS_10BT_HD 0x0800
1553 #define SJA1105_BASIC_STATUS_100BT2_FD 0x0400
1554 #define SJA1105_BASIC_STATUS_100BT2_HD 0x0200
1555 #define SJA1105_BASIC_STATUS_EXTENDED_STATUS 0x0100
1556 #define SJA1105_BASIC_STATUS_UNIDIRECT_ABILITY 0x0080
1557 #define SJA1105_BASIC_STATUS_MF_PREAMBLE_SUPPR 0x0040
1558 #define SJA1105_BASIC_STATUS_AUTONEG_COMPLETE 0x0020
1559 #define SJA1105_BASIC_STATUS_REMOTE_FAULT 0x0010
1560 #define SJA1105_BASIC_STATUS_AUTONEG_ABILITY 0x0008
1561 #define SJA1105_BASIC_STATUS_LINK_STATUS 0x0004
1562 #define SJA1105_BASIC_STATUS_EXTENDED_CAPABILITY 0x0001
1563 
1564 //PHY_IDENTIFIER_1 register
1565 #define SJA1105_PHY_IDENTIFIER_1_PHY_ID_MSB 0xFFFF
1566 #define SJA1105_PHY_IDENTIFIER_1_PHY_ID_MSB_DEFAULT 0xB018
1567 
1568 //PHY_IDENTIFIER_2 register
1569 #define SJA1105_PHY_IDENTIFIER_2_PHY_ID_LSB 0xFC00
1570 #define SJA1105_PHY_IDENTIFIER_2_PHY_ID_LSB_DEFAULT 0x0000
1571 #define SJA1105_PHY_IDENTIFIER_2_TYPE_NO 0x03F0
1572 #define SJA1105_PHY_IDENTIFIER_2_TYPE_NO_DEFAULT 0x02D0
1573 #define SJA1105_PHY_IDENTIFIER_2_REVISION_NO 0x000F
1574 #define SJA1105_PHY_IDENTIFIER_2_REVISION_NO_DEFAULT 0x0000
1575 
1576 //C++ guard
1577 #ifdef __cplusplus
1578 extern "C" {
1579 #endif
1580 
1581 //SJA1105 Ethernet switch driver
1582 extern const SwitchDriver sja1105SwitchDriver;
1583 
1584 //SJA1105 related functions
1585 error_t sja1105Init(NetInterface *interface);
1587 
1589  size_t length);
1590 
1591 void sja1105ConfigurePll1(NetInterface *interface);
1592 error_t sja1105ConfigureCgu(NetInterface *interface, uint8_t port);
1593 
1594 void sja1105Tick(NetInterface *interface);
1595 
1596 void sja1105EnableIrq(NetInterface *interface);
1597 void sja1105DisableIrq(NetInterface *interface);
1598 
1599 void sja1105EventHandler(NetInterface *interface);
1600 
1601 error_t sja1105TagFrame(NetInterface *interface, NetBuffer *buffer,
1602  size_t *offset, NetTxAncillary *ancillary);
1603 
1604 error_t sja1105UntagFrame(NetInterface *interface, uint8_t **frame,
1605  size_t *length, NetRxAncillary *ancillary);
1606 
1607 bool_t sja1105GetLinkState(NetInterface *interface, uint8_t port);
1608 uint32_t sja1105GetLinkSpeed(NetInterface *interface, uint8_t port);
1610 
1611 void sja1105SetPortSpeed(NetInterface *interface, uint8_t port, uint32_t speed);
1612 
1613 void sja1105SetPortState(NetInterface *interface, uint8_t port,
1614  SwitchPortState state);
1615 
1617 
1618 void sja1105SetAgingTime(NetInterface *interface, uint32_t agingTime);
1619 
1620 void sja1105EnableIgmpSnooping(NetInterface *interface, bool_t enable);
1621 void sja1105EnableMldSnooping(NetInterface *interface, bool_t enable);
1622 void sja1105EnableRsvdMcastTable(NetInterface *interface, bool_t enable);
1623 
1625  const SwitchFdbEntry *entry);
1626 
1628  const SwitchFdbEntry *entry);
1629 
1631  SwitchFdbEntry *entry);
1632 
1633 void sja1105FlushStaticFdbTable(NetInterface *interface);
1634 
1636  SwitchFdbEntry *entry);
1637 
1638 void sja1105FlushDynamicFdbTable(NetInterface *interface, uint8_t port);
1639 
1641  bool_t enable, uint32_t forwardPorts);
1642 
1644 error_t sja1105ReadMacConfigEntry(NetInterface *interface, uint8_t port);
1645 
1646 void sja1105WriteSingleReg(NetInterface *interface, uint32_t address,
1647  uint32_t data);
1648 
1649 uint32_t sja1105ReadSingleReg(NetInterface *interface, uint32_t address);
1650 
1651 void sja1105WriteMultipleRegs(NetInterface *interface, uint32_t address,
1652  const uint32_t *data, uint_t count);
1653 
1654 void sja1105ReadMultipleRegs(NetInterface *interface, uint32_t address,
1655  uint32_t *data, uint_t count);
1656 
1657 void sja1105DumpReg(NetInterface *interface);
1658 
1659 void sja1105WritePhyReg(NetInterface *interface, uint8_t phyAddr,
1660  uint8_t regAddr, uint16_t data);
1661 
1662 uint16_t sja1105ReadPhyReg(NetInterface *interface, uint8_t phyAddr,
1663  uint8_t regAddr);
1664 
1665 void sja1105DumpPhyReg(NetInterface *interface, uint8_t phyAddr);
1666 
1667 //C++ guard
1668 #ifdef __cplusplus
1669 }
1670 #endif
1671 
1672 #endif
void sja1105SetPortState(NetInterface *interface, uint8_t port, SwitchPortState state)
Set port state.
int bool_t
Definition: compiler_port.h:53
error_t sja1105GetDynamicFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the dynamic MAC table.
void sja1105SetPortSpeed(NetInterface *interface, uint8_t port, uint32_t speed)
Reconfigure port speed.
void sja1105ConfigurePll1(NetInterface *interface)
PLL1 setup for 50MHz.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
error_t sja1105GetStaticFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the static MAC table.
error_t sja1105WriteMacConfigEntry(NetInterface *interface, uint8_t port)
Reconfigure an entry in the MAC configuration table.
error_t sja1105LoadStaticConfig(NetInterface *interface, const char_t *data, size_t length)
Load static configuration into the device.
uint8_t data[]
Definition: ethernet.h:222
void sja1105WriteSingleReg(NetInterface *interface, uint32_t address, uint32_t data)
Write a single register.
error_t sja1105InitHook(NetInterface *interface)
SJA1105 custom configuration.
void sja1105EnableRsvdMcastTable(NetInterface *interface, bool_t enable)
Enable reserved multicast table.
error_t sja1105DeleteStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Remove an entry from the static MAC table.
void sja1105Tick(NetInterface *interface)
SJA1105 timer handler.
void sja1105SetUnknownMcastFwdPorts(NetInterface *interface, bool_t enable, uint32_t forwardPorts)
Set forward ports for unknown multicast packets.
void sja1105WritePhyReg(NetInterface *interface, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t sja1105AddStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Add a new entry to the static MAC table.
const SwitchDriver sja1105SwitchDriver
SJA1105 Ethernet switch driver.
error_t
Error codes.
Definition: error.h:43
void sja1105ReadMultipleRegs(NetInterface *interface, uint32_t address, uint32_t *data, uint_t count)
Read multiple registers.
SwitchPortState sja1105GetPortState(NetInterface *interface, uint8_t port)
Get port state.
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
uint32_t sja1105ReadSingleReg(NetInterface *interface, uint32_t address)
Read a single register.
void sja1105DisableIrq(NetInterface *interface)
Disable interrupts.
void sja1105EnableIrq(NetInterface *interface)
Enable interrupts.
#define NetTxAncillary
Definition: net_misc.h:36
SwitchPortState
Switch port state.
Definition: nic.h:134
uint8_t length
Definition: tcp.h:368
void sja1105EnableIgmpSnooping(NetInterface *interface, bool_t enable)
Enable IGMP snooping.
uint16_t port
Definition: dns_common.h:267
error_t sja1105ReadMacConfigEntry(NetInterface *interface, uint8_t port)
Read an entry from the MAC configuration table.
void sja1105FlushDynamicFdbTable(NetInterface *interface, uint8_t port)
Flush dynamic MAC table.
char char_t
Definition: compiler_port.h:48
error_t sja1105UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, NetRxAncillary *ancillary)
Decode tail tag from incoming Ethernet frame.
void sja1105DumpReg(NetInterface *interface)
Dump registers for debugging purpose.
uint16_t regAddr
Ethernet switch driver.
Definition: nic.h:325
NicDuplexMode sja1105GetDuplexMode(NetInterface *interface, uint8_t port)
Get duplex mode.
uint16_t sja1105ReadPhyReg(NetInterface *interface, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Ipv6Addr address[]
Definition: ipv6.h:325
NicDuplexMode
Duplex mode.
Definition: nic.h:122
Network interface controller abstraction layer.
void sja1105WriteMultipleRegs(NetInterface *interface, uint32_t address, const uint32_t *data, uint_t count)
Write multiple registers.
void sja1105DumpPhyReg(NetInterface *interface, uint8_t phyAddr)
Dump PHY registers for debugging purpose.
error_t sja1105ConfigureCgu(NetInterface *interface, uint8_t port)
Clock generation unit setup.
void sja1105SetAgingTime(NetInterface *interface, uint32_t agingTime)
Set aging time for dynamic filtering entries.
bool_t sja1105GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void sja1105EventHandler(NetInterface *interface)
SJA1105 event handler.
error_t sja1105TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, NetTxAncillary *ancillary)
Add tail tag to Ethernet frame.
unsigned int uint_t
Definition: compiler_port.h:50
uint32_t sja1105GetLinkSpeed(NetInterface *interface, uint8_t port)
Get link speed.
void sja1105EnableMldSnooping(NetInterface *interface, bool_t enable)
Enable MLD snooping.
error_t sja1105Init(NetInterface *interface)
SJA1105 Ethernet switch initialization.
Forwarding database entry.
Definition: nic.h:149
void sja1105FlushStaticFdbTable(NetInterface *interface)
Flush static MAC table.