upd60611_driver.h
Go to the documentation of this file.
1 /**
2  * @file upd60611_driver.h
3  * @brief uPD60611 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _UPD60611_DRIVER_H
30 #define _UPD60611_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef UPD60611_PHY_ADDR
37  #define UPD60611_PHY_ADDR 0
38 #elif (UPD60611_PHY_ADDR < 0 || UPD60611_PHY_ADDR > 31)
39  #error UPD60611_PHY_ADDR parameter is not valid
40 #endif
41 
42 //uPD60611 registers
43 #define UPD60611_PHY_REG_BMCR 0x00
44 #define UPD60611_PHY_REG_BMSR 0x01
45 #define UPD60611_PHY_REG_PHYIDR1 0x02
46 #define UPD60611_PHY_REG_PHYIDR2 0x03
47 #define UPD60611_PHY_REG_ANAR 0x04
48 #define UPD60611_PHY_REG_ANLPAR 0x05
49 #define UPD60611_PHY_REG_ANER 0x06
50 #define UPD60611_PHY_REG_ANNPTR 0x07
51 #define UPD60611_PHY_REG_SRR 0x10
52 #define UPD60611_PHY_REG_MCSR 0x11
53 #define UPD60611_PHY_REG_SMR 0x12
54 #define UPD60611_PHY_REG_EBSR 0x13
55 #define UPD60611_PHY_REG_BER 0x17
56 #define UPD60611_PHY_REG_FEQMR 0x18
57 #define UPD60611_PHY_REG_DCSR 0x19
58 #define UPD60611_PHY_REG_DCR 0x1A
59 #define UPD60611_PHY_REG_SCSIR 0x1B
60 #define UPD60611_PHY_REG_ISR 0x1D
61 #define UPD60611_PHY_REG_IER 0x1E
62 #define UPD60611_PHY_REG_PSCSR 0x1F
63 
64 //BMCR register
65 #define BMCR_RESET (1 << 15)
66 #define BMCR_LOOPBACK (1 << 14)
67 #define BMCR_SPEED_SEL (1 << 13)
68 #define BMCR_AN_EN (1 << 12)
69 #define BMCR_POWER_DOWN (1 << 11)
70 #define BMCR_ISOLATE (1 << 10)
71 #define BMCR_RESTART_AN (1 << 9)
72 #define BMCR_DUPLEX_MODE (1 << 8)
73 #define BMCR_COL_TEST (1 << 7)
74 
75 //BMSR register
76 #define BMSR_100BT4 (1 << 15)
77 #define BMSR_100BTX_FD (1 << 14)
78 #define BMSR_100BTX (1 << 13)
79 #define BMSR_10BT_FD (1 << 12)
80 #define BMSR_10BT (1 << 11)
81 #define BMSR_AN_COMPLETE (1 << 5)
82 #define BMSR_REMOTE_FAULT (1 << 4)
83 #define BMSR_AN_ABLE (1 << 3)
84 #define BMSR_LINK_STATUS (1 << 2)
85 #define BMSR_JABBER_DETECT (1 << 1)
86 #define BMSR_EXTENDED_CAP (1 << 0)
87 
88 //ANAR register
89 #define ANAR_NP (1 << 15)
90 #define ANAR_RF (1 << 13)
91 #define ANAR_PAUSE1 (1 << 11)
92 #define ANAR_PAUSE0 (1 << 10)
93 #define ANAR_100BT4 (1 << 9)
94 #define ANAR_100BTX_FD (1 << 8)
95 #define ANAR_100BTX (1 << 7)
96 #define ANAR_10BT_FD (1 << 6)
97 #define ANAR_10BT (1 << 5)
98 #define ANAR_SELECTOR4 (1 << 4)
99 #define ANAR_SELECTOR3 (1 << 3)
100 #define ANAR_SELECTOR2 (1 << 2)
101 #define ANAR_SELECTOR1 (1 << 1)
102 #define ANAR_SELECTOR0 (1 << 0)
103 
104 //ANLPAR register
105 #define ANLPAR_NP (1 << 15)
106 #define ANLPAR_ACK (1 << 14)
107 #define ANLPAR_RF (1 << 13)
108 #define ANLPAR_PAUSE (1 << 10)
109 #define ANLPAR_100BT4 (1 << 9)
110 #define ANLPAR_100BTX_FD (1 << 8)
111 #define ANLPAR_100BTX (1 << 7)
112 #define ANLPAR_10BT_FD (1 << 6)
113 #define ANLPAR_10BT (1 << 5)
114 #define ANLPAR_SELECTOR4 (1 << 4)
115 #define ANLPAR_SELECTOR3 (1 << 3)
116 #define ANLPAR_SELECTOR2 (1 << 2)
117 #define ANLPAR_SELECTOR1 (1 << 1)
118 #define ANLPAR_SELECTOR0 (1 << 0)
119 
120 //ANER register
121 #define ANER_PDF (1 << 4)
122 #define ANER_LP_NP_ABLE (1 << 3)
123 #define ANER_NP_ABLE (1 << 2)
124 #define ANER_PAGE_RX (1 << 1)
125 #define ANER_LP_AN_ABLE (1 << 0)
126 
127 //ANNPTR register
128 #define ANNPTR_NP (1 << 15)
129 #define ANNPTR_MP (1 << 13)
130 #define ANNPTR_ACK2 (1 << 12)
131 #define ANNPTR_TOGGLE (1 << 11)
132 #define ANNPTR_CODE10 (1 << 10)
133 #define ANNPTR_CODE9 (1 << 9)
134 #define ANNPTR_CODE8 (1 << 8)
135 #define ANNPTR_CODE7 (1 << 7)
136 #define ANNPTR_CODE6 (1 << 6)
137 #define ANNPTR_CODE5 (1 << 5)
138 #define ANNPTR_CODE4 (1 << 4)
139 #define ANNPTR_CODE3 (1 << 3)
140 #define ANNPTR_CODE2 (1 << 2)
141 #define ANNPTR_CODE1 (1 << 1)
142 #define ANNPTR_CODE0 (1 << 0)
143 
144 //MCSR register
145 #define MCSR_EDPWRDOWN (1 << 13)
146 #define MCSR_FARLOOPBACK (1 << 9)
147 #define MCSR_FASTEST (1 << 8)
148 #define MCSR_AUTOMDIX_EN (1 << 7)
149 #define MCSR_MDI MODE (1 << 6)
150 #define MCSR_FORCE_GOOD_LINK (1 << 2)
151 #define MCSR_ENERGYON (1 << 1)
152 
153 //SMR register
154 #define SMR_FX_MODE (1 << 10)
155 #define SMR_PHY_MODE3 (1 << 8)
156 #define SMR_PHY_MODE2 (1 << 7)
157 #define SMR_PHY_MODE1 (1 << 6)
158 #define SMR_PHY_MODE0 (1 << 5)
159 #define SMR_PHY_ADD_DEV1 (1 << 4)
160 #define SMR_PHY_ADD_DEV0 (1 << 3)
161 #define SMR_PHY_ADD_MOD2 (1 << 2)
162 #define SMR_PHY_ADD_MOD1 (1 << 1)
163 #define SMR_PHY_ADD_MOD0 (1 << 0)
164 
165 //EBSR register
166 #define EBSR_T_EL_BUF_OVF (1 << 7)
167 #define EBSR_T_EL_BUF_UDF (1 << 6)
168 #define EBSR_R_EL_BUF_OVF (1 << 5)
169 #define EBSR_R_EL_BUF_UDF (1 << 4)
170 
171 //BER register
172 #define BER_LNK_OK (1 << 15)
173 #define BER_CNT_LNK_EN (1 << 14)
174 #define BER_CNT_TRIG2 (1 << 13)
175 #define BER_CNT_TRIG1 (1 << 12)
176 #define BER_CNT_TRIG0 (1 << 11)
177 #define BER_WINDOW3 (1 << 10)
178 #define BER_WINDOW2 (1 << 9)
179 #define BER_WINDOW1 (1 << 8)
180 #define BER_WINDOW0 (1 << 7)
181 #define BER_COUNT6 (1 << 6)
182 #define BER_COUNT5 (1 << 5)
183 #define BER_COUNT4 (1 << 4)
184 #define BER_COUNT3 (1 << 3)
185 #define BER_COUNT2 (1 << 2)
186 #define BER_COUNT1 (1 << 1)
187 #define BER_COUNT0 (1 << 0)
188 
189 //DCSR register
190 #define DCSR_DIAG_INIT (1 << 14)
191 #define DCSR_ADC_MAX_VALUE5 (1 << 13)
192 #define DCSR_ADC_MAX_VALUE4 (1 << 12)
193 #define DCSR_ADC_MAX_VALUE3 (1 << 11)
194 #define DCSR_ADC_MAX_VALUE2 (1 << 10)
195 #define DCSR_ADC_MAX_VALUE1 (1 << 9)
196 #define DCSR_ADC_MAX_VALUE0 (1 << 8)
197 #define DCSR_DIAG_DONE (1 << 7)
198 #define DCSR_DIAG_POL (1 << 6)
199 #define DCSR_DIAG_SEL_LINE (1 << 5)
200 #define DCSR_PW_DIAG4 (1 << 4)
201 #define DCSR_PW_DIAG3 (1 << 3)
202 #define DCSR_PW_DIAG2 (1 << 2)
203 #define DCSR_PW_DIAG1 (1 << 1)
204 #define DCSR_PW_DIAG0 (1 << 0)
205 
206 //DCR register
207 #define DCR_CNT_WINDOW7 (1 << 15)
208 #define DCR_CNT_WINDOW6 (1 << 14)
209 #define DCR_CNT_WINDOW5 (1 << 13)
210 #define DCR_CNT_WINDOW4 (1 << 12)
211 #define DCR_CNT_WINDOW3 (1 << 11)
212 #define DCR_CNT_WINDOW2 (1 << 10)
213 #define DCR_CNT_WINDOW1 (1 << 9)
214 #define DCR_CNT_WINDOW0 (1 << 8)
215 #define DCR_DIAGCNT7 (1 << 7)
216 #define DCR_DIAGCNT6 (1 << 6)
217 #define DCR_DIAGCNT5 (1 << 5)
218 #define DCR_DIAGCNT4 (1 << 4)
219 #define DCR_DIAGCNT3 (1 << 3)
220 #define DCR_DIAGCNT2 (1 << 2)
221 #define DCR_DIAGCNT1 (1 << 1)
222 #define DCR_DIAGCNT0 (1 << 0)
223 
224 //SCSIR register
225 #define SCSIR_SWRST_FAST (1 << 12)
226 #define SCSIR_SQEOFF (1 << 11)
227 #define SCSIR_FEFIEN (1 << 5)
228 #define SCSIR_XPOL (1 << 4)
229 
230 //ISR register
231 #define ISR_BER (1 << 10)
232 #define ISR_FEQ (1 << 9)
233 #define ISR_ENERGYON (1 << 7)
234 #define ISR_AN_COMPLETE (1 << 6)
235 #define ISR_REMOTE_FAULT (1 << 5)
236 #define ISR_LINK_DOWN (1 << 4)
237 #define ISR_AN_LP_ACK (1 << 3)
238 #define ISR_PD_FAULT (1 << 2)
239 #define ISR_AN_PAGE_RECEIVED (1 << 1)
240 
241 //IER register
242 #define IER_BER (1 << 10)
243 #define IER_FEQ (1 << 9)
244 #define IER_ENERGYON (1 << 7)
245 #define IER_AN_COMPLETE (1 << 6)
246 #define IER_REMOTE_FAULT (1 << 5)
247 #define IER_LINK_DOWN (1 << 4)
248 #define IER_AN_LP_ACK (1 << 3)
249 #define IER_PD_FAULT (1 << 2)
250 #define IER_AN_PAGE_RECEIVED (1 << 1)
251 
252 //PSCSR register
253 #define PSCSR_AUTODONE (1 << 12)
254 #define PSCSR_ENABLE_4B5B (1 << 6)
255 #define PSCSR_HCDSPEED2 (1 << 4)
256 #define PSCSR_HCDSPEED1 (1 << 3)
257 #define PSCSR_HCDSPEED0 (1 << 2)
258 #define PSCSR_RX_DV_J2T (1 << 1)
259 #define PSCSR_SCRAMBLE_DIS (1 << 0)
260 
261 //Speed indication
262 #define PSCSR_HCDSPEED_MASK (7 << 2)
263 #define PSCSR_HCDSPEED_10BT (1 << 2)
264 #define PSCSR_HCDSPEED_100BTX (2 << 2)
265 #define PSCSR_HCDSPEED_10BT_FD (5 << 2)
266 #define PSCSR_HCDSPEED_100BTX_FD (6 << 2)
267 
268 //C++ guard
269 #ifdef __cplusplus
270  extern "C" {
271 #endif
272 
273 //uPD60611 Ethernet PHY driver
274 extern const PhyDriver upd60611PhyDriver;
275 
276 //uPD60611 related functions
277 error_t upd60611Init(NetInterface *interface);
278 
279 void upd60611Tick(NetInterface *interface);
280 
281 void upd60611EnableIrq(NetInterface *interface);
282 void upd60611DisableIrq(NetInterface *interface);
283 
284 void upd60611EventHandler(NetInterface *interface);
285 
286 void upd60611WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
287 uint16_t upd60611ReadPhyReg(NetInterface *interface, uint8_t address);
288 
289 void upd60611DumpPhyReg(NetInterface *interface);
290 
291 //C++ guard
292 #ifdef __cplusplus
293  }
294 #endif
295 
296 #endif
const PhyDriver upd60611PhyDriver
uPD60611 Ethernet PHY driver
void upd60611EventHandler(NetInterface *interface)
uPD60611 event handler
void upd60611EnableIrq(NetInterface *interface)
Enable interrupts.
PHY driver.
Definition: nic.h:196
void upd60611WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
void upd60611DisableIrq(NetInterface *interface)
Disable interrupts.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
void upd60611Tick(NetInterface *interface)
uPD60611 timer handler
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void upd60611DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
error_t upd60611Init(NetInterface *interface)
uPD60611 PHY transceiver initialization
uint16_t upd60611ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
Network interface controller abstraction layer.