w6100_driver.h
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1 /**
2  * @file w6100_driver.h
3  * @brief WIZnet W6100 Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.4
29  **/
30 
31 #ifndef _W6100_DRIVER_H
32 #define _W6100_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //TX buffer size
38 #ifndef W6100_ETH_TX_BUFFER_SIZE
39  #define W6100_ETH_TX_BUFFER_SIZE 1536
40 #elif (W6100_ETH_TX_BUFFER_SIZE != 1536)
41  #error W6100_ETH_TX_BUFFER_SIZE parameter is not valid
42 #endif
43 
44 //RX buffer size
45 #ifndef W6100_ETH_RX_BUFFER_SIZE
46  #define W6100_ETH_RX_BUFFER_SIZE 1536
47 #elif (W6100_ETH_RX_BUFFER_SIZE != 1536)
48  #error W6100_ETH_RX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Control byte
52 #define W6100_CTRL_BSB 0xF8
53 #define W6100_CTRL_BSB_COMMON_REG 0x00
54 #define W6100_CTRL_BSB_S0_REG 0x08
55 #define W6100_CTRL_BSB_S0_TX_BUFFER 0x10
56 #define W6100_CTRL_BSB_S0_RX_BUFFER 0x18
57 #define W6100_CTRL_BSB_S1_REG 0x28
58 #define W6100_CTRL_BSB_S1_TX_BUFFER 0x30
59 #define W6100_CTRL_BSB_S1_RX_BUFFER 0x38
60 #define W6100_CTRL_BSB_S2_REG 0x48
61 #define W6100_CTRL_BSB_S2_TX_BUFFER 0x50
62 #define W6100_CTRL_BSB_S2_RX_BUFFER 0x58
63 #define W6100_CTRL_BSB_S3_REG 0x68
64 #define W6100_CTRL_BSB_S3_TX_BUFFER 0x70
65 #define W6100_CTRL_BSB_S3_RX_BUFFER 0x78
66 #define W6100_CTRL_BSB_S4_REG 0x88
67 #define W6100_CTRL_BSB_S4_TX_BUFFER 0x90
68 #define W6100_CTRL_BSB_S4_RX_BUFFER 0x98
69 #define W6100_CTRL_BSB_S5_REG 0xA8
70 #define W6100_CTRL_BSB_S5_TX_BUFFER 0xB0
71 #define W6100_CTRL_BSB_S5_RX_BUFFER 0xB8
72 #define W6100_CTRL_BSB_S6_REG 0xC8
73 #define W6100_CTRL_BSB_S6_TX_BUFFER 0xD0
74 #define W6100_CTRL_BSB_S6_RX_BUFFER 0xD8
75 #define W6100_CTRL_BSB_S7_REG 0xE8
76 #define W6100_CTRL_BSB_S7_TX_BUFFER 0xF0
77 #define W6100_CTRL_BSB_S7_RX_BUFFER 0xF8
78 #define W6100_CTRL_RWB 0x04
79 #define W6100_CTRL_RWB_READ 0x00
80 #define W6100_CTRL_RWB_WRITE 0x04
81 #define W6100_CTRL_OM 0x03
82 #define W6100_CTRL_OM_VDM 0x00
83 #define W6100_CTRL_OM_FDM1 0x01
84 #define W6100_CTRL_OM_FDM2 0x02
85 #define W6100_CTRL_OM_FDM4 0x03
86 
87 //Common register block
88 #define W6100_CIDR0 0x0000
89 #define W6100_CIDR1 0x0001
90 #define W6100_VER0 0x0002
91 #define W6100_VER1 0x0003
92 #define W6100_SYSR 0x2000
93 #define W6100_SYCR0 0x2004
94 #define W6100_SYCR1 0x2005
95 #define W6100_TCNTR0 0x2016
96 #define W6100_TCNTR1 0x2017
97 #define W6100_TCNTCLR 0x2020
98 #define W6100_IR 0x2100
99 #define W6100_SIR 0x2101
100 #define W6100_SLIR 0x2102
101 #define W6100_IMR 0x2104
102 #define W6100_IRCLR 0x2108
103 #define W6100_SIMR 0x2114
104 #define W6100_SLIMR 0x2124
105 #define W6100_SLIRCLR 0x2128
106 #define W6100_SLPSR 0x212C
107 #define W6100_SLCR 0x2130
108 #define W6100_PHYSR 0x3000
109 #define W6100_PHYRAR 0x3008
110 #define W6100_PHYDIR0 0x300C
111 #define W6100_PHYDIR1 0x300D
112 #define W6100_PHYDOR0 0x3010
113 #define W6100_PHYDOR1 0x3011
114 #define W6100_PHYACR 0x3014
115 #define W6100_PHYDIVR 0x3018
116 #define W6100_PHYCR0 0x301C
117 #define W6100_PHYCR1 0x301D
118 #define W6100_NET4MR 0x4000
119 #define W6100_NET6MR 0x4004
120 #define W6100_NETMR 0x4008
121 #define W6100_NETMR2 0x4009
122 #define W6100_PTMR 0x4100
123 #define W6100_PMNR 0x4104
124 #define W6100_PHAR0 0x4108
125 #define W6100_PHAR1 0x4109
126 #define W6100_PHAR2 0x410A
127 #define W6100_PHAR3 0x410B
128 #define W6100_PHAR4 0x410C
129 #define W6100_PHAR5 0x410D
130 #define W6100_PSIDR0 0x4110
131 #define W6100_PSIDR1 0x4111
132 #define W6100_PMRUR0 0x4114
133 #define W6100_PMRUR1 0x4115
134 #define W6100_SHAR0 0x4120
135 #define W6100_SHAR1 0x4121
136 #define W6100_SHAR2 0x4122
137 #define W6100_SHAR3 0x4123
138 #define W6100_SHAR4 0x4124
139 #define W6100_SHAR5 0x4125
140 #define W6100_GAR0 0x4130
141 #define W6100_GAR1 0x4131
142 #define W6100_GAR2 0x4132
143 #define W6100_GAR3 0x4133
144 #define W6100_SUBR0 0x4134
145 #define W6100_SUBR1 0x4135
146 #define W6100_SUBR2 0x4136
147 #define W6100_SUBR3 0x4137
148 #define W6100_SIPR0 0x4138
149 #define W6100_SIPR1 0x4139
150 #define W6100_SIPR2 0x413A
151 #define W6100_SIPR3 0x413B
152 #define W6100_LLAR0 0x4140
153 #define W6100_LLAR1 0x4141
154 #define W6100_LLAR2 0x4142
155 #define W6100_LLAR3 0x4143
156 #define W6100_LLAR4 0x4144
157 #define W6100_LLAR5 0x4145
158 #define W6100_LLAR6 0x4146
159 #define W6100_LLAR7 0x4147
160 #define W6100_LLAR8 0x4148
161 #define W6100_LLAR9 0x4149
162 #define W6100_LLAR10 0x414A
163 #define W6100_LLAR11 0x414B
164 #define W6100_LLAR12 0x414C
165 #define W6100_LLAR13 0x414D
166 #define W6100_LLAR14 0x414E
167 #define W6100_LLAR15 0x414F
168 #define W6100_GUAR0 0x4150
169 #define W6100_GUAR1 0x4151
170 #define W6100_GUAR2 0x4152
171 #define W6100_GUAR3 0x4153
172 #define W6100_GUAR4 0x4154
173 #define W6100_GUAR5 0x4155
174 #define W6100_GUAR6 0x4156
175 #define W6100_GUAR7 0x4157
176 #define W6100_GUAR8 0x4158
177 #define W6100_GUAR9 0x4159
178 #define W6100_GUAR10 0x415A
179 #define W6100_GUAR11 0x415B
180 #define W6100_GUAR12 0x415C
181 #define W6100_GUAR13 0x415D
182 #define W6100_GUAR14 0x415E
183 #define W6100_GUAR15 0x415F
184 #define W6100_SUB6R0 0x4160
185 #define W6100_SUB6R1 0x4161
186 #define W6100_SUB6R2 0x4162
187 #define W6100_SUB6R3 0x4163
188 #define W6100_SUB6R4 0x4164
189 #define W6100_SUB6R5 0x4165
190 #define W6100_SUB6R6 0x4166
191 #define W6100_SUB6R7 0x4167
192 #define W6100_SUB6R8 0x4168
193 #define W6100_SUB6R9 0x4169
194 #define W6100_SUB6R10 0x416A
195 #define W6100_SUB6R11 0x416B
196 #define W6100_SUB6R12 0x416C
197 #define W6100_SUB6R13 0x416D
198 #define W6100_SUB6R14 0x416E
199 #define W6100_SUB6R15 0x416F
200 #define W6100_GA6R0 0x4170
201 #define W6100_GA6R1 0x4171
202 #define W6100_GA6R2 0x4172
203 #define W6100_GA6R3 0x4173
204 #define W6100_GA6R4 0x4174
205 #define W6100_GA6R5 0x4175
206 #define W6100_GA6R6 0x4176
207 #define W6100_GA6R7 0x4177
208 #define W6100_GA6R8 0x4178
209 #define W6100_GA6R9 0x4179
210 #define W6100_GA6R10 0x417A
211 #define W6100_GA6R11 0x417B
212 #define W6100_GA6R12 0x417C
213 #define W6100_GA6R13 0x417D
214 #define W6100_GA6R14 0x417E
215 #define W6100_GA6R15 0x417F
216 #define W6100_SLDIP6R0 0x4180
217 #define W6100_SLDIP6R1 0x4181
218 #define W6100_SLDIP6R2 0x4182
219 #define W6100_SLDIP6R3 0x4183
220 #define W6100_SLDIP6R4 0x4184
221 #define W6100_SLDIP6R5 0x4185
222 #define W6100_SLDIP6R6 0x4186
223 #define W6100_SLDIP6R7 0x4187
224 #define W6100_SLDIP6R8 0x4188
225 #define W6100_SLDIP6R9 0x4189
226 #define W6100_SLDIP6R10 0x418A
227 #define W6100_SLDIP6R11 0x418B
228 #define W6100_SLDIP6R12 0x418C
229 #define W6100_SLDIP6R13 0x418D
230 #define W6100_SLDIP6R14 0x418E
231 #define W6100_SLDIP6R15 0x418F
232 #define W6100_SLDHAR0 0x4190
233 #define W6100_SLDHAR1 0x4191
234 #define W6100_SLDHAR2 0x4192
235 #define W6100_SLDHAR3 0x4193
236 #define W6100_SLDHAR4 0x4194
237 #define W6100_SLDHAR5 0x4195
238 #define W6100_PINGIDR0 0x4198
239 #define W6100_PINGIDR1 0x4199
240 #define W6100_PINGSEQR0 0x419C
241 #define W6100_PINGSEQR1 0x419D
242 #define W6100_UIPR0 0x41A0
243 #define W6100_UIPR1 0x41A1
244 #define W6100_UIPR2 0x41A2
245 #define W6100_UIPR3 0x41A3
246 #define W6100_UPORTR0 0x41A4
247 #define W6100_UPORTR1 0x41A5
248 #define W6100_UIP6R0 0x41B0
249 #define W6100_UIP6R1 0x41B1
250 #define W6100_UIP6R2 0x41B2
251 #define W6100_UIP6R3 0x41B3
252 #define W6100_UIP6R4 0x41B4
253 #define W6100_UIP6R5 0x41B5
254 #define W6100_UIP6R6 0x41B6
255 #define W6100_UIP6R7 0x41B7
256 #define W6100_UIP6R8 0x41B8
257 #define W6100_UIP6R9 0x41B9
258 #define W6100_UIP6R10 0x41BA
259 #define W6100_UIP6R11 0x41BB
260 #define W6100_UIP6R12 0x41BC
261 #define W6100_UIP6R13 0x41BD
262 #define W6100_UIP6R14 0x41BE
263 #define W6100_UIP6R15 0x41BF
264 #define W6100_UPORT6R0 0x41C0
265 #define W6100_UPORT6R1 0x41C1
266 #define W6100_INTPTMR0 0x41C5
267 #define W6100_INTPTMR1 0x41C6
268 #define W6100_PLR 0x41D0
269 #define W6100_PFR 0x41D4
270 #define W6100_VLTR0 0x41D8
271 #define W6100_VLTR1 0x41D9
272 #define W6100_VLTR2 0x41DA
273 #define W6100_VLTR3 0x41DB
274 #define W6100_PLTR0 0x41DC
275 #define W6100_PLTR1 0x41DD
276 #define W6100_PLTR2 0x41DE
277 #define W6100_PLTR3 0x41DF
278 #define W6100_PAR0 0x41E0
279 #define W6100_PAR1 0x41E1
280 #define W6100_PAR2 0x41E2
281 #define W6100_PAR3 0x41E3
282 #define W6100_PAR4 0x41E4
283 #define W6100_PAR5 0x41E5
284 #define W6100_PAR6 0x41E6
285 #define W6100_PAR7 0x41E7
286 #define W6100_PAR8 0x41E8
287 #define W6100_PAR9 0x41E9
288 #define W6100_PAR10 0x41EA
289 #define W6100_PAR11 0x41EB
290 #define W6100_PAR12 0x41EC
291 #define W6100_PAR13 0x41ED
292 #define W6100_PAR14 0x41EE
293 #define W6100_PAR15 0x41EF
294 #define W6100_ICMP6BLKR 0x41F0
295 #define W6100_CHPLCKR 0x41F4
296 #define W6100_NETLCKR 0x41F5
297 #define W6100_PHYLCKR 0x41F6
298 #define W6100_RTR0 0x4200
299 #define W6100_RTR1 0x4201
300 #define W6100_RCR 0x4204
301 #define W6100_SLRTR0 0x4208
302 #define W6100_SLRTR1 0x4209
303 #define W6100_SLRCR 0x420C
304 #define W6100_SLHOPR 0x420F
305 
306 //Socket register block
307 #define W6100_Sn_MR 0x0000
308 #define W6100_Sn_PSR 0x0004
309 #define W6100_Sn_CR 0x0010
310 #define W6100_Sn_IR 0x0020
311 #define W6100_Sn_IMR 0x0024
312 #define W6100_Sn_IRCLR 0x0028
313 #define W6100_Sn_SR 0x0030
314 #define W6100_Sn_ESR 0x0031
315 #define W6100_Sn_PNR 0x0100
316 #define W6100_Sn_TOSR 0x0104
317 #define W6100_Sn_TTLR 0x0108
318 #define W6100_Sn_FRGR0 0x010C
319 #define W6100_Sn_FRGR1 0x010D
320 #define W6100_Sn_MSSR0 0x0110
321 #define W6100_Sn_MSSR1 0x0111
322 #define W6100_Sn_PORTR0 0x0114
323 #define W6100_Sn_PORTR1 0x0115
324 #define W6100_Sn_DHAR0 0x0118
325 #define W6100_Sn_DHAR1 0x0119
326 #define W6100_Sn_DHAR2 0x011A
327 #define W6100_Sn_DHAR3 0x011B
328 #define W6100_Sn_DHAR4 0x011C
329 #define W6100_Sn_DHAR5 0x011D
330 #define W6100_Sn_DIPR0 0x0120
331 #define W6100_Sn_DIPR1 0x0121
332 #define W6100_Sn_DIPR2 0x0122
333 #define W6100_Sn_DIPR3 0x0123
334 #define W6100_Sn_DIP6R0 0x0130
335 #define W6100_Sn_DIP6R1 0x0131
336 #define W6100_Sn_DIP6R2 0x0132
337 #define W6100_Sn_DIP6R3 0x0133
338 #define W6100_Sn_DIP6R4 0x0134
339 #define W6100_Sn_DIP6R5 0x0135
340 #define W6100_Sn_DIP6R6 0x0136
341 #define W6100_Sn_DIP6R7 0x0137
342 #define W6100_Sn_DIP6R8 0x0138
343 #define W6100_Sn_DIP6R9 0x0139
344 #define W6100_Sn_DIP6R10 0x013A
345 #define W6100_Sn_DIP6R11 0x013B
346 #define W6100_Sn_DIP6R12 0x013C
347 #define W6100_Sn_DIP6R13 0x013D
348 #define W6100_Sn_DIP6R14 0x013E
349 #define W6100_Sn_DIP6R15 0x013F
350 #define W6100_Sn_DPORTR0 0x0140
351 #define W6100_Sn_DPORTR1 0x0141
352 #define W6100_Sn_MR2 0x0144
353 #define W6100_Sn_RTR0 0x0180
354 #define W6100_Sn_RTR1 0x0181
355 #define W6100_Sn_RCR 0x0184
356 #define W6100_Sn_KPALVTR 0x0188
357 #define W6100_Sn_TX_BSR 0x0200
358 #define W6100_Sn_TX_FSR0 0x0204
359 #define W6100_Sn_TX_FSR1 0x0205
360 #define W6100_Sn_TX_RD0 0x0208
361 #define W6100_Sn_TX_RD1 0x0209
362 #define W6100_Sn_TX_WR0 0x020C
363 #define W6100_Sn_TX_WR1 0x020D
364 #define W6100_Sn_RX_BSR 0x0220
365 #define W6100_Sn_RX_RSR0 0x0224
366 #define W6100_Sn_RX_RSR1 0x0225
367 #define W6100_Sn_RX_RD0 0x0228
368 #define W6100_Sn_RX_RD1 0x0229
369 #define W6100_Sn_RX_WR0 0x022C
370 #define W6100_Sn_RX_WR1 0x022D
371 
372 //Chip Identification 0 register
373 #define W6100_CIDR0_DEFAULT 0x61
374 
375 //Chip Identification 1 register
376 #define W6100_CIDR1_DEFAULT 0x00
377 
378 //Chip Version 0 register
379 #define W6100_VER0_DEFAULT 0x46
380 
381 //Chip Version 1 register
382 #define W6100_VER1_DEFAULT 0x61
383 
384 //System Status register
385 #define W6100_SYSR_CHPL 0x80
386 #define W6100_SYSR_NETL 0x40
387 #define W6100_SYSR_PHYL 0x20
388 #define W6100_SYSR_IND 0x02
389 #define W6100_SYSR_SPI 0x01
390 
391 //System Config 0 register
392 #define W6100_SYCR0_RST 0x80
393 
394 //System Config 1 register
395 #define W6100_SYCR1_IEN 0x80
396 #define W6100_SYCR1_CLKSEL 0x01
397 
398 //Interrupt register
399 #define W6100_IR_WOL 0x80
400 #define W6100_IR_UNR6 0x10
401 #define W6100_IR_IPCONF 0x04
402 #define W6100_IR_UNR4 0x02
403 #define W6100_IR_PTERM 0x01
404 
405 //Socket Interrupt register
406 #define W6100_SIR_S7_INT 0x80
407 #define W6100_SIR_S6_INT 0x40
408 #define W6100_SIR_S5_INT 0x20
409 #define W6100_SIR_S4_INT 0x10
410 #define W6100_SIR_S3_INT 0x08
411 #define W6100_SIR_S2_INT 0x04
412 #define W6100_SIR_S1_INT 0x02
413 #define W6100_SIR_S0_INT 0x01
414 
415 //Socket-less Interrupt register
416 #define W6100_SLIR_TOUT 0x80
417 #define W6100_SLIR_ARP4 0x40
418 #define W6100_SLIR_PING4 0x20
419 #define W6100_SLIR_ARP6 0x10
420 #define W6100_SLIR_PING6 0x08
421 #define W6100_SLIR_NS 0x04
422 #define W6100_SLIR_RS 0x02
423 #define W6100_SLIR_RA 0x01
424 
425 //Interrupt Mask register
426 #define W6100_IMR_WOL 0x80
427 #define W6100_IMR_UNR6 0x10
428 #define W6100_IMR_IPCONF 0x04
429 #define W6100_IMR_UNR4 0x02
430 #define W6100_IMR_PTERM 0x01
431 
432 //IR Clear register
433 #define W6100_IRCLR_WOL 0x80
434 #define W6100_IRCLR_UNR6 0x10
435 #define W6100_IRCLR_IPCONF 0x04
436 #define W6100_IRCLR_UNR4 0x02
437 #define W6100_IRCLR_PTERM 0x01
438 
439 //Socket Interrupt Mask register
440 #define W6100_SIMR_S7_INT 0x80
441 #define W6100_SIMR_S6_INT 0x40
442 #define W6100_SIMR_S5_INT 0x20
443 #define W6100_SIMR_S4_INT 0x10
444 #define W6100_SIMR_S3_INT 0x08
445 #define W6100_SIMR_S2_INT 0x04
446 #define W6100_SIMR_S1_INT 0x02
447 #define W6100_SIMR_S0_INT 0x01
448 
449 //Socket-less Interrupt Mask register
450 #define W6100_SLIMR_TOUT 0x80
451 #define W6100_SLIMR_ARP4 0x40
452 #define W6100_SLIMR_PING4 0x20
453 #define W6100_SLIMR_ARP6 0x10
454 #define W6100_SLIMR_PING6 0x08
455 #define W6100_SLIMR_NS 0x04
456 #define W6100_SLIMR_RS 0x02
457 #define W6100_SLIMR_RA 0x01
458 
459 //SLIR Clear register
460 #define W6100_SLIRCLR_TOUT 0x80
461 #define W6100_SLIRCLR_ARP4 0x40
462 #define W6100_SLIRCLR_PING4 0x20
463 #define W6100_SLIRCLR_ARP6 0x10
464 #define W6100_SLIRCLR_PING6 0x08
465 #define W6100_SLIRCLR_NS 0x04
466 #define W6100_SLIRCLR_RS 0x02
467 #define W6100_SLIRCLR_RA 0x01
468 
469 //Socket-less Prefer Source IPv6 Address register
470 #define W6100_SLPSR_AUTO 0x00
471 #define W6100_SLPSR_LLA 0x02
472 #define W6100_SLPSR_GUA 0x03
473 
474 //Socket-less Command register
475 #define W6100_SLCR_ARP4 0x40
476 #define W6100_SLCR_PING4 0x20
477 #define W6100_SLCR_ARP6 0x10
478 #define W6100_SLCR_PING6 0x08
479 #define W6100_SLCR_NS 0x04
480 #define W6100_SLCR_RS 0x02
481 #define W6100_SLCR_NA 0x01
482 
483 //PHY Status register
484 #define W6100_PHYSR_CAB 0x80
485 #define W6100_PHYSR_MODE 0x38
486 #define W6100_PHYSR_MODE_AN 0x00
487 #define W6100_PHYSR_MODE_100BTX_FD 0x20
488 #define W6100_PHYSR_MODE_100BTX_HD 0x28
489 #define W6100_PHYSR_MODE_10BT_FD 0x30
490 #define W6100_PHYSR_MODE_10BT_HD 0x38
491 #define W6100_PHYSR_DPX 0x04
492 #define W6100_PHYSR_SPD 0x02
493 #define W6100_PHYSR_LNK 0x01
494 
495 //PHY Register Address register
496 #define W6100_PHYRAR_ADDR 0x1F
497 
498 //PHY Division register
499 #define W6100_PHYDIVR_DIV32 0x00
500 #define W6100_PHYDIVR_DIV64 0x01
501 #define W6100_PHYDIVR_DIV128 0x02
502 
503 //PHY Control 0 register
504 #define W6100_PHYCR0_MODE 0x07
505 #define W6100_PHYCR0_MODE_AN 0x00
506 #define W6100_PHYCR0_MODE_100BTX_FD 0x04
507 #define W6100_PHYCR0_MODE_100BTX_HD 0x05
508 #define W6100_PHYCR0_MODE_10BT_FD 0x06
509 #define W6100_PHYCR0_MODE_10BT_HD 0x07
510 
511 //PHY Control 1 register
512 #define W6100_PHYCR1_PWDN 0x20
513 #define W6100_PHYCR1_TE 0x08
514 #define W6100_PHYCR1_RST 0x01
515 
516 //Network IPv4 Mode register
517 #define W6100_NET4MR_UNRB 0x08
518 #define W6100_NET4MR_PARP 0x04
519 #define W6100_NET4MR_RSTB 0x02
520 #define W6100_NET4MR_PB 0x01
521 
522 //Network IPv6 Mode register
523 #define W6100_NET6MR_UNRB 0x08
524 #define W6100_NET6MR_PARP 0x04
525 #define W6100_NET6MR_RSTB 0x02
526 #define W6100_NET6MR_PB 0x01
527 
528 //Network Mode register
529 #define W6100_NETMR_ANB 0x20
530 #define W6100_NETMR_M6B 0x10
531 #define W6100_NETMR_WOL 0x04
532 #define W6100_NETMR_IP6B 0x02
533 #define W6100_NETMR_IP4B 0x01
534 
535 //Network Mode 2 register
536 #define W6100_NETMR2_DHAS 0x80
537 #define W6100_NETMR2_PPPOE 0x01
538 
539 //ICMPv6 Block register
540 #define W6100_ICMP6BLKR_PING6 0x10
541 #define W6100_ICMP6BLKR_MLD 0x08
542 #define W6100_ICMP6BLKR_RA 0x04
543 #define W6100_ICMP6BLKR_NA 0x02
544 #define W6100_ICMP6BLKR_NS 0x01
545 
546 //Chip Lock register
547 #define W6100_CHPLCKR_LOCK 0x00
548 #define W6100_CHPLCKR_UNLOCK 0xCE
549 
550 //Network Lock register
551 #define W6100_NETLCKR_UNLOCK 0x3A
552 #define W6100_NETLCKR_LOCK 0xC5
553 
554 //PHY Lock register
555 #define W6100_PHYLCKR_LOCK 0x00
556 #define W6100_PHYLCKR_UNLOCK 0x53
557 
558 //Socket n Mode register
559 #define W6100_Sn_MR_MULTI 0x80
560 #define W6100_Sn_MR_MF 0x80
561 #define W6100_Sn_MR_BRDB 0x40
562 #define W6100_Sn_MR_FPSH 0x40
563 #define W6100_Sn_MR_ND 0x20
564 #define W6100_Sn_MR_MC 0x20
565 #define W6100_Sn_MR_SMB 0x20
566 #define W6100_Sn_MR_MMB 0x20
567 #define W6100_Sn_MR_UNIB 0x10
568 #define W6100_Sn_MR_MMB6 0x10
569 #define W6100_Sn_MR_PROTOCOL 0x0F
570 #define W6100_Sn_MR_PROTOCOL_CLOSED 0x00
571 #define W6100_Sn_MR_PROTOCOL_TCP4 0x01
572 #define W6100_Sn_MR_PROTOCOL_UDP4 0x02
573 #define W6100_Sn_MR_PROTOCOL_IPRAW4 0x03
574 #define W6100_Sn_MR_PROTOCOL_MACRAW 0x07
575 #define W6100_Sn_MR_PROTOCOL_TCP6 0x09
576 #define W6100_Sn_MR_PROTOCOL_UDP6 0x0A
577 #define W6100_Sn_MR_PROTOCOL_IPRAW6 0x0B
578 #define W6100_Sn_MR_PROTOCOL_TCPD 0x0D
579 #define W6100_Sn_MR_PROTOCOL_UDPD 0x0F
580 
581 //Socket n Prefer Source IPv6 Address register
582 #define W6100_Sn_PSR_AUTO 0x00
583 #define W6100_Sn_PSR_LLA 0x02
584 #define W6100_Sn_PSR_GUA 0x03
585 
586 //Socket n Command register
587 #define W6100_Sn_CR_OPEN 0x01
588 #define W6100_Sn_CR_LISTEN 0x02
589 #define W6100_Sn_CR_CONNECT 0x04
590 #define W6100_Sn_CR_DISCON 0x08
591 #define W6100_Sn_CR_CLOSE 0x10
592 #define W6100_Sn_CR_SEND 0x20
593 #define W6100_Sn_CR_SEND_KEEP 0x22
594 #define W6100_Sn_CR_RECV 0x40
595 #define W6100_Sn_CR_CONNECT6 0x84
596 #define W6100_Sn_CR_SEND6 0xA6
597 
598 //Socket n Interrupt register
599 #define W6100_Sn_IR_SENDOK 0x10
600 #define W6100_Sn_IR_TIMEOUT 0x08
601 #define W6100_Sn_IR_RECV 0x04
602 #define W6100_Sn_IR_DISCON 0x02
603 #define W6100_Sn_IR_CON 0x01
604 
605 //Socket n Interrupt Mask register
606 #define W6100_Sn_IMR_SENDOK 0x10
607 #define W6100_Sn_IMR_TIMEOUT 0x08
608 #define W6100_Sn_IMR_RECV 0x04
609 #define W6100_Sn_IMR_DISCON 0x02
610 #define W6100_Sn_IMR_CON 0x01
611 
612 //Sn_IR Clear register
613 #define W6100_Sn_IRCLR_SENDOK 0x10
614 #define W6100_Sn_IRCLR_TIMEOUT 0x08
615 #define W6100_Sn_IRCLR_RECV 0x04
616 #define W6100_Sn_IRCLR_DISCON 0x02
617 #define W6100_Sn_IRCLR_CON 0x01
618 
619 //Socket n Status register
620 #define W6100_Sn_SR_SOCK_CLOSED 0x00
621 #define W6100_Sn_SR_SOCK_INIT 0x13
622 #define W6100_Sn_SR_SOCK_LISTEN 0x14
623 #define W6100_Sn_SR_SOCK_SYNSENT 0x15
624 #define W6100_Sn_SR_SOCK_SYNRECV 0x16
625 #define W6100_Sn_SR_SOCK_ESTABLISHED 0x17
626 #define W6100_Sn_SR_SOCK_FIN_WAIT 0x18
627 #define W6100_Sn_SR_SOCK_TIME_WAIT 0x1B
628 #define W6100_Sn_SR_SOCK_CLOSE_WAIT 0x1C
629 #define W6100_Sn_SR_SOCK_LAST_ACK 0x1D
630 #define W6100_Sn_SR_SOCK_UDP 0x22
631 #define W6100_Sn_SR_SOCK_IPRAW 0x32
632 #define W6100_Sn_SR_SOCK_IPRAW6 0x33
633 #define W6100_Sn_SR_SOCK_MACRAW 0x42
634 
635 //Socket n Extension Status register
636 #define W6100_Sn_ESR_TCPM 0x04
637 #define W6100_Sn_ESR_TCPM_TCP4 0x00
638 #define W6100_Sn_ESR_TCPM_TCP6 0x04
639 #define W6100_Sn_ESR_TCPOP 0x02
640 #define W6100_Sn_ESR_TCPOP_CLIENT 0x00
641 #define W6100_Sn_ESR_TCPOP_SERVER 0x02
642 #define W6100_Sn_ESR_IP6T 0x01
643 #define W6100_Sn_ESR_IP6T_LLA 0x00
644 #define W6100_Sn_ESR_IP6T_GUA 0x01
645 
646 //Socket n Mode 2 register
647 #define W6100_Sn_MR2_DHAM 0x02
648 #define W6100_Sn_MR2_FARP 0x01
649 
650 //Socket n TX Buffer Size register
651 #define W6100_Sn_TX_BSR_0KB 0x00
652 #define W6100_Sn_TX_BSR_1KB 0x01
653 #define W6100_Sn_TX_BSR_2KB 0x02
654 #define W6100_Sn_TX_BSR_4KB 0x04
655 #define W6100_Sn_TX_BSR_8KB 0x08
656 #define W6100_Sn_TX_BSR_16KB 0x10
657 
658 //Socket n RX Buffer Size register
659 #define W6100_Sn_RX_BSR_0KB 0x00
660 #define W6100_Sn_RX_BSR_1KB 0x01
661 #define W6100_Sn_RX_BSR_2KB 0x02
662 #define W6100_Sn_RX_BSR_4KB 0x04
663 #define W6100_Sn_RX_BSR_8KB 0x08
664 #define W6100_Sn_RX_BSR_16KB 0x10
665 
666 //Block Select Bits
667 #define W6100_CTRL_BSB_Sn_REG(n) (0x08 + (n) * 0x20)
668 #define W6100_CTRL_BSB_Sn_TX_BUFFER(n) (0x10 + (n) * 0x20)
669 #define W6100_CTRL_BSB_Sn_RX_BUFFER(n) (0x18 + (n) * 0x20)
670 
671 //C++ guard
672 #ifdef __cplusplus
673 extern "C" {
674 #endif
675 
676 //W6100 driver
677 extern const NicDriver w6100Driver;
678 
679 //W6100 related functions
680 error_t w6100Init(NetInterface *interface);
681 void w6100InitHook(NetInterface *interface);
682 
683 void w6100Tick(NetInterface *interface);
684 
685 void w6100EnableIrq(NetInterface *interface);
686 void w6100DisableIrq(NetInterface *interface);
688 void w6100EventHandler(NetInterface *interface);
689 
691  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
692 
694 
696 
697 void w6100WriteReg8(NetInterface *interface, uint8_t control,
698  uint16_t address, uint8_t data);
699 
700 uint8_t w6100ReadReg8(NetInterface *interface, uint8_t control,
701  uint16_t address);
702 
703 void w6100WriteReg16(NetInterface *interface, uint8_t control,
704  uint16_t address, uint16_t data);
705 
706 uint16_t w6100ReadReg16(NetInterface *interface, uint8_t control,
707  uint16_t address);
708 
709 void w6100WriteBuffer(NetInterface *interface, uint8_t control,
710  uint16_t address, const uint8_t *data, size_t length);
711 
712 void w6100ReadBuffer(NetInterface *interface, uint8_t control,
713  uint16_t address, uint8_t *data, size_t length);
714 
715 void w6100DumpReg(NetInterface *interface);
716 
717 //C++ guard
718 #ifdef __cplusplus
719 }
720 #endif
721 
722 #endif
void w6100EnableIrq(NetInterface *interface)
Enable interrupts.
Definition: w6100_driver.c:263
int bool_t
Definition: compiler_port.h:53
uint8_t control
Definition: ethernet.h:234
error_t w6100UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
Definition: w6100_driver.c:524
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
uint8_t data[]
Definition: ethernet.h:222
void w6100WriteBuffer(NetInterface *interface, uint8_t control, uint16_t address, const uint8_t *data, size_t length)
Write TX buffer.
Definition: w6100_driver.c:672
error_t w6100SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
Definition: w6100_driver.c:381
void w6100InitHook(NetInterface *interface)
W6100 custom configuration.
Definition: w6100_driver.c:196
error_t
Error codes.
Definition: error.h:43
void w6100DisableIrq(NetInterface *interface)
Disable interrupts.
Definition: w6100_driver.c:278
#define NetInterface
Definition: net.h:36
void w6100WriteReg16(NetInterface *interface, uint8_t control, uint16_t address, uint16_t data)
Write 16-bit register.
Definition: w6100_driver.c:604
#define NetTxAncillary
Definition: net_misc.h:36
uint8_t length
Definition: tcp.h:368
void w6100Tick(NetInterface *interface)
W6100 timer handler.
Definition: w6100_driver.c:206
const NicDriver w6100Driver
W6100 driver.
Definition: w6100_driver.c:44
Ipv6Addr address[]
Definition: ipv6.h:325
void w6100DumpReg(NetInterface *interface)
Dump registers for debugging purpose.
Definition: w6100_driver.c:740
Network interface controller abstraction layer.
error_t w6100Init(NetInterface *interface)
W6100 controller initialization.
Definition: w6100_driver.c:71
uint16_t w6100ReadReg16(NetInterface *interface, uint8_t control, uint16_t address)
Read 16-bit register.
Definition: w6100_driver.c:635
void w6100WriteReg8(NetInterface *interface, uint8_t control, uint16_t address, uint8_t data)
Write 8-bit register.
Definition: w6100_driver.c:539
uint8_t w6100ReadReg8(NetInterface *interface, uint8_t control, uint16_t address)
Read 8-bit register.
Definition: w6100_driver.c:569
error_t w6100ReceivePacket(NetInterface *interface)
Receive a packet.
Definition: w6100_driver.c:446
void w6100ReadBuffer(NetInterface *interface, uint8_t control, uint16_t address, uint8_t *data, size_t length)
Read RX buffer.
Definition: w6100_driver.c:708
NIC driver.
Definition: nic.h:286
bool_t w6100IrqHandler(NetInterface *interface)
W6100 interrupt service routine.
Definition: w6100_driver.c:294
void w6100EventHandler(NetInterface *interface)
W6100 event handler.
Definition: w6100_driver.c:356