ar8031_driver.h
Go to the documentation of this file.
1 /**
2  * @file ar8031_driver.h
3  * @brief AR8031 Gigabit Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _AR8031_DRIVER_H
30 #define _AR8031_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef AR8031_PHY_ADDR
37  #define AR8031_PHY_ADDR 0
38 #elif (AR8031_PHY_ADDR < 0 || AR8031_PHY_ADDR > 31)
39  #error AR8031_PHY_ADDR parameter is not valid
40 #endif
41 
42 //AR8031 registers
43 #define AR8031_PHY_REG_BMCR 0x00
44 #define AR8031_PHY_REG_BMSR 0x01
45 #define AR8031_PHY_REG_PHYIDR1 0x02
46 #define AR8031_PHY_REG_PHYIDR2 0x03
47 #define AR8031_PHY_REG_ANAR 0x04
48 #define AR8031_PHY_REG_ANLPAR 0x05
49 #define AR8031_PHY_REG_ANER 0x06
50 #define AR8031_PHY_REG_ANNPTR 0x07
51 #define AR8031_PHY_REG_LPNPAR 0x08
52 #define AR8031_PHY_REG_1000BT_CTRL 0x09
53 #define AR8031_PHY_REG_1000BT_STATUS 0x0A
54 #define AR8031_PHY_REG_MMD_CTRL 0x0D
55 #define AR8031_PHY_REG_MMD_DATA 0x0E
56 #define AR8031_PHY_REG_EXT_STATUS 0x0F
57 #define AR8031_PHY_REG_FUNCTION_CTRL 0x10
58 #define AR8031_PHY_REG_PHY_STATUS 0x11
59 #define AR8031_PHY_REG_INT_EN 0x12
60 #define AR8031_PHY_REG_INT_STATUS 0x13
61 #define AR8031_PHY_REG_SMART_SPEED 0x14
62 #define AR8031_PHY_REG_CDT_CTRL 0x16
63 #define AR8031_PHY_REG_LED_CTRL 0x18
64 #define AR8031_PHY_REG_MAN_LED_OVERRIDE 0x19
65 #define AR8031_PHY_REG_CDT_STATUS 0x1C
66 #define AR8031_PHY_REG_DBG_PORT 0x1D
67 #define AR8031_PHY_REG_DBG_PORT2 0x1E
68 #define AR8031_PHY_REG_CHIP_CONFIG 0x1F
69 
70 //BMCR register
71 #define BMCR_RESET (1 << 15)
72 #define BMCR_LOOPBACK (1 << 14)
73 #define BMCR_SPEED_SEL_LSB (1 << 13)
74 #define BMCR_AN_EN (1 << 12)
75 #define BMCR_POWER_DOWN (1 << 11)
76 #define BMCR_ISOLATE (1 << 10)
77 #define BMCR_RESTART_AN (1 << 9)
78 #define BMCR_DUPLEX_MODE (1 << 8)
79 #define BMCR_COL_TEST (1 << 7)
80 #define BMCR_SPEED_SEL_MSB (1 << 6)
81 
82 //BMSR register
83 #define BMSR_100BT4 (1 << 15)
84 #define BMSR_100BTX_FD (1 << 14)
85 #define BMSR_100BTX_HD (1 << 13)
86 #define BMSR_10BT_FD (1 << 12)
87 #define BMSR_10BT_HD (1 << 11)
88 #define BMSR_100BT2_FD (1 << 10)
89 #define BMSR_100BT2_HD (1 << 9)
90 #define BMSR_EXTENDED_STATUS (1 << 8)
91 #define BMSR_NO_PREAMBLE (1 << 6)
92 #define BMSR_AN_COMPLETE (1 << 5)
93 #define BMSR_REMOTE_FAULT (1 << 4)
94 #define BMSR_AN_ABLE (1 << 3)
95 #define BMSR_LINK_STATUS (1 << 2)
96 #define BMSR_JABBER_DETECT (1 << 1)
97 #define BMSR_EXTENDED_CAP (1 << 0)
98 
99 //ANAR register
100 #define ANAR_NEXT_PAGE (1 << 15)
101 #define ANAR_ACK (1 << 14)
102 #define ANAR_REMOTE_FAULT (1 << 13)
103 #define ANAR_XNP_ABLE (1 << 12)
104 #define ANAR_ASYMMETRIC_PAUSE (1 << 11)
105 #define ANAR_PAUSE (1 << 10)
106 #define ANAR_100BT4 (1 << 9)
107 #define ANAR_100BTX_FD (1 << 8)
108 #define ANAR_100BTX_HD (1 << 7)
109 #define ANAR_10BT_FD (1 << 6)
110 #define ANAR_10BT_HD (1 << 5)
111 #define ANAR_SELECTOR4 (1 << 4)
112 #define ANAR_SELECTOR3 (1 << 3)
113 #define ANAR_SELECTOR2 (1 << 2)
114 #define ANAR_SELECTOR1 (1 << 1)
115 #define ANAR_SELECTOR0 (1 << 0)
116 
117 //ANLPAR register
118 #define ANLPAR_NEXT_PAGE (1 << 15)
119 #define ANLPAR_ACK (1 << 14)
120 #define ANLPAR_REMOTE_FAULT (1 << 13)
121 #define ANLPAR_ASYMMETRIC_PAUSE (1 << 11)
122 #define ANLPAR_PAUSE (1 << 10)
123 #define ANLPAR_100BT4 (1 << 9)
124 #define ANLPAR_100BTX_FD (1 << 8)
125 #define ANLPAR_100BTX_HD (1 << 7)
126 #define ANLPAR_10BT_FD (1 << 6)
127 #define ANLPAR_10BT_HD (1 << 5)
128 #define ANLPAR_SELECTOR4 (1 << 4)
129 #define ANLPAR_SELECTOR3 (1 << 3)
130 #define ANLPAR_SELECTOR2 (1 << 2)
131 #define ANLPAR_SELECTOR1 (1 << 1)
132 #define ANLPAR_SELECTOR0 (1 << 0)
133 
134 //ANER register
135 #define ANER_PAR_DET_FAULT (1 << 4)
136 #define ANER_LP_NEXT_PAGE_ABLE (1 << 3)
137 #define ANER_NEXT_PAGE_ABLE (1 << 2)
138 #define ANER_PAGE_RECEIVED (1 << 1)
139 #define ANER_LP_AN_ABLE (1 << 0)
140 
141 //ANNPTR register
142 #define ANNPTR_NEXT_PAGE (1 << 15)
143 #define ANNPTR_MSG_PAGE (1 << 13)
144 #define ANNPTR_ACK2 (1 << 12)
145 #define ANNPTR_TOGGLE (1 << 11)
146 #define ANNPTR_MESSAGE10 (1 << 10)
147 #define ANNPTR_MESSAGE9 (1 << 9)
148 #define ANNPTR_MESSAGE8 (1 << 8)
149 #define ANNPTR_MESSAGE7 (1 << 7)
150 #define ANNPTR_MESSAGE6 (1 << 6)
151 #define ANNPTR_MESSAGE5 (1 << 5)
152 #define ANNPTR_MESSAGE4 (1 << 4)
153 #define ANNPTR_MESSAGE3 (1 << 3)
154 #define ANNPTR_MESSAGE2 (1 << 2)
155 #define ANNPTR_MESSAGE1 (1 << 1)
156 #define ANNPTR_MESSAGE0 (1 << 0)
157 
158 //LPNPAR register
159 #define LPNPAR_NEXT_PAGE (1 << 15)
160 #define LPNPAR_MSG_PAGE (1 << 13)
161 #define LPNPAR_ACK2 (1 << 12)
162 #define LPNPAR_TOGGLE (1 << 11)
163 #define LPNPAR_MESSAGE10 (1 << 10)
164 #define LPNPAR_MESSAGE9 (1 << 9)
165 #define LPNPAR_MESSAGE8 (1 << 8)
166 #define LPNPAR_MESSAGE7 (1 << 7)
167 #define LPNPAR_MESSAGE6 (1 << 6)
168 #define LPNPAR_MESSAGE5 (1 << 5)
169 #define LPNPAR_MESSAGE4 (1 << 4)
170 #define LPNPAR_MESSAGE3 (1 << 3)
171 #define LPNPAR_MESSAGE2 (1 << 2)
172 #define LPNPAR_MESSAGE1 (1 << 1)
173 #define LPNPAR_MESSAGE0 (1 << 0)
174 
175 //1000BT_CTRL register
176 #define _1000BT_CTRL_TEST_MODE2 (1 << 15)
177 #define _1000BT_CTRL_TEST_MODE1 (1 << 14)
178 #define _1000BT_CTRL_TEST_MODE0 (1 << 13)
179 #define _1000BT_CTRL_MS_MAN_CONF_EN (1 << 12)
180 #define _1000BT_CTRL_MS_MAN_CONF_VAL (1 << 11)
181 #define _1000BT_CTRL_PORT_TYPE (1 << 10)
182 #define _1000BT_CTRL_1000BT_FD (1 << 9)
183 #define _1000BT_CTRL_1000BT_HD (1 << 8)
184 
185 //1000BT_STATUS register
186 #define _1000BT_STATUS_MS_CONF_FAULT (1 << 15)
187 #define _1000BT_STATUS_MS_CONF_RES (1 << 14)
188 #define _1000BT_STATUS_LOC_REC_STATUS (1 << 13)
189 #define _1000BT_STATUS_REM_REC_STATUS (1 << 12)
190 #define _1000BT_STATUS_LP_1000BT_FD (1 << 11)
191 #define _1000BT_STATUS_LP_1000BT_HD (1 << 10)
192 #define _1000BT_STATUS_IDLE_ERR_CTR7 (1 << 7)
193 #define _1000BT_STATUS_IDLE_ERR_CTR6 (1 << 6)
194 #define _1000BT_STATUS_IDLE_ERR_CTR5 (1 << 5)
195 #define _1000BT_STATUS_IDLE_ERR_CTR4 (1 << 4)
196 #define _1000BT_STATUS_IDLE_ERR_CTR3 (1 << 3)
197 #define _1000BT_STATUS_IDLE_ERR_CTR2 (1 << 2)
198 #define _1000BT_STATUS_IDLE_ERR_CTR1 (1 << 1)
199 #define _1000BT_STATUS_IDLE_ERR_CTR0 (1 << 0)
200 
201 //MMD_CTRL register
202 #define MMD_CTRL_FUNCTION1 (1 << 15)
203 #define MMD_CTRL_FUNCTION0 (1 << 14)
204 #define MMD_CTRL_DEVAD4 (1 << 4)
205 #define MMD_CTRL_DEVAD3 (1 << 3)
206 #define MMD_CTRL_DEVAD2 (1 << 2)
207 #define MMD_CTRL_DEVAD1 (1 << 1)
208 #define MMD_CTRL_DEVAD0 (1 << 0)
209 
210 //EXT_STATUS register
211 #define EXT_STATUS_1000BX_FD (1 << 15)
212 #define EXT_STATUS_1000BX_HD (1 << 14)
213 #define EXT_STATUS_1000BT_FD (1 << 13)
214 #define EXT_STATUS_1000BT_HD (1 << 12)
215 
216 //FUNCTION register
217 #define FUNCTION_ASSERT_CRS_ON_TX (1 << 11)
218 #define FUNCTION_FORCE_LINK (1 << 10)
219 #define FUNCTION_MDI_CROSSOVER_MODE1 (1 << 6)
220 #define FUNCTION_MDI_CROSSOVER_MODE0 (1 << 5)
221 #define FUNCTION_SQE_TEST (1 << 2)
222 #define FUNCTION_POLARITY_REVERSAL (1 << 1)
223 #define FUNCTION_DISABLE_JABBER (1 << 0)
224 
225 //PHY_STATUS register
226 #define PHY_STATUS_SPEED1 (1 << 15)
227 #define PHY_STATUS_SPEED0 (1 << 14)
228 #define PHY_STATUS_DUPLEX (1 << 13)
229 #define PHY_STATUS_PAGE_RECEIVED (1 << 12)
230 #define PHY_STATUS_SPEED_DUPLEX_RESOLVED (1 << 11)
231 #define PHY_STATUS_LINK (1 << 10)
232 #define PHY_STATUS_MDI_CROSSOVER_STATUS (1 << 6)
233 #define PHY_STATUS_WIRESPEED_DOWNGRADE (1 << 5)
234 #define PHY_STATUS_TX_PAUSE_ENABLED (1 << 3)
235 #define PHY_STATUS_RX_PAUSE_ENABLED (1 << 2)
236 #define PHY_STATUS_POLARITY (1 << 1)
237 #define PHY_STATUS_JABBER (1 << 0)
238 
239 //Speed
240 #define PHY_STATUS_SPEED_MASK (3 << 14)
241 #define PHY_STATUS_SPEED_10 (0 << 14)
242 #define PHY_STATUS_SPEED_100 (1 << 14)
243 #define PHY_STATUS_SPEED_1000 (2 << 14)
244 
245 //INT_EN register
246 #define INT_EN_AN_ERROR (1 << 15)
247 #define INT_EN_SPEED_CHANGED (1 << 14)
248 #define INT_EN_PAGE_RECEIVED (1 << 12)
249 #define INT_EN_LINK_FAIL (1 << 11)
250 #define INT_EN_LINK_SUCCESS (1 << 10)
251 #define INT_EN_FAST_LINK_DOWN1 (1 << 9)
252 #define INT_EN_LINK_FAIL_BX (1 << 8)
253 #define INT_EN_LINK_SUCCESS_BX (1 << 7)
254 #define INT_EN_FAST_LINK_DOWN0 (1 << 6)
255 #define INT_EN_WIRESPEED_DOWNGRADE (1 << 5)
256 #define INT_EN_10MS_PTP (1 << 4)
257 #define INT_EN_RX_PTP (1 << 3)
258 #define INT_EN_TX_PTP (1 << 2)
259 #define INT_EN_POLARITY_CHANGED (1 << 1)
260 #define INT_EN_WOL_PTP (1 << 0)
261 
262 //INT_STATUS register
263 #define INT_STATUS_AN_ERROR (1 << 15)
264 #define INT_STATUS_SPEED_CHANGED (1 << 14)
265 #define INT_STATUS_PAGE_RECEIVED (1 << 12)
266 #define INT_STATUS_LINK_FAIL (1 << 11)
267 #define INT_STATUS_LINK_SUCCESS (1 << 10)
268 #define INT_STATUS_FAST_LINK_DOWN1 (1 << 9)
269 #define INT_STATUS_LINK_FAIL_BX (1 << 8)
270 #define INT_STATUS_LINK_SUCCESS_BX (1 << 7)
271 #define INT_STATUS_FAST_LINK_DOWN0 (1 << 6)
272 #define INT_STATUS_WIRESPEED_DOWNGRADE (1 << 5)
273 #define INT_STATUS_10MS_PTP (1 << 4)
274 #define INT_STATUS_RX_PTP (1 << 3)
275 #define INT_STATUS_TX_PTP (1 << 2)
276 #define INT_STATUS_POLARITY_CHANGED (1 << 1)
277 #define INT_STATUS_WOL_PTP (1 << 0)
278 
279 //SMART_SPEED register
280 #define SMART_SPEED_EN (1 << 5)
281 #define SMART_SPEED_RETRY_LIMIT2 (1 << 4)
282 #define SMART_SPEED_RETRY_LIMIT1 (1 << 3)
283 #define SMART_SPEED_RETRY_LIMIT0 (1 << 2)
284 #define SMART_SPEED_TIMER (1 << 1)
285 
286 //CDT_CTRL register
287 #define CDT_CTRL_MDI_PAIR_SELECT1 (1 << 9)
288 #define CDT_CTRL_MDI_PAIR_SELECT0 (1 << 8)
289 #define CDT_CTRL_ENABLE_TEST (1 << 0)
290 
291 //LED_CTRL register
292 #define LED_CTRL_DISABLE_LED (1 << 15)
293 #define LED_CTRL_LED_ON_TIME2 (1 << 14)
294 #define LED_CTRL_LED_ON_TIME1 (1 << 13)
295 #define LED_CTRL_LED_ON_TIME0 (1 << 12)
296 #define LED_CTRL_LED_OFF_TIME2 (1 << 10)
297 #define LED_CTRL_LED_OFF_TIME1 (1 << 9)
298 #define LED_CTRL_LED_OFF_TIME0 (1 << 8)
299 #define LED_CTRL_LED_LINK_CTRL1 (1 << 4)
300 #define LED_CTRL_LED_LINK_CTRL0 (1 << 3)
301 #define LED_CTRL_LED_ACT_CTRL (1 << 1)
302 
303 //MAN_LED_OVERRIDE register
304 #define MAN_LED_OVERRIDE_LED_ACT_CTRL (1 << 12)
305 #define MAN_LED_OVERRIDE_LED_LINK_CTRL1 (1 << 7)
306 #define MAN_LED_OVERRIDE_LED_LINK_CTRL0 (1 << 6)
307 #define MAN_LED_OVERRIDE_LED_RX_CTRL1 (1 << 3)
308 #define MAN_LED_OVERRIDE_LED_RX_CTRL0 (1 << 2)
309 #define MAN_LED_OVERRIDE_LED_TX_CTRL1 (1 << 1)
310 #define MAN_LED_OVERRIDE_LED_TX_CTRL0 (1 << 0)
311 
312 //CDT_STATUS register
313 #define CDT_STATUS_STATUS1 (1 << 9)
314 #define CDT_STATUS_STATUS0 (1 << 8)
315 #define CDT_STATUS_DELTA_TIME7 (1 << 7)
316 #define CDT_STATUS_DELTA_TIME6 (1 << 6)
317 #define CDT_STATUS_DELTA_TIME5 (1 << 5)
318 #define CDT_STATUS_DELTA_TIME4 (1 << 4)
319 #define CDT_STATUS_DELTA_TIME3 (1 << 3)
320 #define CDT_STATUS_DELTA_TIME2 (1 << 2)
321 #define CDT_STATUS_DELTA_TIME1 (1 << 1)
322 #define CDT_STATUS_DELTA_TIME0 (1 << 0)
323 
324 //CHIP_CONF register
325 #define CHIP_CONFIG_BT_BX_REG_SEL (1 << 15)
326 #define CHIP_CONFIG_SMII_IMP_50_75_AUTO (1 << 14)
327 #define CHIP_CONFIG_SGMII_RXIMP_50_75 (1 << 13)
328 #define CHIP_CONFIG_SGMII_TXIMP_50_75 (1 << 12)
329 #define CHIP_CONFIG_PRIORITY_SEL (1 << 10)
330 #define CHIP_CONFIG_FIBER_MODE_AUTO (1 << 8)
331 #define CHIP_CONFIG_MODE_CFG_QUAL3 (1 << 7)
332 #define CHIP_CONFIG_MODE_CFG_QUAL2 (1 << 6)
333 #define CHIP_CONFIG_MODE_CFG_QUAL1 (1 << 5)
334 #define CHIP_CONFIG_MODE_CFG_QUAL0 (1 << 4)
335 #define CHIP_CONFIG_MODE_CFG3 (1 << 3)
336 #define CHIP_CONFIG_MODE_CFG2 (1 << 2)
337 #define CHIP_CONFIG_MODE_CFG1 (1 << 1)
338 #define CHIP_CONFIG_MODE_CFG0 (1 << 0)
339 
340 //C++ guard
341 #ifdef __cplusplus
342  extern "C" {
343 #endif
344 
345 //AR8031 Ethernet PHY driver
346 extern const PhyDriver ar8031PhyDriver;
347 
348 //AR8031 related functions
349 error_t ar8031Init(NetInterface *interface);
350 
351 void ar8031Tick(NetInterface *interface);
352 
353 void ar8031EnableIrq(NetInterface *interface);
354 void ar8031DisableIrq(NetInterface *interface);
355 
356 void ar8031EventHandler(NetInterface *interface);
357 
358 void ar8031WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
359 uint16_t ar8031ReadPhyReg(NetInterface *interface, uint8_t address);
360 
361 void ar8031DumpPhyReg(NetInterface *interface);
362 
363 //C++ guard
364 #ifdef __cplusplus
365  }
366 #endif
367 
368 #endif
const PhyDriver ar8031PhyDriver
AR8031 Ethernet PHY driver.
Definition: ar8031_driver.c:42
void ar8031DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
void ar8031EnableIrq(NetInterface *interface)
Enable interrupts.
void ar8031WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
PHY driver.
Definition: nic.h:196
void ar8031Tick(NetInterface *interface)
AR8031 timer handler.
error_t ar8031Init(NetInterface *interface)
AR8031 PHY transceiver initialization.
Definition: ar8031_driver.c:58
uint16_t ar8031ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
void ar8031DisableIrq(NetInterface *interface)
Disable interrupts.
#define NetInterface
Definition: net.h:34
void ar8031EventHandler(NetInterface *interface)
AR8031 event handler.
Network interface controller abstraction layer.