Artery AT32F4 Ethernet MAC driver. More...

#include "core/nic.h"

Data Structures
struct	At32f4xxTxDmaDesc
	Enhanced TX DMA descriptor. More...

struct	At32f4xxRxDmaDesc
	Enhanced RX DMA descriptor. More...

Macros
#define	AT32F4XX_ETH_TX_BUFFER_COUNT 3

#define	AT32F4XX_ETH_TX_BUFFER_SIZE 1536

#define	AT32F4XX_ETH_RX_BUFFER_COUNT 6

#define	AT32F4XX_ETH_RX_BUFFER_SIZE 1536

#define	AT32F4XX_ETH_IRQ_PRIORITY_GROUPING 3

#define	AT32F4XX_ETH_IRQ_GROUP_PRIORITY 12

#define	AT32F4XX_ETH_IRQ_SUB_PRIORITY 0

#define	EMAC_CTRL_WD 0x00800000

#define	EMAC_CTRL_JD 0x00400000

#define	EMAC_CTRL_IFG 0x000E0000

#define	EMAC_CTRL_DCS 0x00010000

#define	EMAC_CTRL_RESERVED15 0x00008000

#define	EMAC_CTRL_FES 0x00004000

#define	EMAC_CTRL_DRO 0x00002000

#define	EMAC_CTRL_LM 0x00001000

#define	EMAC_CTRL_DM 0x00000800

#define	EMAC_CTRL_IPC 0x00000400

#define	EMAC_CTRL_DR 0x00000200

#define	EMAC_CTRL_ACS 0x00000080

#define	EMAC_CTRL_BL 0x00000060

#define	EMAC_CTRL_DC 0x00000010

#define	EMAC_CTRL_TE 0x00000008

#define	EMAC_CTRL_RE 0x00000004

#define	EMAC_FRMF_RA 0x80000000

#define	EMAC_FRMF_HPF 0x00000400

#define	EMAC_FRMF_SAF 0x00000200

#define	EMAC_FRMF_SAIF 0x00000100

#define	EMAC_FRMF_PCF 0x000000C0

#define	EMAC_FRMF_DBF 0x00000020

#define	EMAC_FRMF_PMC 0x00000010

#define	EMAC_FRMF_DAIF 0x00000008

#define	EMAC_FRMF_HMC 0x00000004

#define	EMAC_FRMF_HUC 0x00000002

#define	EMAC_FRMF_PR 0x00000001

#define	EMAC_MIIADDR_PA 0x0000F800

#define	EMAC_MIIADDR_MII 0x000007C0

#define	EMAC_MIIADDR_CR 0x0000003C

#define	EMAC_MIIADDR_CR_DIV_42 0x00000000

#define	EMAC_MIIADDR_CR_DIV_62 0x00000004

#define	EMAC_MIIADDR_CR_DIV_16 0x00000008

#define	EMAC_MIIADDR_CR_DIV_26 0x0000000C

#define	EMAC_MIIADDR_CR_DIV_102 0x00000010

#define	EMAC_MIIADDR_CR_DIV_124 0x00000014

#define	EMAC_MIIADDR_MW 0x00000002

#define	EMAC_MIIADDR_MB 0x00000001

#define	EMAC_MIIDT_MD 0x0000FFFF

#define	EMAC_IMR_TIM 0x00000200

#define	EMAC_IMR_PIM 0x00000008

#define	EMAC_A0H_AE 0x80000000

#define	EMAC_A0H_MA0H 0x0000FFFF

#define	EMAC_A1H_AE 0x80000000

#define	EMAC_A1H_SA 0x40000000

#define	EMAC_A1H_MBC 0x3F000000

#define	EMAC_A1H_MA1H 0x0000FFFF

#define	EMAC_A2H_AE 0x80000000

#define	EMAC_A2H_SA 0x40000000

#define	EMAC_A2H_MBC 0x3F000000

#define	EMAC_A2H_MA2H 0x0000FFFF

#define	EMAC_A3H_AE 0x80000000

#define	EMAC_A3H_SA 0x40000000

#define	EMAC_A3H_MBC 0x3F000000

#define	EMAC_A3H_MA3H 0x0000FFFF

#define	EMAC_MMC_RIM_RUGFCIM 0x00020000

#define	EMAC_MMC_RIM_RAEFACIM 0x00000040

#define	EMAC_MMC_RIM_RCEFCIM 0x00000020

#define	EMAC_MMC_TIM_TGFCIM 0x00200000

#define	EMAC_MMC_TIM_TMCGFCIM 0x00008000

#define	EMAC_MMC_TIM_TSCGFCIM 0x00004000

#define	EMAC_DMA_BM_AAB 0x02000000

#define	EMAC_DMA_BM_PBLX8 0x01000000

#define	EMAC_DMA_BM_USP 0x00800000

#define	EMAC_DMA_BM_RDP 0x007E0000

#define	EMAC_DMA_BM_RDP_1 0x00020000

#define	EMAC_DMA_BM_RDP_2 0x00040000

#define	EMAC_DMA_BM_RDP_4 0x00080000

#define	EMAC_DMA_BM_RDP_8 0x00100000

#define	EMAC_DMA_BM_RDP_16 0x00200000

#define	EMAC_DMA_BM_RDP_32 0x00400000

#define	EMAC_DMA_BM_FB 0x00010000

#define	EMAC_DMA_BM_PR 0x0000C000

#define	EMAC_DMA_BM_PR_1_1 0x00000000

#define	EMAC_DMA_BM_PR_2_1 0x00004000

#define	EMAC_DMA_BM_PR_3_1 0x00008000

#define	EMAC_DMA_BM_PR_4_1 0x0000C000

#define	EMAC_DMA_BM_PBL 0x00003F00

#define	EMAC_DMA_BM_PBL_1 0x00000100

#define	EMAC_DMA_BM_PBL_2 0x00000200

#define	EMAC_DMA_BM_PBL_4 0x00000400

#define	EMAC_DMA_BM_PBL_8 0x00000800

#define	EMAC_DMA_BM_PBL_16 0x00001000

#define	EMAC_DMA_BM_PBL_32 0x00002000

#define	EMAC_DMA_BM_DSL 0x0000007C

#define	EMAC_DMA_BM_DSL_0 0x00000000

#define	EMAC_DMA_BM_DSL_1 0x00000004

#define	EMAC_DMA_BM_DSL_2 0x00000008

#define	EMAC_DMA_BM_DSL_4 0x00000010

#define	EMAC_DMA_BM_DSL_8 0x00000020

#define	EMAC_DMA_BM_DSL_16 0x00000040

#define	EMAC_DMA_BM_DA 0x00000002

#define	EMAC_DMA_BM_SWR 0x00000001

#define	EMAC_DMA_STS_TTI 0x20000000

#define	EMAC_DMA_STS_MPI 0x10000000

#define	EMAC_DMA_STS_MMI 0x08000000

#define	EMAC_DMA_STS_EB 0x03800000

#define	EMAC_DMA_STS_TS 0x00700000

#define	EMAC_DMA_STS_RS 0x000E0000

#define	EMAC_DMA_STS_NIS 0x00010000

#define	EMAC_DMA_STS_AIS 0x00008000

#define	EMAC_DMA_STS_ERI 0x00004000

#define	EMAC_DMA_STS_FBEI 0x00002000

#define	EMAC_DMA_STS_ETI 0x00000400

#define	EMAC_DMA_STS_RWT 0x00000200

#define	EMAC_DMA_STS_RPS 0x00000100

#define	EMAC_DMA_STS_RBU 0x00000080

#define	EMAC_DMA_STS_RI 0x00000040

#define	EMAC_DMA_STS_UNF 0x00000020

#define	EMAC_DMA_STS_OVF 0x00000010

#define	EMAC_DMA_STS_TJT 0x00000008

#define	EMAC_DMA_STS_TBU 0x00000004

#define	EMAC_DMA_STS_TPS 0x00000002

#define	EMAC_DMA_STS_TI 0x00000001

#define	EMAC_DMA_OPM_DT 0x04000000

#define	EMAC_DMA_OPM_RSF 0x02000000

#define	EMAC_DMA_OPM_DFRF 0x01000000

#define	EMAC_DMA_OPM_TSF 0x00200000

#define	EMAC_DMA_OPM_FTF 0x00100000

#define	EMAC_DMA_OPM_TTC 0x0001C000

#define	EMAC_DMA_OPM_SSTC 0x00002000

#define	EMAC_DMA_OPM_FEF 0x00000080

#define	EMAC_DMA_OPM_FUGF 0x00000040

#define	EMAC_DMA_OPM_RTC 0x00000018

#define	EMAC_DMA_OPM_OSF 0x00000004

#define	EMAC_DMA_OPM_SSR 0x00000002

#define	EMAC_DMA_IE_NIE 0x00010000

#define	EMAC_DMA_IE_AIE 0x00008000

#define	EMAC_DMA_IE_ERE 0x00004000

#define	EMAC_DMA_IE_FBEE 0x00002000

#define	EMAC_DMA_IE_EIE 0x00000400

#define	EMAC_DMA_IE_RWTE 0x00000200

#define	EMAC_DMA_IE_RSE 0x00000100

#define	EMAC_DMA_IE_RBUE 0x00000080

#define	EMAC_DMA_IE_RIE 0x00000040

#define	EMAC_DMA_IE_UNE 0x00000020

#define	EMAC_DMA_IE_OVE 0x00000010

#define	EMAC_DMA_IE_TJE 0x00000008

#define	EMAC_DMA_IE_TUE 0x00000004

#define	EMAC_DMA_IE_TSE 0x00000002

#define	EMAC_DMA_IE_TIE 0x00000001

#define	EMAC_TDES0_OWN 0x80000000

#define	EMAC_TDES0_IC 0x40000000

#define	EMAC_TDES0_LS 0x20000000

#define	EMAC_TDES0_FS 0x10000000

#define	EMAC_TDES0_DC 0x08000000

#define	EMAC_TDES0_DP 0x04000000

#define	EMAC_TDES0_TTSE 0x02000000

#define	EMAC_TDES0_CIC 0x00C00000

#define	EMAC_TDES0_TER 0x00200000

#define	EMAC_TDES0_TCH 0x00100000

#define	EMAC_TDES0_TTSS 0x00020000

#define	EMAC_TDES0_IHE 0x00010000

#define	EMAC_TDES0_ES 0x00008000

#define	EMAC_TDES0_JT 0x00004000

#define	EMAC_TDES0_FF 0x00002000

#define	EMAC_TDES0_IPE 0x00001000

#define	EMAC_TDES0_LOC 0x00000800

#define	EMAC_TDES0_NC 0x00000400

#define	EMAC_TDES0_LC 0x00000200

#define	EMAC_TDES0_EC 0x00000100

#define	EMAC_TDES0_VF 0x00000080

#define	EMAC_TDES0_CC 0x00000078

#define	EMAC_TDES0_ED 0x00000004

#define	EMAC_TDES0_UF 0x00000002

#define	EMAC_TDES0_DB 0x00000001

#define	EMAC_TDES1_TBS2 0x1FFF0000

#define	EMAC_TDES1_TBS1 0x00001FFF

#define	EMAC_TDES2_TBAP1 0xFFFFFFFF

#define	EMAC_TDES3_TBAP2 0xFFFFFFFF

#define	EMAC_RDES0_OWN 0x80000000

#define	EMAC_RDES0_AFM 0x40000000

#define	EMAC_RDES0_FL 0x3FFF0000

#define	EMAC_RDES0_ES 0x00008000

#define	EMAC_RDES0_DE 0x00004000

#define	EMAC_RDES0_SAF 0x00002000

#define	EMAC_RDES0_LE 0x00001000

#define	EMAC_RDES0_OE 0x00000800

#define	EMAC_RDES0_VLAN 0x00000400

#define	EMAC_RDES0_FS 0x00000200

#define	EMAC_RDES0_LS 0x00000100

#define	EMAC_RDES0_IPHCE 0x00000080

#define	EMAC_RDES0_LC 0x00000040

#define	EMAC_RDES0_FT 0x00000020

#define	EMAC_RDES0_RWT 0x00000010

#define	EMAC_RDES0_RE 0x00000008

#define	EMAC_RDES0_DBE 0x00000004

#define	EMAC_RDES0_CE 0x00000002

#define	EMAC_RDES0_PCE 0x00000001

#define	EMAC_RDES1_DIC 0x80000000

#define	EMAC_RDES1_RBS2 0x1FFF0000

#define	EMAC_RDES1_RER 0x00008000

#define	EMAC_RDES1_RCH 0x00004000

#define	EMAC_RDES1_RBS1 0x00001FFF

#define	EMAC_RDES2_RBAP1 0xFFFFFFFF

#define	EMAC_RDES3_RBAP2 0xFFFFFFFF

Functions
error_t	at32f4xxEthInit (NetInterface *interface)
	AT32F4 Ethernet MAC initialization. More...

void	at32f4xxEthInitGpio (NetInterface *interface)
	GPIO configuration. More...

void	at32f4xxEthInitDmaDesc (NetInterface *interface)
	Initialize DMA descriptor lists. More...

void	at32f4xxEthTick (NetInterface *interface)
	AT32F4 Ethernet MAC timer handler. More...

void	at32f4xxEthEnableIrq (NetInterface *interface)
	Enable interrupts. More...

void	at32f4xxEthDisableIrq (NetInterface *interface)
	Disable interrupts. More...

void	at32f4xxEthEventHandler (NetInterface *interface)
	AT32F4 Ethernet MAC event handler. More...

error_t	at32f4xxEthSendPacket (NetInterface interface, const NetBuffer buffer, size_t offset, NetTxAncillary *ancillary)
	Send a packet. More...

error_t	at32f4xxEthReceivePacket (NetInterface *interface)
	Receive a packet. More...

error_t	at32f4xxEthUpdateMacAddrFilter (NetInterface *interface)
	Configure MAC address filtering. More...

error_t	at32f4xxEthUpdateMacConfig (NetInterface *interface)
	Adjust MAC configuration parameters for proper operation. More...

void	at32f4xxEthWritePhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
	Write PHY register. More...

uint16_t	at32f4xxEthReadPhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
	Read PHY register. More...

uint32_t	at32f4xxEthCalcCrc (const void *data, size_t length)
	CRC calculation. More...

Variables
const NicDriver	at32f4xxEthDriver
	AT32F4 Ethernet MAC driver. More...

Detailed Description

Artery AT32F4 Ethernet MAC driver.

License

SPDX-License-Identifier: GPL-2.0-or-later

This file is part of CycloneTCP Open.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Author: Oryx Embedded SARL (www.oryx-embedded.com)

Version: 2.4.4

Definition in file at32f4xx_eth_driver.h.

Macro Definition Documentation

◆ AT32F4XX_ETH_IRQ_GROUP_PRIORITY

#define AT32F4XX_ETH_IRQ_GROUP_PRIORITY 12

Definition at line 74 of file at32f4xx_eth_driver.h.

◆ AT32F4XX_ETH_IRQ_PRIORITY_GROUPING

#define AT32F4XX_ETH_IRQ_PRIORITY_GROUPING 3

Definition at line 67 of file at32f4xx_eth_driver.h.

◆ AT32F4XX_ETH_IRQ_SUB_PRIORITY

#define AT32F4XX_ETH_IRQ_SUB_PRIORITY 0

Definition at line 81 of file at32f4xx_eth_driver.h.

◆ AT32F4XX_ETH_RX_BUFFER_COUNT

#define AT32F4XX_ETH_RX_BUFFER_COUNT 6

Definition at line 53 of file at32f4xx_eth_driver.h.

◆ AT32F4XX_ETH_RX_BUFFER_SIZE

#define AT32F4XX_ETH_RX_BUFFER_SIZE 1536

Definition at line 60 of file at32f4xx_eth_driver.h.

◆ AT32F4XX_ETH_TX_BUFFER_COUNT

#define AT32F4XX_ETH_TX_BUFFER_COUNT 3

Definition at line 39 of file at32f4xx_eth_driver.h.

◆ AT32F4XX_ETH_TX_BUFFER_SIZE

#define AT32F4XX_ETH_TX_BUFFER_SIZE 1536

Definition at line 46 of file at32f4xx_eth_driver.h.

◆ EMAC_A0H_AE

#define EMAC_A0H_AE 0x80000000

Definition at line 138 of file at32f4xx_eth_driver.h.

◆ EMAC_A0H_MA0H

#define EMAC_A0H_MA0H 0x0000FFFF

Definition at line 139 of file at32f4xx_eth_driver.h.

◆ EMAC_A1H_AE

#define EMAC_A1H_AE 0x80000000

Definition at line 142 of file at32f4xx_eth_driver.h.

◆ EMAC_A1H_MA1H

#define EMAC_A1H_MA1H 0x0000FFFF

Definition at line 145 of file at32f4xx_eth_driver.h.

◆ EMAC_A1H_MBC

#define EMAC_A1H_MBC 0x3F000000

Definition at line 144 of file at32f4xx_eth_driver.h.

◆ EMAC_A1H_SA

#define EMAC_A1H_SA 0x40000000

Definition at line 143 of file at32f4xx_eth_driver.h.

◆ EMAC_A2H_AE

#define EMAC_A2H_AE 0x80000000

Definition at line 148 of file at32f4xx_eth_driver.h.

◆ EMAC_A2H_MA2H

#define EMAC_A2H_MA2H 0x0000FFFF

Definition at line 151 of file at32f4xx_eth_driver.h.

◆ EMAC_A2H_MBC

#define EMAC_A2H_MBC 0x3F000000

Definition at line 150 of file at32f4xx_eth_driver.h.

◆ EMAC_A2H_SA

#define EMAC_A2H_SA 0x40000000

Definition at line 149 of file at32f4xx_eth_driver.h.

◆ EMAC_A3H_AE

#define EMAC_A3H_AE 0x80000000

Definition at line 154 of file at32f4xx_eth_driver.h.

◆ EMAC_A3H_MA3H

#define EMAC_A3H_MA3H 0x0000FFFF

Definition at line 157 of file at32f4xx_eth_driver.h.

◆ EMAC_A3H_MBC

#define EMAC_A3H_MBC 0x3F000000

Definition at line 156 of file at32f4xx_eth_driver.h.

◆ EMAC_A3H_SA

#define EMAC_A3H_SA 0x40000000

Definition at line 155 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_ACS

#define EMAC_CTRL_ACS 0x00000080

Definition at line 98 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_BL

#define EMAC_CTRL_BL 0x00000060

Definition at line 99 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_DC

#define EMAC_CTRL_DC 0x00000010

Definition at line 100 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_DCS

#define EMAC_CTRL_DCS 0x00010000

Definition at line 90 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_DM

#define EMAC_CTRL_DM 0x00000800

Definition at line 95 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_DR

#define EMAC_CTRL_DR 0x00000200

Definition at line 97 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_DRO

#define EMAC_CTRL_DRO 0x00002000

Definition at line 93 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_FES

#define EMAC_CTRL_FES 0x00004000

Definition at line 92 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_IFG

#define EMAC_CTRL_IFG 0x000E0000

Definition at line 89 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_IPC

#define EMAC_CTRL_IPC 0x00000400

Definition at line 96 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_JD

#define EMAC_CTRL_JD 0x00400000

Definition at line 88 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_LM

#define EMAC_CTRL_LM 0x00001000

Definition at line 94 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_RE

#define EMAC_CTRL_RE 0x00000004

Definition at line 102 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_RESERVED15

#define EMAC_CTRL_RESERVED15 0x00008000

Definition at line 91 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_TE

#define EMAC_CTRL_TE 0x00000008

Definition at line 101 of file at32f4xx_eth_driver.h.

◆ EMAC_CTRL_WD

#define EMAC_CTRL_WD 0x00800000

Definition at line 87 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_AAB

#define EMAC_DMA_BM_AAB 0x02000000

Definition at line 170 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_DA

#define EMAC_DMA_BM_DA 0x00000002

Definition at line 200 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_DSL

#define EMAC_DMA_BM_DSL 0x0000007C

Definition at line 193 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_DSL_0

#define EMAC_DMA_BM_DSL_0 0x00000000

Definition at line 194 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_DSL_1

#define EMAC_DMA_BM_DSL_1 0x00000004

Definition at line 195 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_DSL_16

#define EMAC_DMA_BM_DSL_16 0x00000040

Definition at line 199 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_DSL_2

#define EMAC_DMA_BM_DSL_2 0x00000008

Definition at line 196 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_DSL_4

#define EMAC_DMA_BM_DSL_4 0x00000010

Definition at line 197 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_DSL_8

#define EMAC_DMA_BM_DSL_8 0x00000020

Definition at line 198 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_FB

#define EMAC_DMA_BM_FB 0x00010000

Definition at line 180 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PBL

#define EMAC_DMA_BM_PBL 0x00003F00

Definition at line 186 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PBL_1

#define EMAC_DMA_BM_PBL_1 0x00000100

Definition at line 187 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PBL_16

#define EMAC_DMA_BM_PBL_16 0x00001000

Definition at line 191 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PBL_2

#define EMAC_DMA_BM_PBL_2 0x00000200

Definition at line 188 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PBL_32

#define EMAC_DMA_BM_PBL_32 0x00002000

Definition at line 192 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PBL_4

#define EMAC_DMA_BM_PBL_4 0x00000400

Definition at line 189 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PBL_8

#define EMAC_DMA_BM_PBL_8 0x00000800

Definition at line 190 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PBLX8

#define EMAC_DMA_BM_PBLX8 0x01000000

Definition at line 171 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PR

#define EMAC_DMA_BM_PR 0x0000C000

Definition at line 181 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PR_1_1

#define EMAC_DMA_BM_PR_1_1 0x00000000

Definition at line 182 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PR_2_1

#define EMAC_DMA_BM_PR_2_1 0x00004000

Definition at line 183 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PR_3_1

#define EMAC_DMA_BM_PR_3_1 0x00008000

Definition at line 184 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_PR_4_1

#define EMAC_DMA_BM_PR_4_1 0x0000C000

Definition at line 185 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_RDP

#define EMAC_DMA_BM_RDP 0x007E0000

Definition at line 173 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_RDP_1

#define EMAC_DMA_BM_RDP_1 0x00020000

Definition at line 174 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_RDP_16

#define EMAC_DMA_BM_RDP_16 0x00200000

Definition at line 178 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_RDP_2

#define EMAC_DMA_BM_RDP_2 0x00040000

Definition at line 175 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_RDP_32

#define EMAC_DMA_BM_RDP_32 0x00400000

Definition at line 179 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_RDP_4

#define EMAC_DMA_BM_RDP_4 0x00080000

Definition at line 176 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_RDP_8

#define EMAC_DMA_BM_RDP_8 0x00100000

Definition at line 177 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_SWR

#define EMAC_DMA_BM_SWR 0x00000001

Definition at line 201 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_BM_USP

#define EMAC_DMA_BM_USP 0x00800000

Definition at line 172 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_AIE

#define EMAC_DMA_IE_AIE 0x00008000

Definition at line 242 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_EIE

#define EMAC_DMA_IE_EIE 0x00000400

Definition at line 245 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_ERE

#define EMAC_DMA_IE_ERE 0x00004000

Definition at line 243 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_FBEE

#define EMAC_DMA_IE_FBEE 0x00002000

Definition at line 244 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_NIE

#define EMAC_DMA_IE_NIE 0x00010000

Definition at line 241 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_OVE

#define EMAC_DMA_IE_OVE 0x00000010

Definition at line 251 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_RBUE

#define EMAC_DMA_IE_RBUE 0x00000080

Definition at line 248 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_RIE

#define EMAC_DMA_IE_RIE 0x00000040

Definition at line 249 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_RSE

#define EMAC_DMA_IE_RSE 0x00000100

Definition at line 247 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_RWTE

#define EMAC_DMA_IE_RWTE 0x00000200

Definition at line 246 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_TIE

#define EMAC_DMA_IE_TIE 0x00000001

Definition at line 255 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_TJE

#define EMAC_DMA_IE_TJE 0x00000008

Definition at line 252 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_TSE

#define EMAC_DMA_IE_TSE 0x00000002

Definition at line 254 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_TUE

#define EMAC_DMA_IE_TUE 0x00000004

Definition at line 253 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_IE_UNE

#define EMAC_DMA_IE_UNE 0x00000020

Definition at line 250 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_DFRF

#define EMAC_DMA_OPM_DFRF 0x01000000

Definition at line 229 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_DT

#define EMAC_DMA_OPM_DT 0x04000000

Definition at line 227 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_FEF

#define EMAC_DMA_OPM_FEF 0x00000080

Definition at line 234 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_FTF

#define EMAC_DMA_OPM_FTF 0x00100000

Definition at line 231 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_FUGF

#define EMAC_DMA_OPM_FUGF 0x00000040

Definition at line 235 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_OSF

#define EMAC_DMA_OPM_OSF 0x00000004

Definition at line 237 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_RSF

#define EMAC_DMA_OPM_RSF 0x02000000

Definition at line 228 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_RTC

#define EMAC_DMA_OPM_RTC 0x00000018

Definition at line 236 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_SSR

#define EMAC_DMA_OPM_SSR 0x00000002

Definition at line 238 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_SSTC

#define EMAC_DMA_OPM_SSTC 0x00002000

Definition at line 233 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_TSF

#define EMAC_DMA_OPM_TSF 0x00200000

Definition at line 230 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_OPM_TTC

#define EMAC_DMA_OPM_TTC 0x0001C000

Definition at line 232 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_AIS

#define EMAC_DMA_STS_AIS 0x00008000

Definition at line 211 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_EB

#define EMAC_DMA_STS_EB 0x03800000

Definition at line 207 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_ERI

#define EMAC_DMA_STS_ERI 0x00004000

Definition at line 212 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_ETI

#define EMAC_DMA_STS_ETI 0x00000400

Definition at line 214 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_FBEI

#define EMAC_DMA_STS_FBEI 0x00002000

Definition at line 213 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_MMI

#define EMAC_DMA_STS_MMI 0x08000000

Definition at line 206 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_MPI

#define EMAC_DMA_STS_MPI 0x10000000

Definition at line 205 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_NIS

#define EMAC_DMA_STS_NIS 0x00010000

Definition at line 210 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_OVF

#define EMAC_DMA_STS_OVF 0x00000010

Definition at line 220 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_RBU

#define EMAC_DMA_STS_RBU 0x00000080

Definition at line 217 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_RI

#define EMAC_DMA_STS_RI 0x00000040

Definition at line 218 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_RPS

#define EMAC_DMA_STS_RPS 0x00000100

Definition at line 216 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_RS

#define EMAC_DMA_STS_RS 0x000E0000

Definition at line 209 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_RWT

#define EMAC_DMA_STS_RWT 0x00000200

Definition at line 215 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_TBU

#define EMAC_DMA_STS_TBU 0x00000004

Definition at line 222 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_TI

#define EMAC_DMA_STS_TI 0x00000001

Definition at line 224 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_TJT

#define EMAC_DMA_STS_TJT 0x00000008

Definition at line 221 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_TPS

#define EMAC_DMA_STS_TPS 0x00000002

Definition at line 223 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_TS

#define EMAC_DMA_STS_TS 0x00700000

Definition at line 208 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_TTI

#define EMAC_DMA_STS_TTI 0x20000000

Definition at line 204 of file at32f4xx_eth_driver.h.

◆ EMAC_DMA_STS_UNF

#define EMAC_DMA_STS_UNF 0x00000020

Definition at line 219 of file at32f4xx_eth_driver.h.

◆ EMAC_FRMF_DAIF

#define EMAC_FRMF_DAIF 0x00000008

Definition at line 112 of file at32f4xx_eth_driver.h.

◆ EMAC_FRMF_DBF

#define EMAC_FRMF_DBF 0x00000020

Definition at line 110 of file at32f4xx_eth_driver.h.

◆ EMAC_FRMF_HMC

#define EMAC_FRMF_HMC 0x00000004

Definition at line 113 of file at32f4xx_eth_driver.h.

◆ EMAC_FRMF_HPF

#define EMAC_FRMF_HPF 0x00000400

Definition at line 106 of file at32f4xx_eth_driver.h.

◆ EMAC_FRMF_HUC

#define EMAC_FRMF_HUC 0x00000002

Definition at line 114 of file at32f4xx_eth_driver.h.

◆ EMAC_FRMF_PCF

#define EMAC_FRMF_PCF 0x000000C0

Definition at line 109 of file at32f4xx_eth_driver.h.

◆ EMAC_FRMF_PMC

#define EMAC_FRMF_PMC 0x00000010

Definition at line 111 of file at32f4xx_eth_driver.h.

◆ EMAC_FRMF_PR

#define EMAC_FRMF_PR 0x00000001

Definition at line 115 of file at32f4xx_eth_driver.h.

◆ EMAC_FRMF_RA

#define EMAC_FRMF_RA 0x80000000

Definition at line 105 of file at32f4xx_eth_driver.h.

◆ EMAC_FRMF_SAF

#define EMAC_FRMF_SAF 0x00000200

Definition at line 107 of file at32f4xx_eth_driver.h.

◆ EMAC_FRMF_SAIF

#define EMAC_FRMF_SAIF 0x00000100

Definition at line 108 of file at32f4xx_eth_driver.h.

◆ EMAC_IMR_PIM

#define EMAC_IMR_PIM 0x00000008

Definition at line 135 of file at32f4xx_eth_driver.h.

◆ EMAC_IMR_TIM

#define EMAC_IMR_TIM 0x00000200

Definition at line 134 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIADDR_CR

#define EMAC_MIIADDR_CR 0x0000003C

Definition at line 120 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIADDR_CR_DIV_102

#define EMAC_MIIADDR_CR_DIV_102 0x00000010

Definition at line 125 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIADDR_CR_DIV_124

#define EMAC_MIIADDR_CR_DIV_124 0x00000014

Definition at line 126 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIADDR_CR_DIV_16

#define EMAC_MIIADDR_CR_DIV_16 0x00000008

Definition at line 123 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIADDR_CR_DIV_26

#define EMAC_MIIADDR_CR_DIV_26 0x0000000C

Definition at line 124 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIADDR_CR_DIV_42

#define EMAC_MIIADDR_CR_DIV_42 0x00000000

Definition at line 121 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIADDR_CR_DIV_62

#define EMAC_MIIADDR_CR_DIV_62 0x00000004

Definition at line 122 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIADDR_MB

#define EMAC_MIIADDR_MB 0x00000001

Definition at line 128 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIADDR_MII

#define EMAC_MIIADDR_MII 0x000007C0

Definition at line 119 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIADDR_MW

#define EMAC_MIIADDR_MW 0x00000002

Definition at line 127 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIADDR_PA

#define EMAC_MIIADDR_PA 0x0000F800

Definition at line 118 of file at32f4xx_eth_driver.h.

◆ EMAC_MIIDT_MD

#define EMAC_MIIDT_MD 0x0000FFFF

Definition at line 131 of file at32f4xx_eth_driver.h.

◆ EMAC_MMC_RIM_RAEFACIM

#define EMAC_MMC_RIM_RAEFACIM 0x00000040

Definition at line 161 of file at32f4xx_eth_driver.h.

◆ EMAC_MMC_RIM_RCEFCIM

#define EMAC_MMC_RIM_RCEFCIM 0x00000020

Definition at line 162 of file at32f4xx_eth_driver.h.

◆ EMAC_MMC_RIM_RUGFCIM

#define EMAC_MMC_RIM_RUGFCIM 0x00020000

Definition at line 160 of file at32f4xx_eth_driver.h.

◆ EMAC_MMC_TIM_TGFCIM

#define EMAC_MMC_TIM_TGFCIM 0x00200000

Definition at line 165 of file at32f4xx_eth_driver.h.

◆ EMAC_MMC_TIM_TMCGFCIM

#define EMAC_MMC_TIM_TMCGFCIM 0x00008000

Definition at line 166 of file at32f4xx_eth_driver.h.

◆ EMAC_MMC_TIM_TSCGFCIM

#define EMAC_MMC_TIM_TSCGFCIM 0x00004000

Definition at line 167 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_AFM

#define EMAC_RDES0_AFM 0x40000000

Definition at line 290 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_CE

#define EMAC_RDES0_CE 0x00000002

Definition at line 306 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_DBE

#define EMAC_RDES0_DBE 0x00000004

Definition at line 305 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_DE

#define EMAC_RDES0_DE 0x00004000

Definition at line 293 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_ES

#define EMAC_RDES0_ES 0x00008000

Definition at line 292 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_FL

#define EMAC_RDES0_FL 0x3FFF0000

Definition at line 291 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_FS

#define EMAC_RDES0_FS 0x00000200

Definition at line 298 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_FT

#define EMAC_RDES0_FT 0x00000020

Definition at line 302 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_IPHCE

#define EMAC_RDES0_IPHCE 0x00000080

Definition at line 300 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_LC

#define EMAC_RDES0_LC 0x00000040

Definition at line 301 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_LE

#define EMAC_RDES0_LE 0x00001000

Definition at line 295 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_LS

#define EMAC_RDES0_LS 0x00000100

Definition at line 299 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_OE

#define EMAC_RDES0_OE 0x00000800

Definition at line 296 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_OWN

#define EMAC_RDES0_OWN 0x80000000

Definition at line 289 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_PCE

#define EMAC_RDES0_PCE 0x00000001

Definition at line 307 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_RE

#define EMAC_RDES0_RE 0x00000008

Definition at line 304 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_RWT

#define EMAC_RDES0_RWT 0x00000010

Definition at line 303 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_SAF

#define EMAC_RDES0_SAF 0x00002000

Definition at line 294 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES0_VLAN

#define EMAC_RDES0_VLAN 0x00000400

Definition at line 297 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES1_DIC

#define EMAC_RDES1_DIC 0x80000000

Definition at line 308 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES1_RBS1

#define EMAC_RDES1_RBS1 0x00001FFF

Definition at line 312 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES1_RBS2

#define EMAC_RDES1_RBS2 0x1FFF0000

Definition at line 309 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES1_RCH

#define EMAC_RDES1_RCH 0x00004000

Definition at line 311 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES1_RER

#define EMAC_RDES1_RER 0x00008000

Definition at line 310 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES2_RBAP1

#define EMAC_RDES2_RBAP1 0xFFFFFFFF

Definition at line 313 of file at32f4xx_eth_driver.h.

◆ EMAC_RDES3_RBAP2

#define EMAC_RDES3_RBAP2 0xFFFFFFFF

Definition at line 314 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_CC

#define EMAC_TDES0_CC 0x00000078

Definition at line 279 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_CIC

#define EMAC_TDES0_CIC 0x00C00000

Definition at line 265 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_DB

#define EMAC_TDES0_DB 0x00000001

Definition at line 282 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_DC

#define EMAC_TDES0_DC 0x08000000

Definition at line 262 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_DP

#define EMAC_TDES0_DP 0x04000000

Definition at line 263 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_EC

#define EMAC_TDES0_EC 0x00000100

Definition at line 277 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_ED

#define EMAC_TDES0_ED 0x00000004

Definition at line 280 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_ES

#define EMAC_TDES0_ES 0x00008000

Definition at line 270 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_FF

#define EMAC_TDES0_FF 0x00002000

Definition at line 272 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_FS

#define EMAC_TDES0_FS 0x10000000

Definition at line 261 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_IC

#define EMAC_TDES0_IC 0x40000000

Definition at line 259 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_IHE

#define EMAC_TDES0_IHE 0x00010000

Definition at line 269 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_IPE

#define EMAC_TDES0_IPE 0x00001000

Definition at line 273 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_JT

#define EMAC_TDES0_JT 0x00004000

Definition at line 271 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_LC

#define EMAC_TDES0_LC 0x00000200

Definition at line 276 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_LOC

#define EMAC_TDES0_LOC 0x00000800

Definition at line 274 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_LS

#define EMAC_TDES0_LS 0x20000000

Definition at line 260 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_NC

#define EMAC_TDES0_NC 0x00000400

Definition at line 275 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_OWN

#define EMAC_TDES0_OWN 0x80000000

Definition at line 258 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_TCH

#define EMAC_TDES0_TCH 0x00100000

Definition at line 267 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_TER

#define EMAC_TDES0_TER 0x00200000

Definition at line 266 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_TTSE

#define EMAC_TDES0_TTSE 0x02000000

Definition at line 264 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_TTSS

#define EMAC_TDES0_TTSS 0x00020000

Definition at line 268 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_UF

#define EMAC_TDES0_UF 0x00000002

Definition at line 281 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES0_VF

#define EMAC_TDES0_VF 0x00000080

Definition at line 278 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES1_TBS1

#define EMAC_TDES1_TBS1 0x00001FFF

Definition at line 284 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES1_TBS2

#define EMAC_TDES1_TBS2 0x1FFF0000

Definition at line 283 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES2_TBAP1

#define EMAC_TDES2_TBAP1 0xFFFFFFFF

Definition at line 285 of file at32f4xx_eth_driver.h.

◆ EMAC_TDES3_TBAP2

#define EMAC_TDES3_TBAP2 0xFFFFFFFF

Definition at line 286 of file at32f4xx_eth_driver.h.

Function Documentation

◆ at32f4xxEthCalcCrc()

uint32_t at32f4xxEthCalcCrc	(	const void *	data,
		size_t	length
	)

CRC calculation.

Parameters

[in]	data	Pointer to the data over which to calculate the CRC
[in]	length	Number of bytes to process

Returns: Resulting CRC value

Definition at line 1025 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthDisableIrq()

void at32f4xxEthDisableIrq ( NetInterface * interface )

Disable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 538 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthEnableIrq()

void at32f4xxEthEnableIrq ( NetInterface * interface )

Enable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 510 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthEventHandler()

void at32f4xxEthEventHandler ( NetInterface * interface )

AT32F4 Ethernet MAC event handler.

Parameters

[in] interface Underlying network interface

Definition at line 618 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthInit()

error_t at32f4xxEthInit ( NetInterface * interface )

AT32F4 Ethernet MAC initialization.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 124 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthInitDmaDesc()

void at32f4xxEthInitDmaDesc ( NetInterface * interface )

Initialize DMA descriptor lists.

Parameters

[in] interface Underlying network interface

Definition at line 429 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthInitGpio()

void at32f4xxEthInitGpio ( NetInterface * interface )

GPIO configuration.

Parameters

[in] interface Underlying network interface

Definition at line 252 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthReadPhyReg()

uint16_t at32f4xxEthReadPhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr
	)

Read PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)

Returns: Register value

Definition at line 979 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthReceivePacket()

error_t at32f4xxEthReceivePacket ( NetInterface * interface )

Receive a packet.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 702 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthSendPacket()

error_t at32f4xxEthSendPacket	(	NetInterface *	interface,
		const NetBuffer *	buffer,
		size_t	offset,
		NetTxAncillary *	ancillary
	)

Send a packet.

Parameters

[in]	interface	Underlying network interface
[in]	buffer	Multi-part buffer containing the data to send
[in]	offset	Offset to the first data byte
[in]	ancillary	Additional options passed to the stack along with the packet

Returns: Error code

Definition at line 643 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthTick()

void at32f4xxEthTick ( NetInterface * interface )

AT32F4 Ethernet MAC timer handler.

This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state

Parameters

[in] interface Underlying network interface

Definition at line 485 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthUpdateMacAddrFilter()

error_t at32f4xxEthUpdateMacAddrFilter ( NetInterface * interface )

Configure MAC address filtering.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 772 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthUpdateMacConfig()

error_t at32f4xxEthUpdateMacConfig ( NetInterface * interface )

Adjust MAC configuration parameters for proper operation.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 894 of file at32f4xx_eth_driver.c.

◆ at32f4xxEthWritePhyReg()

void at32f4xxEthWritePhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr,
		uint16_t	data
	)

Write PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)
[in]	data	Register value

Definition at line 937 of file at32f4xx_eth_driver.c.

Variable Documentation

◆ at32f4xxEthDriver

const NicDriver at32f4xxEthDriver

extern

AT32F4 Ethernet MAC driver.

Definition at line 97 of file at32f4xx_eth_driver.c.

Data Structures

Macros

Functions

Variables

Detailed Description

License

Macro Definition Documentation

◆ AT32F4XX_ETH_IRQ_GROUP_PRIORITY

◆ AT32F4XX_ETH_IRQ_PRIORITY_GROUPING

◆ AT32F4XX_ETH_IRQ_SUB_PRIORITY

◆ AT32F4XX_ETH_RX_BUFFER_COUNT

◆ AT32F4XX_ETH_RX_BUFFER_SIZE

◆ AT32F4XX_ETH_TX_BUFFER_COUNT

◆ AT32F4XX_ETH_TX_BUFFER_SIZE

◆ EMAC_A0H_AE

◆ EMAC_A0H_MA0H

◆ EMAC_A1H_AE

◆ EMAC_A1H_MA1H

◆ EMAC_A1H_MBC

◆ EMAC_A1H_SA

◆ EMAC_A2H_AE

◆ EMAC_A2H_MA2H

◆ EMAC_A2H_MBC

◆ EMAC_A2H_SA

◆ EMAC_A3H_AE

◆ EMAC_A3H_MA3H

◆ EMAC_A3H_MBC

◆ EMAC_A3H_SA

◆ EMAC_CTRL_ACS

◆ EMAC_CTRL_BL

◆ EMAC_CTRL_DC

◆ EMAC_CTRL_DCS

◆ EMAC_CTRL_DM

◆ EMAC_CTRL_DR

◆ EMAC_CTRL_DRO

◆ EMAC_CTRL_FES

◆ EMAC_CTRL_IFG

◆ EMAC_CTRL_IPC

◆ EMAC_CTRL_JD

◆ EMAC_CTRL_LM

◆ EMAC_CTRL_RE

◆ EMAC_CTRL_RESERVED15

◆ EMAC_CTRL_TE

◆ EMAC_CTRL_WD

◆ EMAC_DMA_BM_AAB

◆ EMAC_DMA_BM_DA

◆ EMAC_DMA_BM_DSL

◆ EMAC_DMA_BM_DSL_0

◆ EMAC_DMA_BM_DSL_1

◆ EMAC_DMA_BM_DSL_16

◆ EMAC_DMA_BM_DSL_2

◆ EMAC_DMA_BM_DSL_4

◆ EMAC_DMA_BM_DSL_8

◆ EMAC_DMA_BM_FB

◆ EMAC_DMA_BM_PBL

◆ EMAC_DMA_BM_PBL_1

◆ EMAC_DMA_BM_PBL_16

◆ EMAC_DMA_BM_PBL_2

◆ EMAC_DMA_BM_PBL_32

◆ EMAC_DMA_BM_PBL_4

◆ EMAC_DMA_BM_PBL_8

◆ EMAC_DMA_BM_PBLX8

◆ EMAC_DMA_BM_PR

◆ EMAC_DMA_BM_PR_1_1

◆ EMAC_DMA_BM_PR_2_1

◆ EMAC_DMA_BM_PR_3_1

◆ EMAC_DMA_BM_PR_4_1

◆ EMAC_DMA_BM_RDP

◆ EMAC_DMA_BM_RDP_1

◆ EMAC_DMA_BM_RDP_16

◆ EMAC_DMA_BM_RDP_2

◆ EMAC_DMA_BM_RDP_32

◆ EMAC_DMA_BM_RDP_4

◆ EMAC_DMA_BM_RDP_8

◆ EMAC_DMA_BM_SWR

◆ EMAC_DMA_BM_USP

◆ EMAC_DMA_IE_AIE

◆ EMAC_DMA_IE_EIE

◆ EMAC_DMA_IE_ERE

◆ EMAC_DMA_IE_FBEE