dp83640_driver.h
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1 /**
2  * @file dp83640_driver.h
3  * @brief DP83640 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _DP83640_DRIVER_H
30 #define _DP83640_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef DP83640_PHY_ADDR
37  #define DP83640_PHY_ADDR 1
38 #elif (DP83640_PHY_ADDR < 0 || DP83640_PHY_ADDR > 31)
39  #error DP83640_PHY_ADDR parameter is not valid
40 #endif
41 
42 //DP83640 registers
43 #define DP83640_PHY_REG_BMCR 0x00
44 #define DP83640_PHY_REG_BMSR 0x01
45 #define DP83640_PHY_REG_PHYIDR1 0x02
46 #define DP83640_PHY_REG_PHYIDR2 0x03
47 #define DP83640_PHY_REG_ANAR 0x04
48 #define DP83640_PHY_REG_ANLPAR 0x05
49 #define DP83640_PHY_REG_ANER 0x06
50 #define DP83640_PHY_REG_ANNPTR 0x07
51 #define DP83640_PHY_REG_PHYSTS 0x10
52 #define DP83640_PHY_REG_MICR 0x11
53 #define DP83640_PHY_REG_MISR 0x12
54 #define DP83640_PHY_REG_PAGESEL 0x13
55 
56 //Extended registers (page 0)
57 #define DP83640_PHY_REG_FCSCR 0x14
58 #define DP83640_PHY_REG_RECR 0x15
59 #define DP83640_PHY_REG_PCSR 0x16
60 #define DP83640_PHY_REG_RBR 0x17
61 #define DP83640_PHY_REG_LEDCR 0x18
62 #define DP83640_PHY_REG_PHYCR 0x19
63 #define DP83640_PHY_REG_10BTSCR 0x1A
64 #define DP83640_PHY_REG_CDCTRL1 0x1B
65 #define DP83640_PHY_REG_PHYCR2 0x1C
66 #define DP83640_PHY_REG_EDCR 0x1D
67 #define DP83640_PHY_REG_PCFCR 0x1F
68 
69 //Extended registers (page 1)
70 #define DP83640_PHY_REG_SD_CNFG 0x1E
71 
72 //Extended registers (page 2)
73 #define DP83640_PHY_REG_LEN100_DET 0x14
74 #define DP83640_PHY_REG_FREQ100 0x15
75 #define DP83640_PHY_REG_TDR_CTRL 0x16
76 #define DP83640_PHY_REG_TDR_WIN 0x17
77 #define DP83640_PHY_REG_TDR_PEAK 0x18
78 #define DP83640_PHY_REG_TDR_THR 0x19
79 #define DP83640_PHY_REG_VAR_CTRL 0x1A
80 #define DP83640_PHY_REG_VAR_DAT 0x1B
81 #define DP83640_PHY_REG_LQMR 0x1D
82 #define DP83640_PHY_REG_LQDR 0x1E
83 #define DP83640_PHY_REG_LQMR2 0x1F
84 
85 //Extended registers (page 4)
86 #define DP83640_PHY_REG_PSF_CFG 0x18
87 
88 //Extended registers (page 4)
89 #define DP83640_PHY_REG_PTP_CTL 0x14
90 #define DP83640_PHY_REG_PTP_TDR 0x15
91 #define DP83640_PHY_REG_PTP_STS 0x16
92 #define DP83640_PHY_REG_PTP_TSTS 0x17
93 #define DP83640_PHY_REG_PTP_RATEL 0x18
94 #define DP83640_PHY_REG_PTP_RATEH 0x19
95 #define DP83640_PHY_REG_PTP_RDCKSUM 0x1A
96 #define DP83640_PHY_REG_PTP_WRCKSUM 0x1B
97 #define DP83640_PHY_REG_PTP_TXTS 0x1C
98 #define DP83640_PHY_REG_PTP_RXTS 0x1D
99 #define DP83640_PHY_REG_PTP_ESTS 0x1E
100 #define DP83640_PHY_REG_PTP_EDATA 0x1F
101 
102 //Extended registers (page 5)
103 #define DP83640_PHY_REG_PTP_TRIG 0x14
104 #define DP83640_PHY_REG_PTP_EVNT 0x15
105 #define DP83640_PHY_REG_PTP_TXCFG0 0x16
106 #define DP83640_PHY_REG_PTP_TXCFG1 0x17
107 #define DP83640_PHY_REG_PSF_CFG0 0x18
108 #define DP83640_PHY_REG_PTP_RXCFG0 0x19
109 #define DP83640_PHY_REG_PTP_RXCFG1 0x1A
110 #define DP83640_PHY_REG_PTP_RXCFG2 0x1B
111 #define DP83640_PHY_REG_PTP_RXCFG3 0x1C
112 #define DP83640_PHY_REG_PTP_RXCFG4 0x1D
113 #define DP83640_PHY_REG_PTP_TRDL 0x1E
114 #define DP83640_PHY_REG_PTP_TRDH 0x1F
115 
116 //Extended registers (page 6)
117 #define DP83640_PHY_REG_PTP_COC 0x14
118 #define DP83640_PHY_REG_PSF_CFG1 0x15
119 #define DP83640_PHY_REG_PSF_CFG2 0x16
120 #define DP83640_PHY_REG_PSF_CFG3 0x17
121 #define DP83640_PHY_REG_PSF_CFG4 0x18
122 #define DP83640_PHY_REG_PTP_SFDCFG 0x19
123 #define DP83640_PHY_REG_PTP_INTCTL 0x1A
124 #define DP83640_PHY_REG_PTP_CLKSRC 0x1B
125 #define DP83640_PHY_REG_PTP_ETR 0x1C
126 #define DP83640_PHY_REG_PTP_OFF 0x1D
127 #define DP83640_PHY_REG_PTP_GPIOMON 0x1E
128 #define DP83640_PHY_REG_PTP_RXHASH 0x1F
129 
130 //BMCR register
131 #define BMCR_RESET (1 << 15)
132 #define BMCR_LOOPBACK (1 << 14)
133 #define BMCR_SPEED_SEL (1 << 13)
134 #define BMCR_AN_EN (1 << 12)
135 #define BMCR_POWER_DOWN (1 << 11)
136 #define BMCR_ISOLATE (1 << 10)
137 #define BMCR_RESTART_AN (1 << 9)
138 #define BMCR_DUPLEX_MODE (1 << 8)
139 #define BMCR_COL_TEST (1 << 7)
140 #define BMCR_UNIDIRECTIONAL_EN (1 << 5)
141 
142 //BMSR register
143 #define BMSR_100BT4 (1 << 15)
144 #define BMSR_100BTX_FD (1 << 14)
145 #define BMSR_100BTX (1 << 13)
146 #define BMSR_10BT_FD (1 << 12)
147 #define BMSR_10BT (1 << 11)
148 #define BMSR_UNIDIRECTIONAL_ABLE (1 << 7)
149 #define BMSR_NO_PREAMBLE (1 << 6)
150 #define BMSR_AN_COMPLETE (1 << 5)
151 #define BMSR_REMOTE_FAULT (1 << 4)
152 #define BMSR_AN_ABLE (1 << 3)
153 #define BMSR_LINK_STATUS (1 << 2)
154 #define BMSR_JABBER_DETECT (1 << 1)
155 #define BMSR_EXTENDED_CAP (1 << 0)
156 
157 //ANAR register
158 #define ANAR_NP (1 << 15)
159 #define ANAR_RF (1 << 13)
160 #define ANAR_ASM_DIR (1 << 11)
161 #define ANAR_PAUSE (1 << 10)
162 #define ANAR_100BT4 (1 << 9)
163 #define ANAR_100BTX_FD (1 << 8)
164 #define ANAR_100BTX (1 << 7)
165 #define ANAR_10BT_FD (1 << 6)
166 #define ANAR_10BT (1 << 5)
167 #define ANAR_SELECTOR4 (1 << 4)
168 #define ANAR_SELECTOR3 (1 << 3)
169 #define ANAR_SELECTOR2 (1 << 2)
170 #define ANAR_SELECTOR1 (1 << 1)
171 #define ANAR_SELECTOR0 (1 << 0)
172 
173 //ANLPAR register
174 #define ANLPAR_NP (1 << 15)
175 #define ANLPAR_ACK (1 << 14)
176 #define ANLPAR_RF (1 << 13)
177 #define ANLPAR_ASM_DIR (1 << 11)
178 #define ANLPAR_PAUSE (1 << 10)
179 #define ANLPAR_100BT4 (1 << 9)
180 #define ANLPAR_100BTX_FD (1 << 8)
181 #define ANLPAR_100BTX (1 << 7)
182 #define ANLPAR_10BT_FD (1 << 6)
183 #define ANLPAR_10BT (1 << 5)
184 #define ANLPAR_SELECTOR4 (1 << 4)
185 #define ANLPAR_SELECTOR3 (1 << 3)
186 #define ANLPAR_SELECTOR2 (1 << 2)
187 #define ANLPAR_SELECTOR1 (1 << 1)
188 #define ANLPAR_SELECTOR0 (1 << 0)
189 
190 //ANER register
191 #define ANER_PDF (1 << 4)
192 #define ANER_LP_NP_ABLE (1 << 3)
193 #define ANER_NP_ABLE (1 << 2)
194 #define ANER_PAGE_RX (1 << 1)
195 #define ANER_LP_AN_ABLE (1 << 0)
196 
197 //ANNPTR register
198 #define ANNPTR_NP (1 << 15)
199 #define ANNPTR_MP (1 << 13)
200 #define ANNPTR_ACK2 (1 << 12)
201 #define ANNPTR_TOG_TX (1 << 11)
202 #define ANNPTR_CODE10 (1 << 10)
203 #define ANNPTR_CODE9 (1 << 9)
204 #define ANNPTR_CODE8 (1 << 8)
205 #define ANNPTR_CODE7 (1 << 7)
206 #define ANNPTR_CODE6 (1 << 6)
207 #define ANNPTR_CODE5 (1 << 5)
208 #define ANNPTR_CODE4 (1 << 4)
209 #define ANNPTR_CODE3 (1 << 3)
210 #define ANNPTR_CODE2 (1 << 2)
211 #define ANNPTR_CODE1 (1 << 1)
212 #define ANNPTR_CODE0 (1 << 0)
213 
214 //PHYSTS register
215 #define PHYSTS_MDIX_MODE (1 << 14)
216 #define PHYSTS_RX_ERROR_LATCH (1 << 13)
217 #define PHYSTS_POLARITY_STATUS (1 << 12)
218 #define PHYSTS_FALSE_CARRIER_SENSE (1 << 11)
219 #define PHYSTS_SIGNAL_DETECT (1 << 10)
220 #define PHYSTS_DESCRAMBLER_LOCK (1 << 9)
221 #define PHYSTS_PAGE_RECEIVED (1 << 8)
222 #define PHYSTS_MII_INTERRUPT (1 << 7)
223 #define PHYSTS_REMOTE_FAULT (1 << 6)
224 #define PHYSTS_JABBER_DETECT (1 << 5)
225 #define PHYSTS_AN_COMPLETE (1 << 4)
226 #define PHYSTS_LOOPBACK_STATUS (1 << 3)
227 #define PHYSTS_DUPLEX_STATUS (1 << 2)
228 #define PHYSTS_SPEED_STATUS (1 << 1)
229 #define PHYSTS_LINK_STATUS (1 << 0)
230 
231 //MICR register
232 #define MICR_TINT (1 << 2)
233 #define MICR_INTEN (1 << 1)
234 #define MICR_INT_OE (1 << 0)
235 
236 //MISR register
237 #define MISR_ED_INT (1 << 14)
238 #define MISR_LINK_INT (1 << 13)
239 #define MISR_SPD_INT (1 << 12)
240 #define MISR_DUP_INT (1 << 11)
241 #define MISR_ANC_INT (1 << 10)
242 #define MISR_FHF_INT (1 << 9)
243 #define MISR_RHF_INT (1 << 8)
244 #define MISR_LQ_INT_EN (1 << 7)
245 #define MISR_ED_INT_EN (1 << 6)
246 #define MISR_LINK_INT_EN (1 << 5)
247 #define MISR_SPD_INT_EN (1 << 4)
248 #define MISR_DUP_INT_EN (1 << 3)
249 #define MISR_ANC_INT_EN (1 << 2)
250 #define MISR_FHF_INT_EN (1 << 1)
251 #define MISR_RHF_INT_EN (1 << 0)
252 
253 //PAGESEL register
254 #define PAGESEL_PAGE_SEL2 (1 << 2)
255 #define PAGESEL_PAGE_SEL1 (1 << 1)
256 #define PAGESEL_PAGE_SEL0 (1 << 0)
257 
258 //FCSCR register
259 #define FCSCR_FCSCNT7 (1 << 7)
260 #define FCSCR_FCSCNT6 (1 << 6)
261 #define FCSCR_FCSCNT5 (1 << 5)
262 #define FCSCR_FCSCNT4 (1 << 4)
263 #define FCSCR_FCSCNT3 (1 << 3)
264 #define FCSCR_FCSCNT2 (1 << 2)
265 #define FCSCR_FCSCNT1 (1 << 1)
266 #define FCSCR_FCSCNT0 (1 << 0)
267 
268 //RECR register
269 #define RECR_RXERCNT7 (1 << 7)
270 #define RECR_RXERCNT6 (1 << 6)
271 #define RECR_RXERCNT5 (1 << 5)
272 #define RECR_RXERCNT4 (1 << 4)
273 #define RECR_RXERCNT3 (1 << 3)
274 #define RECR_RXERCNT2 (1 << 2)
275 #define RECR_RXERCNT1 (1 << 1)
276 #define RECR_RXERCNT0 (1 << 0)
277 
278 //PCSR register
279 #define PCSR_AUTO_CROSSOVER (1 << 15)
280 #define PCSR_FREE_CLK (1 << 11)
281 #define PCSR_TQ_EN (1 << 10)
282 #define PCSR_SD_FORCE_PMA (1 << 9)
283 #define PCSR_SD_OPTION (1 << 8)
284 #define PCSR_DESC_TIME (1 << 7)
285 #define PCSR_FX_EN (1 << 6)
286 #define PCSR_FORCE_100_OK (1 << 5)
287 #define PCSR_FEFI_EN (1 << 3)
288 #define PCSR_NRZI_BYPASS (1 << 2)
289 #define PCSR_SCRAM_BYPASS (1 << 1)
290 #define PCSR_DESCRAM_BYPASS (1 << 0)
291 
292 //RBR register
293 #define RBR_RMII_MASTER (1 << 14)
294 #define RBR_DIS_TX_OPT (1 << 13)
295 #define RBR_PMD_LOOP (1 << 8)
296 #define RBR_SCMII_RX (1 << 7)
297 #define RBR_SCMII_TX (1 << 6)
298 #define RBR_RMII_MODE (1 << 5)
299 #define RBR_RMII_REV1_0 (1 << 4)
300 #define RBR_RX_OVF_STS (1 << 3)
301 #define RBR_RX_UNF_STS (1 << 2)
302 #define RBR_ELAST_BUF1 (1 << 1)
303 #define RBR_ELAST_BUF0 (1 << 0)
304 
305 //LEDCR register
306 #define LEDCR_DIS_SPDLED (1 << 11)
307 #define LEDCR_DIS_LNKLED (1 << 10)
308 #define LEDCR_DIS_ACTLED (1 << 9)
309 #define LEDCR_LEDACT_RX (1 << 8)
310 #define LEDCR_BLINK_FREQ1 (1 << 7)
311 #define LEDCR_BLINK_FREQ0 (1 << 6)
312 #define LEDCR_DRV_SPDLED (1 << 5)
313 #define LEDCR_DRV_LNKLED (1 << 4)
314 #define LEDCR_DRV_ACTLED (1 << 3)
315 #define LEDCR_SPDLED (1 << 2)
316 #define LEDCR_LNKLED (1 << 1)
317 #define LEDCR_ACTLED (1 << 0)
318 
319 #define LEDCR_BLINK_FREQ_6HZ (0 << 6)
320 #define LEDCR_BLINK_FREQ_12HZ (1 << 6)
321 #define LEDCR_BLINK_FREQ_24HZ (2 << 6)
322 #define LEDCR_BLINK_FREQ_48HZ (3 << 6)
323 
324 //PHYCR register
325 #define PHYCR_MDIX_EN (1 << 15)
326 #define PHYCR_FORCE_MDIX (1 << 14)
327 #define PHYCR_PAUSE_RX (1 << 13)
328 #define PHYCR_PAUSE_TX (1 << 12)
329 #define PHYCR_BIST_FE (1 << 11)
330 #define PHYCR_PSR_15 (1 << 10)
331 #define PHYCR_BIST_STATUS (1 << 9)
332 #define PHYCR_BIST_START (1 << 8)
333 #define PHYCR_BP_STRETCH (1 << 7)
334 #define PHYCR_LED_CNFG1 (1 << 6)
335 #define PHYCR_LED_CNFG0 (1 << 5)
336 #define PHYCR_PHYADDR4 (1 << 4)
337 #define PHYCR_PHYADDR3 (1 << 3)
338 #define PHYCR_PHYADDR2 (1 << 2)
339 #define PHYCR_PHYADDR1 (1 << 1)
340 #define PHYCR_PHYADDR0 (1 << 0)
341 
342 //10BTSCR register
343 #define _10BTSCR_10BT_SERIAL (1 << 15)
344 #define _10BTSCR_SQUELCH2 (1 << 11)
345 #define _10BTSCR_SQUELCH1 (1 << 10)
346 #define _10BTSCR_SQUELCH0 (1 << 9)
347 #define _10BTSCR_LOOPBACK_10_DIS (1 << 8)
348 #define _10BTSCR_LP_DIS (1 << 7)
349 #define _10BTSCR_FORCE_LINK_10 (1 << 6)
350 #define _10BTSCR_POLARITY (1 << 4)
351 #define _10BTSCR_AUTOPOL_DIS (1 << 3)
352 #define _10BTSCR_10BT_SCALE_MSB (1 << 2)
353 #define _10BTSCR_HEARTBEAT_DIS (1 << 1)
354 #define _10BTSCR_JABBER_DIS (1 << 0)
355 
356 //CDCTRL1 register
357 #define CDCTRL1_BIST_ERROR_COUNT7 (1 << 15)
358 #define CDCTRL1_BIST_ERROR_COUNT6 (1 << 14)
359 #define CDCTRL1_BIST_ERROR_COUNT5 (1 << 13)
360 #define CDCTRL1_BIST_ERROR_COUNT4 (1 << 12)
361 #define CDCTRL1_BIST_ERROR_COUNT3 (1 << 11)
362 #define CDCTRL1_BIST_ERROR_COUNT2 (1 << 10)
363 #define CDCTRL1_BIST_ERROR_COUNT1 (1 << 9)
364 #define CDCTRL1_BIST_ERROR_COUNT0 (1 << 8)
365 #define CDCTRL1_MII_CLOCK_EN (1 << 6)
366 #define CDCTRL1_BIST_CONT (1 << 5)
367 #define CDCTRL1_CDPATTEN_10 (1 << 4)
368 #define CDCTRL1_MDIO_PULL_EN (1 << 3)
369 #define CDCTRL1_PATT_GAP_10M (1 << 2)
370 #define CDCTRL1_CDPATTSEL1 (1 << 1)
371 #define CDCTRL1_CDPATTSEL0 (1 << 0)
372 
373 //PHYCR2 register
374 #define PHYCR2_SYNC_ENET_EN (1 << 13)
375 #define PHYCR2_CLK_OUT RXCLK (1 << 12)
376 #define PHYCR2_BC_WRITE (1 << 11)
377 #define PHYCR2_PHYTER_COMP (1 << 10)
378 #define PHYCR2_SOFT_RESET (1 << 9)
379 #define PHYCR2_CLK_OUT_DIS (1 << 1)
380 
381 //EDCR register
382 #define EDCR_ED_EN (1 << 15)
383 #define EDCR_ED_AUTO_UP (1 << 14)
384 #define EDCR_ED_AUTO_DOWN (1 << 13)
385 #define EDCR_ED_MAN (1 << 12)
386 #define EDCR_ED_BURST_DIS (1 << 11)
387 #define EDCR_ED_PWR_STATE (1 << 10)
388 #define EDCR_ED_ERR_MET (1 << 9)
389 #define EDCR_ED_DATA_MET (1 << 8)
390 #define EDCR_ED_ERR_COUNT3 (1 << 7)
391 #define EDCR_ED_ERR_COUNT2 (1 << 6)
392 #define EDCR_ED_ERR_COUNT1 (1 << 5)
393 #define EDCR_ED_ERR_COUNT0 (1 << 4)
394 #define EDCR_ED_DATA_COUNT3 (1 << 3)
395 #define EDCR_ED_DATA_COUNT2 (1 << 2)
396 #define EDCR_ED_DATA_COUNT1 (1 << 1)
397 #define EDCR_ED_DATA_COUNT0 (1 << 0)
398 
399 //PCFCR register
400 #define PCFCR_PCF_STS_ERR (1 << 15)
401 #define PCFCR_PCF_STS_OK (1 << 14)
402 #define PCFCR_PCF_DA_SEL (1 << 8)
403 #define PCFCR_PCF_INT_CTL1 (1 << 7)
404 #define PCFCR_PCF_INT_CTL0 (1 << 6)
405 #define PCFCR_PCF_BC_DIS (1 << 5)
406 #define PCFCR_PCF_BUF3 (1 << 4)
407 #define PCFCR_PCF_BUF2 (1 << 3)
408 #define PCFCR_PCF_BUF1 (1 << 2)
409 #define PCFCR_PCF_BUF0 (1 << 1)
410 #define PCFCR_PCF_EN (1 << 0)
411 
412 //SD_CNFG register
413 #define SD_CNFG_SD_TIME (1 << 8)
414 
415 //LEN100_DET register
416 #define LEN100_DET_CABLE_LEN7 (1 << 7)
417 #define LEN100_DET_CABLE_LEN6 (1 << 6)
418 #define LEN100_DET_CABLE_LEN5 (1 << 5)
419 #define LEN100_DET_CABLE_LEN4 (1 << 4)
420 #define LEN100_DET_CABLE_LEN3 (1 << 3)
421 #define LEN100_DET_CABLE_LEN2 (1 << 2)
422 #define LEN100_DET_CABLE_LEN1 (1 << 1)
423 #define LEN100_DET_CABLE_LEN0 (1 << 0)
424 
425 //FREQ100 register
426 #define FREQ100_SAMPLE_FREQ (1 << 15)
427 #define FREQ100_SEL_FC (1 << 8)
428 #define FREQ100_FREQ_OFFSET7 (1 << 7)
429 #define FREQ100_FREQ_OFFSET6 (1 << 6)
430 #define FREQ100_FREQ_OFFSET5 (1 << 5)
431 #define FREQ100_FREQ_OFFSET4 (1 << 4)
432 #define FREQ100_FREQ_OFFSET3 (1 << 3)
433 #define FREQ100_FREQ_OFFSET2 (1 << 2)
434 #define FREQ100_FREQ_OFFSET1 (1 << 1)
435 #define FREQ100_FREQ_OFFSET0 (1 << 0)
436 
437 //TDR_CTRL register
438 #define TDR_CTRL_TDR_ENABLE (1 << 15)
439 #define TDR_CTRL_TDR_100MB (1 << 14)
440 #define TDR_CTRL_TX_CHANNEL (1 << 13)
441 #define TDR_CTRL_RX_CHANNEL (1 << 12)
442 #define TDR_CTRL_SEND_TDR (1 << 11)
443 #define TDR_CTRL_TDR_WIDTH2 (1 << 10)
444 #define TDR_CTRL_TDR_WIDTH1 (1 << 9)
445 #define TDR_CTRL_TDR_WIDTH0 (1 << 8)
446 #define TDR_CTRL_TDR_MIN_MODE (1 << 7)
447 #define TDR_CTRL_RX_THRESHOLD5 (1 << 5)
448 #define TDR_CTRL_RX_THRESHOLD4 (1 << 4)
449 #define TDR_CTRL_RX_THRESHOLD3 (1 << 3)
450 #define TDR_CTRL_RX_THRESHOLD2 (1 << 2)
451 #define TDR_CTRL_RX_THRESHOLD1 (1 << 1)
452 #define TDR_CTRL_RX_THRESHOLD0 (1 << 0)
453 
454 //TDR_WIN register
455 #define TDR_WIN_TDR_START7 (1 << 15)
456 #define TDR_WIN_TDR_START6 (1 << 14)
457 #define TDR_WIN_TDR_START5 (1 << 13)
458 #define TDR_WIN_TDR_START4 (1 << 12)
459 #define TDR_WIN_TDR_START3 (1 << 11)
460 #define TDR_WIN_TDR_START2 (1 << 10)
461 #define TDR_WIN_TDR_START1 (1 << 9)
462 #define TDR_WIN_TDR_START0 (1 << 8)
463 #define TDR_WIN_TDR_STOP7 (1 << 7)
464 #define TDR_WIN_TDR_STOP6 (1 << 6)
465 #define TDR_WIN_TDR_STOP5 (1 << 5)
466 #define TDR_WIN_TDR_STOP4 (1 << 4)
467 #define TDR_WIN_TDR_STOP3 (1 << 3)
468 #define TDR_WIN_TDR_STOP2 (1 << 2)
469 #define TDR_WIN_TDR_STOP1 (1 << 1)
470 #define TDR_WIN_TDR_STOP0 (1 << 0)
471 
472 //TDR_PEAK register
473 #define TDR_PEAK_TDR_PEAK5 (1 << 13)
474 #define TDR_PEAK_TDR_PEAK4 (1 << 12)
475 #define TDR_PEAK_TDR_PEAK3 (1 << 11)
476 #define TDR_PEAK_TDR_PEAK2 (1 << 10)
477 #define TDR_PEAK_TDR_PEAK1 (1 << 9)
478 #define TDR_PEAK_TDR_PEAK0 (1 << 8)
479 #define TDR_PEAK_TDR_PEAK_TIME7 (1 << 7)
480 #define TDR_PEAK_TDR_PEAK_TIME6 (1 << 6)
481 #define TDR_PEAK_TDR_PEAK_TIME5 (1 << 5)
482 #define TDR_PEAK_TDR_PEAK_TIME4 (1 << 4)
483 #define TDR_PEAK_TDR_PEAK_TIME3 (1 << 3)
484 #define TDR_PEAK_TDR_PEAK_TIME2 (1 << 2)
485 #define TDR_PEAK_TDR_PEAK_TIME1 (1 << 1)
486 #define TDR_PEAK_TDR_PEAK_TIME0 (1 << 0)
487 
488 //TDR_THR register
489 #define TDR_THR_TDR_THR_MET (1 << 8)
490 #define TDR_THR_TDR_THR_TIME7 (1 << 7)
491 #define TDR_THR_TDR_THR_TIME6 (1 << 6)
492 #define TDR_THR_TDR_THR_TIME5 (1 << 5)
493 #define TDR_THR_TDR_THR_TIME4 (1 << 4)
494 #define TDR_THR_TDR_THR_TIME3 (1 << 3)
495 #define TDR_THR_TDR_THR_TIME2 (1 << 2)
496 #define TDR_THR_TDR_THR_TIME1 (1 << 1)
497 #define TDR_THR_TDR_THR_TIME0 (1 << 0)
498 
499 //VAR_CTRL register
500 #define VAR_CTRL_VAR_RDY (1 << 15)
501 #define VAR_CTRL_VAR_FREEZE (1 << 3)
502 #define VAR_CTRL_VAR_TIMER1 (1 << 2)
503 #define VAR_CTRL_VAR_TIMER0 (1 << 1)
504 #define VAR_CTRL_VAR_ENABLE (1 << 0)
505 
506 //LQMR register
507 #define LQMR_LQM_ENABLE (1 << 15)
508 #define LQMR_RESTART_ON_FC (1 << 14)
509 #define LQMR_RESTART_ON_FREQ (1 << 13)
510 #define LQMR_RESTART_ON_DBLW (1 << 12)
511 #define LQMR_RESTART_ON_DAGC (1 << 11)
512 #define LQMR_RESTART_ON_C1 (1 << 10)
513 #define LQMR_FC_HI_WARN (1 << 9)
514 #define LQMR_FC_LO_WARN (1 << 8)
515 #define LQMR_FREQ_HI_WARN (1 << 7)
516 #define LQMR_FREQ_LO_WARN (1 << 6)
517 #define LQMR_DBLW_HI_WARN (1 << 5)
518 #define LQMR_DBLW_LO_WARN (1 << 4)
519 #define LQMR_DAGC_HI_WARN (1 << 3)
520 #define LQMR_DAGC_LO_WARN (1 << 2)
521 #define LQMR_C1_HI_WARN (1 << 1)
522 #define LQMR_C1_LO_WARN (1 << 0)
523 
524 //LQDR register
525 #define LQDR_SAMPLE_PARAM (1 << 13)
526 #define LQDR_WRITE_LQ_THR (1 << 12)
527 #define LQDR_LQ_PARAM_SEL2 (1 << 11)
528 #define LQDR_LQ_PARAM_SEL1 (1 << 10)
529 #define LQDR_LQ_PARAM_SEL0 (1 << 9)
530 #define LQDR_LQ_THR_SEL (1 << 8)
531 #define LQDR_LQ_THR_DATA7 (1 << 7)
532 #define LQDR_LQ_THR_DATA6 (1 << 6)
533 #define LQDR_LQ_THR_DATA5 (1 << 5)
534 #define LQDR_LQ_THR_DATA4 (1 << 4)
535 #define LQDR_LQ_THR_DATA3 (1 << 3)
536 #define LQDR_LQ_THR_DATA2 (1 << 2)
537 #define LQDR_LQ_THR_DATA1 (1 << 1)
538 #define LQDR_LQ_THR_DATA0 (1 << 0)
539 
540 //LQMR2 register
541 #define LQMR2_RESTART_ON_VAR (1 << 10)
542 #define LQMR2_VAR_HI_WARN (1 << 1)
543 
544 //PSF_CFG0 register
545 #define PSF_CFG0_MAC_SRC_ADD1 (1 << 12)
546 #define PSF_CFG0_MAC_SRC_ADD0 (1 << 11)
547 #define PSF_CFG0_MIN_PRE2 (1 << 10)
548 #define PSF_CFG0_MIN_PRE1 (1 << 9)
549 #define PSF_CFG0_MIN_PRE0 (1 << 8)
550 #define PSF_CFG0_PSF_ENDIAN (1 << 7)
551 #define PSF_CFG0_PSF_IPV4 (1 << 6)
552 #define PSF_CFG0_PSF_PCF_RD (1 << 5)
553 #define PSF_CFG0_PSF_ERR_EN (1 << 4)
554 #define PSF_CFG0_PSF_TXTS_EN (1 << 3)
555 #define PSF_CFG0_PSF_RXTS_EN (1 << 2)
556 #define PSF_CFG0_PSF_TRIG_EN (1 << 1)
557 #define PSF_CFG0_PSF_EVNT_EN (1 << 0)
558 
559 //PTP_COC register
560 #define PTP_COC_PTP_CLKOUT_EN (1 << 15)
561 #define PTP_COC_PTP_CLKOUT_SEL (1 << 14)
562 #define PTP_COC_PTP_CLKOUT_SPEEDSEL (1 << 13)
563 #define PTP_COC_PTP_CLKDIV7 (1 << 7)
564 #define PTP_COC_PTP_CLKDIV6 (1 << 6)
565 #define PTP_COC_PTP_CLKDIV5 (1 << 5)
566 #define PTP_COC_PTP_CLKDIV4 (1 << 4)
567 #define PTP_COC_PTP_CLKDIV3 (1 << 3)
568 #define PTP_COC_PTP_CLKDIV2 (1 << 2)
569 #define PTP_COC_PTP_CLKDIV1 (1 << 1)
570 #define PTP_COC_PTP_CLKDIV0 (1 << 0)
571 
572 //C++ guard
573 #ifdef __cplusplus
574  extern "C" {
575 #endif
576 
577 //DP83640 Ethernet PHY driver
578 extern const PhyDriver dp83640PhyDriver;
579 
580 //DP83640 related functions
581 error_t dp83640Init(NetInterface *interface);
582 
583 void dp83640Tick(NetInterface *interface);
584 
585 void dp83640EnableIrq(NetInterface *interface);
586 void dp83640DisableIrq(NetInterface *interface);
587 
588 void dp83640EventHandler(NetInterface *interface);
589 
590 void dp83640WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
591 uint16_t dp83640ReadPhyReg(NetInterface *interface, uint8_t address);
592 
593 void dp83640DumpPhyReg(NetInterface *interface);
594 
595 //C++ guard
596 #ifdef __cplusplus
597  }
598 #endif
599 
600 #endif
void dp83640EnableIrq(NetInterface *interface)
Enable interrupts.
PHY driver.
Definition: nic.h:196
void dp83640DisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t dp83640ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
error_t dp83640Init(NetInterface *interface)
DP83640 PHY transceiver initialization.
void dp83640Tick(NetInterface *interface)
DP83640 timer handler.
void dp83640EventHandler(NetInterface *interface)
DP83640 event handler.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void dp83640WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
Network interface controller abstraction layer.
void dp83640DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
const PhyDriver dp83640PhyDriver
DP83640 Ethernet PHY driver.