dp83640_driver.h
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1 /**
2  * @file dp83640_driver.h
3  * @brief DP83640 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _DP83640_DRIVER_H
32 #define _DP83640_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //PHY address
38 #ifndef DP83640_PHY_ADDR
39  #define DP83640_PHY_ADDR 1
40 #elif (DP83640_PHY_ADDR < 0 || DP83640_PHY_ADDR > 31)
41  #error DP83640_PHY_ADDR parameter is not valid
42 #endif
43 
44 //DP83640 PHY registers (page 0)
45 #define DP83640_BMCR 0x00
46 #define DP83640_BMSR 0x01
47 #define DP83640_PHYID1 0x02
48 #define DP83640_PHYID2 0x03
49 #define DP83640_ANAR 0x04
50 #define DP83640_ANLPAR 0x05
51 #define DP83640_ANER 0x06
52 #define DP83640_ANNPR 0x07
53 #define DP83640_PHYSTS 0x10
54 #define DP83640_MICR 0x11
55 #define DP83640_MISR 0x12
56 #define DP83640_PAGSR 0x13
57 #define DP83640_FCSCR 0x14
58 #define DP83640_RECR 0x15
59 #define DP83640_PCSR 0x16
60 #define DP83640_RBR 0x17
61 #define DP83640_LEDCR 0x18
62 #define DP83640_PHYCR 0x19
63 #define DP83640_10BTSCR 0x1A
64 #define DP83640_CDCTRL1 0x1B
65 #define DP83640_PHYCR2 0x1C
66 #define DP83640_EDCR 0x1D
67 #define DP83640_PCFCR 0x1E
68 
69 //DP83640 PHY registers (page 1)
70 #define DP83640_SD_CNFG 0x1E
71 
72 //DP83640 PHY registers (page 2)
73 #define DP83640_LEN100_DET 0x14
74 #define DP83640_FREQ100 0x15
75 #define DP83640_TDR_CTRL 0x16
76 #define DP83640_TDR_WIN 0x17
77 #define DP83640_TDR_PEAK 0x18
78 #define DP83640_TDR_THR 0x19
79 #define DP83640_VAR_CTRL 0x1A
80 #define DP83640_VAR_DAT 0x1B
81 #define DP83640_LQMR 0x1D
82 #define DP83640_LQDR 0x1E
83 #define DP83640_LQMR2 0x1F
84 
85 //DP83640 PHY registers (page 4)
86 #define DP83640_PTP_CTL 0x14
87 #define DP83640_PTP_TDR 0x15
88 #define DP83640_PTP_STS 0x16
89 #define DP83640_PTP_TSTS 0x17
90 #define DP83640_PTP_RATEL 0x18
91 #define DP83640_PTP_RATEH 0x19
92 #define DP83640_PTP_RDCKSUM 0x1A
93 #define DP83640_PTP_WRCKSUM 0x1B
94 #define DP83640_PTP_TXTS 0x1C
95 #define DP83640_PTP_RXTS 0x1D
96 #define DP83640_PTP_ESTS 0x1E
97 #define DP83640_PTP_EDATA 0x1F
98 
99 //DP83640 PHY registers (page 5)
100 #define DP83640_PTP_TRIG 0x14
101 #define DP83640_PTP_EVNT 0x15
102 #define DP83640_PTP_TXCFG0 0x16
103 #define DP83640_PTP_TXCFG1 0x17
104 #define DP83640_PSF_CFG0 0x18
105 #define DP83640_PTP_RXCFG0 0x19
106 #define DP83640_PTP_RXCFG1 0x1A
107 #define DP83640_PTP_RXCFG2 0x1B
108 #define DP83640_PTP_RXCFG3 0x1C
109 #define DP83640_PTP_RXCFG4 0x1D
110 #define DP83640_PTP_TRDL 0x1E
111 #define DP83640_PTP_TRDH 0x1F
112 
113 //DP83640 PHY registers (page 6)
114 #define DP83640_PTP_COC 0x14
115 #define DP83640_PSF_CFG1 0x15
116 #define DP83640_PSF_CFG2 0x16
117 #define DP83640_PSF_CFG3 0x17
118 #define DP83640_PSF_CFG4 0x18
119 #define DP83640_PTP_SFDCFG 0x19
120 #define DP83640_PTP_INTCTL 0x1A
121 #define DP83640_PTP_CLKSRC 0x1B
122 #define DP83640_PTP_ETR 0x1C
123 #define DP83640_PTP_OFF 0x1D
124 #define DP83640_PTP_GPIOMON 0x1E
125 #define DP83640_PTP_RXHASH 0x1F
126 
127 //Basic Mode Control register
128 #define DP83640_BMCR_RESET 0x8000
129 #define DP83640_BMCR_LOOPBACK 0x4000
130 #define DP83640_BMCR_SPEED_SEL 0x2000
131 #define DP83640_BMCR_AN_EN 0x1000
132 #define DP83640_BMCR_POWER_DOWN 0x0800
133 #define DP83640_BMCR_ISOLATE 0x0400
134 #define DP83640_BMCR_RESTART_AN 0x0200
135 #define DP83640_BMCR_DUPLEX_MODE 0x0100
136 #define DP83640_BMCR_COL_TEST 0x0080
137 #define DP83640_BMCR_UNIDIRECTIONAL_EN 0x0020
138 
139 //Basic Mode Status register
140 #define DP83640_BMSR_100BT4 0x8000
141 #define DP83640_BMSR_100BTX_FD 0x4000
142 #define DP83640_BMSR_100BTX_HD 0x2000
143 #define DP83640_BMSR_10BT_FD 0x1000
144 #define DP83640_BMSR_10BT_HD 0x0800
145 #define DP83640_BMSR_UNIDIRECTIONAL_ABLE 0x0080
146 #define DP83640_BMSR_MF_PREAMBLE_SUPPR 0x0040
147 #define DP83640_BMSR_AN_COMPLETE 0x0020
148 #define DP83640_BMSR_REMOTE_FAULT 0x0010
149 #define DP83640_BMSR_AN_CAPABLE 0x0008
150 #define DP83640_BMSR_LINK_STATUS 0x0004
151 #define DP83640_BMSR_JABBER_DETECT 0x0002
152 #define DP83640_BMSR_EXTENDED_CAPABLE 0x0001
153 
154 //PHY Identifier 1 register
155 #define DP83640_PHYID1_OUI_MSB 0xFFFF
156 #define DP83640_PHYID1_OUI_MSB_DEFAULT 0x2000
157 
158 //PHY Identifier 2 register
159 #define DP83640_PHYID2_OUI_LSB 0xFC00
160 #define DP83640_PHYID2_OUI_LSB_DEFAULT 0x5C00
161 #define DP83640_PHYID2_VNDR_MDL 0x03F0
162 #define DP83640_PHYID2_VNDR_MDL_DEFAULT 0x00E0
163 #define DP83640_PHYID2_MDL_REV 0x000F
164 
165 //Auto-Negotiation Advertisement register
166 #define DP83640_ANAR_NEXT_PAGE 0x8000
167 #define DP83640_ANAR_REMOTE_FAULT 0x2000
168 #define DP83640_ANAR_ASM_DIR 0x0800
169 #define DP83640_ANAR_PAUSE 0x0400
170 #define DP83640_ANAR_100BT4 0x0200
171 #define DP83640_ANAR_100BTX_FD 0x0100
172 #define DP83640_ANAR_100BTX_HD 0x0080
173 #define DP83640_ANAR_10BT_FD 0x0040
174 #define DP83640_ANAR_10BT_HD 0x0020
175 #define DP83640_ANAR_SELECTOR 0x001F
176 #define DP83640_ANAR_SELECTOR_DEFAULT 0x0001
177 
178 //Auto-Negotiation Link Partner Ability register
179 #define DP83640_ANLPAR_NEXT_PAGE 0x8000
180 #define DP83640_ANLPAR_ACK 0x4000
181 #define DP83640_ANLPAR_REMOTE_FAULT 0x2000
182 #define DP83640_ANLPAR_ASM_DIR 0x0800
183 #define DP83640_ANLPAR_PAUSE 0x0400
184 #define DP83640_ANLPAR_100BT4 0x0200
185 #define DP83640_ANLPAR_100BTX_FD 0x0100
186 #define DP83640_ANLPAR_100BTX_HD 0x0080
187 #define DP83640_ANLPAR_10BT_FD 0x0040
188 #define DP83640_ANLPAR_10BT_HD 0x0020
189 #define DP83640_ANLPAR_SELECTOR 0x001F
190 #define DP83640_ANLPAR_SELECTOR_DEFAULT 0x0001
191 
192 //Auto-Negotiation Expansion register
193 #define DP83640_ANER_PAR_DETECT_FAULT 0x0010
194 #define DP83640_ANER_LP_NP_ABLE 0x0008
195 #define DP83640_ANER_NP_ABLE 0x0004
196 #define DP83640_ANER_PAGE_RX 0x0002
197 #define DP83640_ANER_LP_AN_ABLE 0x0001
198 
199 //Auto-Negotiation Next Page TX register
200 #define DP83640_ANNPR_NEXT_PAGE 0x8000
201 #define DP83640_ANNPR_MSG_PAGE 0x2000
202 #define DP83640_ANNPR_ACK2 0x1000
203 #define DP83640_ANNPR_TOGGLE 0x0800
204 #define DP83640_ANNPR_CODE 0x07FF
205 
206 //PHY Status register
207 #define DP83640_PHYSTS_MDIX_MODE 0x4000
208 #define DP83640_PHYSTS_RECEIVE_ERROR_LATCH 0x2000
209 #define DP83640_PHYSTS_POLARITY_STATUS 0x1000
210 #define DP83640_PHYSTS_FCS_LATCH 0x0800
211 #define DP83640_PHYSTS_SIGNAL_DETECT 0x0400
212 #define DP83640_PHYSTS_DESCRAMBLER_LOCK 0x0200
213 #define DP83640_PHYSTS_PAGE_RECEIVED 0x0100
214 #define DP83640_PHYSTS_MII_INTERRUPT 0x0080
215 #define DP83640_PHYSTS_REMOTE_FAULT 0x0040
216 #define DP83640_PHYSTS_JABBER_DETECT 0x0020
217 #define DP83640_PHYSTS_AN_COMPLETE 0x0010
218 #define DP83640_PHYSTS_LOOPBACK_STATUS 0x0008
219 #define DP83640_PHYSTS_DUPLEX_STATUS 0x0004
220 #define DP83640_PHYSTS_SPEED_STATUS 0x0002
221 #define DP83640_PHYSTS_LINK_STATUS 0x0001
222 
223 //MII Interrupt Control register
224 #define DP83640_MICR_PTP_INT_SEL 0x0008
225 #define DP83640_MICR_TINT 0x0004
226 #define DP83640_MICR_INTEN 0x0002
227 #define DP83640_MICR_INT_OE 0x0001
228 
229 //MII Interrupt Status register
230 #define DP83640_MISR_LQ_INT 0x8000
231 #define DP83640_MISR_ED_INT 0x4000
232 #define DP83640_MISR_LINK_INT 0x2000
233 #define DP83640_MISR_SPD_INT 0x1000
234 #define DP83640_MISR_DUP_INT 0x0800
235 #define DP83640_MISR_ANC_INT 0x0400
236 #define DP83640_MISR_FHF_INT 0x0200
237 #define DP83640_MISR_RHF_INT 0x0100
238 #define DP83640_MISR_LQ_INT_EN 0x0080
239 #define DP83640_MISR_ED_INT_EN 0x0040
240 #define DP83640_MISR_LINK_INT_EN 0x0020
241 #define DP83640_MISR_SPD_INT_EN 0x0010
242 #define DP83640_MISR_DUP_INT_EN 0x0008
243 #define DP83640_MISR_ANC_INT_EN 0x0004
244 #define DP83640_MISR_FHF_INT_EN 0x0002
245 #define DP83640_MISR_RHF_INT_EN 0x0001
246 
247 //Page Select register
248 #define DP83640_PAGSR_PAGE_SEL 0x0007
249 
250 //False Carrier Sense Counter register
251 #define DP83640_FCSCR_FCSCNT 0x00FF
252 
253 //Receive Error Counter register
254 #define DP83640_RECR_RXERCNT 0x00FF
255 
256 //PCS Configuration and Status register
257 #define DP83640_PCSR_FREE_CLK 0x0800
258 #define DP83640_PCSR_TQ_EN 0x0400
259 #define DP83640_PCSR_SD_FORCE_PMA 0x0200
260 #define DP83640_PCSR_SD_OPTION 0x0100
261 #define DP83640_PCSR_DESC_TIME 0x0080
262 #define DP83640_PCSR_FX_EN 0x0040
263 #define DP83640_PCSR_FORCE_100_OK 0x0020
264 #define DP83640_PCSR_FEFI_EN 0x0008
265 #define DP83640_PCSR_NRZI_BYPASS 0x0004
266 #define DP83640_PCSR_SCRAM_BYPASS 0x0002
267 #define DP83640_PCSR_DESCRAM_BYPASS 0x0001
268 
269 //RMII and Bypass register
270 #define DP83640_RBR_RMII_MASTER 0x4000
271 #define DP83640_RBR_DIS_TX_OPT 0x2000
272 #define DP83640_RBR_PMD_LOOP 0x0100
273 #define DP83640_RBR_SCMII_RX 0x0080
274 #define DP83640_RBR_SCMII_TX 0x0040
275 #define DP83640_RBR_RMII_MODE 0x0020
276 #define DP83640_RBR_RMII_REV1_0 0x0010
277 #define DP83640_RBR_RX_OVF_STS 0x0008
278 #define DP83640_RBR_RX_UNF_STS 0x0004
279 #define DP83640_RBR_ELAST_BUF 0x0003
280 
281 //LED Direct Control register
282 #define DP83640_LEDCR_DIS_SPDLED 0x0800
283 #define DP83640_LEDCR_DIS_LNKLED 0x0400
284 #define DP83640_LEDCR_DIS_ACTLED 0x0200
285 #define DP83640_LEDCR_LEDACT_RX 0x0100
286 #define DP83640_LEDCR_BLINK_FREQ 0x00C0
287 #define DP83640_LEDCR_BLINK_FREQ_6HZ 0x0000
288 #define DP83640_LEDCR_BLINK_FREQ_12HZ 0x0040
289 #define DP83640_LEDCR_BLINK_FREQ_24HZ 0x0080
290 #define DP83640_LEDCR_BLINK_FREQ_48HZ 0x00C0
291 #define DP83640_LEDCR_DRV_SPDLED 0x0020
292 #define DP83640_LEDCR_DRV_LNKLED 0x0010
293 #define DP83640_LEDCR_DRV_ACTLED 0x0008
294 #define DP83640_LEDCR_SPDLED 0x0004
295 #define DP83640_LEDCR_LNKLED 0x0002
296 #define DP83640_LEDCR_ACTLED 0x0001
297 
298 //PHY Control register
299 #define DP83640_PHYCR_MDIX_EN 0x8000
300 #define DP83640_PHYCR_FORCE_MDIX 0x4000
301 #define DP83640_PHYCR_PAUSE_RX 0x2000
302 #define DP83640_PHYCR_PAUSE_TX 0x1000
303 #define DP83640_PHYCR_BIST_FE 0x0800
304 #define DP83640_PHYCR_PSR_15 0x0400
305 #define DP83640_PHYCR_BIST_STATUS 0x0200
306 #define DP83640_PHYCR_BIST_START 0x0100
307 #define DP83640_PHYCR_BP_STRETCH 0x0080
308 #define DP83640_PHYCR_LED_CNFG 0x0060
309 #define DP83640_PHYCR_PHYADDR 0x001F
310 
311 //10Base-T Status/Control register
312 #define DP83640_10BTSCR_SQUELCH 0x0E00
313 #define DP83640_10BTSCR_LOOPBACK_10_DIS 0x0100
314 #define DP83640_10BTSCR_LP_DIS 0x0080
315 #define DP83640_10BTSCR_FORCE_LINK_10 0x0040
316 #define DP83640_10BTSCR_FORCE_POL_COR 0x0020
317 #define DP83640_10BTSCR_POLARITY 0x0010
318 #define DP83640_10BTSCR_AUTOPOL_DIS 0x0008
319 #define DP83640_10BTSCR_10BT_SCALE_MSB 0x0004
320 #define DP83640_10BTSCR_HEARTBEAT_DIS 0x0002
321 #define DP83640_10BTSCR_JABBER_DIS 0x0001
322 
323 //CD Test Control and BIST Extensions register
324 #define DP83640_CDCTRL1_BIST_ERROR_COUNT 0xFF00
325 #define DP83640_CDCTRL1_MII_CLOCK_EN 0x0040
326 #define DP83640_CDCTRL1_BIST_CONT 0x0020
327 #define DP83640_CDCTRL1_CDPATTEN_10 0x0010
328 #define DP83640_CDCTRL1_MDIO_PULL_EN 0x0008
329 #define DP83640_CDCTRL1_PATT_GAP_10M 0x0004
330 #define DP83640_CDCTRL1_CDPATTSEL 0x0003
331 
332 //PHY Control 2 register
333 #define DP83640_PHYCR2_SYNC_ENET_EN 0x2000
334 #define DP83640_PHYCR2_CLK_OUT_RXCLK 0x1000
335 #define DP83640_PHYCR2_BC_WRITE 0x0800
336 #define DP83640_PHYCR2_PHYTER_COMP 0x0400
337 #define DP83640_PHYCR2_SOFT_RESET 0x0200
338 #define DP83640_PHYCR2_CLK_OUT_DIS 0x0002
339 
340 //Energy Detect Control register
341 #define DP83640_EDCR_ED_EN 0x8000
342 #define DP83640_EDCR_ED_AUTO_UP 0x4000
343 #define DP83640_EDCR_ED_AUTO_DOWN 0x2000
344 #define DP83640_EDCR_ED_MAN 0x1000
345 #define DP83640_EDCR_ED_BURST_DIS 0x0800
346 #define DP83640_EDCR_ED_PWR_STATE 0x0400
347 #define DP83640_EDCR_ED_ERR_MET 0x0200
348 #define DP83640_EDCR_ED_DATA_MET 0x0100
349 #define DP83640_EDCR_ED_ERR_COUNT 0x00F0
350 #define DP83640_EDCR_ED_DATA_COUNT 0x000F
351 
352 //PHY Control Frames Configuration register
353 #define DP83640_PCFCR_PCF_STS_ERR 0x8000
354 #define DP83640_PCFCR_PCF_STS_OK 0x4000
355 #define DP83640_PCFCR_PCF_DA_SEL 0x0100
356 #define DP83640_PCFCR_PCF_INT_CTL 0x00C0
357 #define DP83640_PCFCR_PCF_BC_DIS 0x0020
358 #define DP83640_PCFCR_PCF_BUF 0x001E
359 #define DP83640_PCFCR_PCF_EN 0x0001
360 
361 //Signal Detect Configuration register
362 #define DP83640_SD_CNFG_SD_TIME 0x0100
363 
364 //100 Mb Length Detect register
365 #define DP83640_LEN100_DET_CABLE_LEN 0x00FF
366 
367 //100 Mb Frequency Offset Indication register
368 #define DP83640_FREQ100_SAMPLE_FREQ 0x8000
369 #define DP83640_FREQ100_SEL_FC 0x0100
370 #define DP83640_FREQ100_FREQ_OFFSET 0x00FF
371 
372 //TDR Control register
373 #define DP83640_TDR_CTRL_TDR_ENABLE 0x8000
374 #define DP83640_TDR_CTRL_TDR_100MB 0x4000
375 #define DP83640_TDR_CTRL_TX_CHANNEL 0x2000
376 #define DP83640_TDR_CTRL_RX_CHANNEL 0x1000
377 #define DP83640_TDR_CTRL_SEND_TDR 0x0800
378 #define DP83640_TDR_CTRL_TDR_WIDTH 0x0700
379 #define DP83640_TDR_CTRL_TDR_MIN_MODE 0x0080
380 #define DP83640_TDR_CTRL_RX_THRESHOLD 0x003F
381 
382 //TDR Window register
383 #define DP83640_TDR_WIN_TDR_START 0xFF00
384 #define DP83640_TDR_WIN_TDR_STOP 0x00FF
385 
386 //TDR Peak register
387 #define DP83640_TDR_PEAK_TDR_PEAK 0x3F00
388 #define DP83640_TDR_PEAK_TDR_PEAK_TIME 0x00FF
389 
390 //TDR Threshold register
391 #define DP83640_TDR_THR_TDR_THR_MET 0x0100
392 #define DP83640_TDR_THR_TDR_THR_TIME 0x00FF
393 
394 //Variance Control register
395 #define DP83640_VAR_CTRL_VAR_RDY 0x8000
396 #define DP83640_VAR_CTRL_VAR_FREEZE 0x0008
397 #define DP83640_VAR_CTRL_VAR_TIMER 0x0006
398 #define DP83640_VAR_CTRL_VAR_ENABLE 0x0001
399 
400 //Link Quality Monitor register
401 #define DP83640_LQMR_LQM_ENABLE 0x8000
402 #define DP83640_LQMR_RESTART_ON_FC 0x4000
403 #define DP83640_LQMR_RESTART_ON_FREQ 0x2000
404 #define DP83640_LQMR_RESTART_ON_DBLW 0x1000
405 #define DP83640_LQMR_RESTART_ON_DAGC 0x0800
406 #define DP83640_LQMR_RESTART_ON_C1 0x0400
407 #define DP83640_LQMR_FC_HI_WARN 0x0200
408 #define DP83640_LQMR_FC_LO_WARN 0x0100
409 #define DP83640_LQMR_FREQ_HI_WARN 0x0080
410 #define DP83640_LQMR_FREQ_LO_WARN 0x0040
411 #define DP83640_LQMR_DBLW_HI_WARN 0x0020
412 #define DP83640_LQMR_DBLW_LO_WARN 0x0010
413 #define DP83640_LQMR_DAGC_HI_WARN 0x0008
414 #define DP83640_LQMR_DAGC_LO_WARN 0x0004
415 #define DP83640_LQMR_C1_HI_WARN 0x0002
416 #define DP83640_LQMR_C1_LO_WARN 0x0001
417 
418 //Link Quality Data register
419 #define DP83640_LQDR_SAMPLE_PARAM 0x2000
420 #define DP83640_LQDR_WRITE_LQ_THR 0x1000
421 #define DP83640_LQDR_LQ_PARAM_SEL 0x0E00
422 #define DP83640_LQDR_LQ_THR_SEL 0x0100
423 #define DP83640_LQDR_LQ_THR_DATA 0x00FF
424 
425 //Link Quality Monitor 2 register
426 #define DP83640_LQMR2_RESTART_ON_VAR 0x0400
427 #define DP83640_LQMR2_VAR_HI_WARN 0x0002
428 
429 //PTP Control register
430 #define DP83640_PTP_CTL_TRIG_SEL 0x1C00
431 #define DP83640_PTP_CTL_TRIG_DIS 0x0200
432 #define DP83640_PTP_CTL_TRIG_EN 0x0100
433 #define DP83640_PTP_CTL_TRIG_READ 0x0080
434 #define DP83640_PTP_CTL_TRIG_LOAD 0x0040
435 #define DP83640_PTP_CTL_PTP_RD_CLK 0x0020
436 #define DP83640_PTP_CTL_PTP_LOAD_CLK 0x0010
437 #define DP83640_PTP_CTL_PTP_STEP_CLK 0x0008
438 #define DP83640_PTP_CTL_PTP_ENABLE 0x0004
439 #define DP83640_PTP_CTL_PTP_DISABLE 0x0002
440 #define DP83640_PTP_CTL_PTP_RESET 0x0001
441 
442 //PTP Time Data register
443 #define DP83640_PTP_TDR_TIME_DATA 0xFFFF
444 
445 //PTP Status register
446 #define DP83640_PTP_STS_TXTS_RDY 0x0800
447 #define DP83640_PTP_STS_RXTS_RDY 0x0400
448 #define DP83640_PTP_STS_TRIG_DONE 0x0200
449 #define DP83640_PTP_STS_EVENT_RDY 0x0100
450 #define DP83640_PTP_STS_TXTS_IE 0x0008
451 #define DP83640_PTP_STS_RXTS_IE 0x0004
452 #define DP83640_PTP_STS_TRIG_IE 0x0002
453 #define DP83640_PTP_STS_EVENT_IE 0x0001
454 
455 //PTP Trigger Status register
456 #define DP83640_PTP_TSTS_TRIG7_ERROR 0x8000
457 #define DP83640_PTP_TSTS_TRIG7_ACTIVE 0x4000
458 #define DP83640_PTP_TSTS_TRIG6_ERROR 0x2000
459 #define DP83640_PTP_TSTS_TRIG6_ACTIVE 0x2000
460 #define DP83640_PTP_TSTS_TRIG5_ERROR 0x0800
461 #define DP83640_PTP_TSTS_TRIG5_ACTIVE 0x0400
462 #define DP83640_PTP_TSTS_TRIG4_ERROR 0x0200
463 #define DP83640_PTP_TSTS_TRIG4_ACTIVE 0x0100
464 #define DP83640_PTP_TSTS_TRIG3_ERROR 0x0080
465 #define DP83640_PTP_TSTS_TRIG3_ACTIVE 0x0040
466 #define DP83640_PTP_TSTS_TRIG2_ERROR 0x0020
467 #define DP83640_PTP_TSTS_TRIG2_ACTIVE 0x0010
468 #define DP83640_PTP_TSTS_TRIG1_ERROR 0x0008
469 #define DP83640_PTP_TSTS_TRIG1_ACTIVE 0x0004
470 #define DP83640_PTP_TSTS_TRIG0_ERROR 0x0002
471 #define DP83640_PTP_TSTS_TRIG0_ACTIVE 0x0001
472 
473 //PTP Rate Low register
474 #define DP83640_PTP_RATEL_PTP_RATE_LO 0xFFFF
475 
476 //PTP Rate High register
477 #define DP83640_PTP_RATEH_PTP_RATE_DIR 0x8000
478 #define DP83640_PTP_RATEH_PTP_TMP_RATE 0x4000
479 #define DP83640_PTP_RATEH_PTP_RATE_HI 0x03FF
480 
481 //PTP Event Status register
482 #define DP83640_PTP_ESTS_EVNTS_MISSED 0x0700
483 #define DP83640_PTP_ESTS_EVNT_TS_LEN 0x00C0
484 #define DP83640_PTP_ESTS_EVNT_RF 0x0020
485 #define DP83640_PTP_ESTS_EVNT_NUM 0x001C
486 #define DP83640_PTP_ESTS_MULT_EVNT 0x0002
487 #define DP83640_PTP_ESTS_EVENT_DET 0x0001
488 
489 //PTP Event Data register
490 #define DP83640_PTP_EDATA_E7_RISE 0x8000
491 #define DP83640_PTP_EDATA_E7_DET 0x4000
492 #define DP83640_PTP_EDATA_E6_RISE 0x2000
493 #define DP83640_PTP_EDATA_E6_DET 0x1000
494 #define DP83640_PTP_EDATA_E5_RISE 0x0800
495 #define DP83640_PTP_EDATA_E5_DET 0x0400
496 #define DP83640_PTP_EDATA_E4_RISE 0x0200
497 #define DP83640_PTP_EDATA_E4_DET 0x0100
498 #define DP83640_PTP_EDATA_E3_RISE 0x0080
499 #define DP83640_PTP_EDATA_E3_DET 0x0040
500 #define DP83640_PTP_EDATA_E2_RISE 0x0020
501 #define DP83640_PTP_EDATA_E2_DET 0x0010
502 #define DP83640_PTP_EDATA_E1_RISE 0x0008
503 #define DP83640_PTP_EDATA_E1_DET 0x0004
504 #define DP83640_PTP_EDATA_E0_RISE 0x0002
505 #define DP83640_PTP_EDATA_E0_DET 0x0001
506 
507 //PTP Trigger Configuration register
508 #define DP83640_PTP_TRIG_TRIG_PULSE 0x8000
509 #define DP83640_PTP_TRIG_TRIG_PER 0x4000
510 #define DP83640_PTP_TRIG_TRIG_IF_LATE 0x2000
511 #define DP83640_PTP_TRIG_TRIG_NOTIFY 0x1000
512 #define DP83640_PTP_TRIG_TRIG_GPIO 0x0F00
513 #define DP83640_PTP_TRIG_TRIG_TOGGLE 0x0080
514 #define DP83640_PTP_TRIG_TRIG_CSEL 0x000E
515 #define DP83640_PTP_TRIG_TRIG_WR 0x0001
516 
517 //PTP Event Configuration register
518 #define DP83640_PTP_EVNT_EVNT_RISE 0x4000
519 #define DP83640_PTP_EVNT_EVNT_FALL 0x2000
520 #define DP83640_PTP_EVNT_EVNT_SINGLE 0x1000
521 #define DP83640_PTP_EVNT_EVNT_GPIO 0x0F00
522 #define DP83640_PTP_EVNT_EVNT_SEL 0x000E
523 #define DP83640_PTP_EVNT_EVNT_WR 0x0001
524 
525 //PTP Transmit Configuration 0 register
526 #define DP83640_PTP_TXCFG0_SYNC_1STEP 0x8000
527 #define DP83640_PTP_TXCFG0_DR_INSERT 0x2000
528 #define DP83640_PTP_TXCFG0_NTP_TS_EN 0x1000
529 #define DP83640_PTP_TXCFG0_IGNORE_2STEP 0x0800
530 #define DP83640_PTP_TXCFG0_CRC_1STEP 0x0400
531 #define DP83640_PTP_TXCFG0_CHK_1STEP 0x0200
532 #define DP83640_PTP_TXCFG0_IP1588_EN 0x0100
533 #define DP83640_PTP_TXCFG0_TX_L2_EN 0x0080
534 #define DP83640_PTP_TXCFG0_TX_IPV6_EN 0x0040
535 #define DP83640_PTP_TXCFG0_TX_IPV4_EN 0x0020
536 #define DP83640_PTP_TXCFG0_TX_PTP_VER 0x001E
537 #define DP83640_PTP_TXCFG0_TX_TS_EN 0x0001
538 
539 //PTP Transmit Configuration 1 register
540 #define DP83640_PTP_TXCFG1_BYTE0_MASK 0xFF00
541 #define DP83640_PTP_TXCFG1_BYTE0_DATA 0x00FF
542 
543 //PHY Status Frames Configuration 0 register
544 #define DP83640_PSF_CFG0_MAC_SRC_ADD 0x1800
545 #define DP83640_PSF_CFG0_MIN_PRE 0x0700
546 #define DP83640_PSF_CFG0_PSF_ENDIAN 0x0080
547 #define DP83640_PSF_CFG0_PSF_IPV4 0x0040
548 #define DP83640_PSF_CFG0_PSF_PCF_RD 0x0020
549 #define DP83640_PSF_CFG0_PSF_ERR_EN 0x0010
550 #define DP83640_PSF_CFG0_PSF_TXTS_EN 0x0008
551 #define DP83640_PSF_CFG0_PSF_RXTS_EN 0x0004
552 #define DP83640_PSF_CFG0_PSF_TRIG_EN 0x0002
553 #define DP83640_PSF_CFG0_PSF_EVNT_EN 0x0001
554 
555 //PTP Receive Configuration 0 register
556 #define DP83640_PTP_RXCFG0_DOMAIN_EN 0x8000
557 #define DP83640_PTP_RXCFG0_ALT_MAST_DIS 0x4000
558 #define DP83640_PTP_RXCFG0_USER_IP_SEL 0x2000
559 #define DP83640_PTP_RXCFG0_USER_IP_EN 0x1000
560 #define DP83640_PTP_RXCFG0_RX_SLAVE 0x0800
561 #define DP83640_PTP_RXCFG0_IP1588_EN 0x0700
562 #define DP83640_PTP_RXCFG0_RX_L2_EN 0x0080
563 #define DP83640_PTP_RXCFG0_RX_IPV6_EN 0x0040
564 #define DP83640_PTP_RXCFG0_RX_IPV4_EN 0x0020
565 #define DP83640_PTP_RXCFG0_RX_PTP_VER 0x001E
566 #define DP83640_PTP_RXCFG0_RX_TS_EN 0x0001
567 
568 //PTP Receive Configuration 1 register
569 #define DP83640_PTP_RXCFG1_BYTE0_MASK 0xFF00
570 #define DP83640_PTP_RXCFG1_BYTE0_DATA 0x00FF
571 
572 //PTP Receive Configuration 2 register
573 #define DP83640_PTP_RXCFG2_IP_ADDR_DATA 0xFFFF
574 
575 //PTP Receive Configuration 3 register
576 #define DP83640_PTP_RXCFG3_TS_MIN_IFG 0xF000
577 #define DP83640_PTP_RXCFG3_ACC_UDP 0x0800
578 #define DP83640_PTP_RXCFG3_ACC_CRC 0x0400
579 #define DP83640_PTP_RXCFG3_TS_APPEND 0x0200
580 #define DP83640_PTP_RXCFG3_TS_INSERT 0x0100
581 #define DP83640_PTP_RXCFG3_PTP_DOMAIN 0x00FF
582 
583 //PTP Receive Configuration 4 register
584 #define DP83640_PTP_RXCFG4_IPV4_UDP_MOD 0x8000
585 #define DP83640_PTP_RXCFG4_TS_SEC_EN 0x4000
586 #define DP83640_PTP_RXCFG4_TS_SEC_LEN 0x3000
587 #define DP83640_PTP_RXCFG4_RXTS_NS_OFF 0x0FC0
588 #define DP83640_PTP_RXCFG4_RXTS_SEC_OFF 0x003F
589 
590 //PTP Clock Output Control register
591 #define DP83640_PTP_COC_PTP_CLKOUT_EN 0x8000
592 #define DP83640_PTP_COC_PTP_CLKOUT_SEL 0x4000
593 #define DP83640_PTP_COC_PTP_CLKOUT_SPEEDSEL 0x2000
594 #define DP83640_PTP_COC_PTP_CLKDIV 0x00FF
595 
596 //PHY Status Frames Configuration 1 register
597 #define DP83640_PSF_CFG1_PTPRESERVED 0xF000
598 #define DP83640_PSF_CFG1_VERSIONPTP 0x0F00
599 #define DP83640_PSF_CFG1_TRANSPORT_SPECIFIC 0x00F0
600 #define DP83640_PSF_CFG1_MESSAGETYPE 0x000F
601 
602 //PHY Status Frames Configuration 2 register
603 #define DP83640_PSF_CFG2_IP_SA_BYTE1 0xFF00
604 #define DP83640_PSF_CFG2_IP_SA_BYTE0 0x00FF
605 
606 //PHY Status Frames Configuration 3 register
607 #define DP83640_PSF_CFG3_IP_SA_BYTE3 0xFF00
608 #define DP83640_PSF_CFG3_IP_SA_BYTE2 0x00FF
609 
610 //PHY Status Frames Configuration 4 register
611 #define DP83640_PSF_CFG4_IP_CHKSUM 0xFFFF
612 
613 //PTP SFD Configuration register
614 #define DP83640_PTP_SFDCFG_TX_SFD_GPIO 0x00F0
615 #define DP83640_PTP_SFDCFG_RX_SFD_GPIO 0x000F
616 
617 //PTP Interrupt Control register
618 #define DP83640_PTP_INTCTL_PTP_INT_GPIO 0x000F
619 
620 //PTP Clock Source register
621 #define DP83640_PTP_CLKSRC_CLK_SRC 0xC000
622 #define DP83640_PTP_CLKSRC_CLK_SRC_PER 0x007F
623 
624 //PTP Offset register
625 #define DP83640_PTP_OFF_PTP_OFFSET 0x00FF
626 
627 //PTP GPIO Monitor register
628 #define DP83640_PTP_GPIOMON_PTP_GPIO_IN 0x0FFF
629 
630 //PTP Receive Hash register
631 #define DP83640_PTP_RXHASH_RX_HASH_EN 0x1000
632 #define DP83640_PTP_RXHASH_PTP_RX_HASH 0x0FFF
633 
634 //C++ guard
635 #ifdef __cplusplus
636 extern "C" {
637 #endif
638 
639 //DP83640 Ethernet PHY driver
640 extern const PhyDriver dp83640PhyDriver;
641 
642 //DP83640 related functions
643 error_t dp83640Init(NetInterface *interface);
644 
645 void dp83640Tick(NetInterface *interface);
646 
647 void dp83640EnableIrq(NetInterface *interface);
648 void dp83640DisableIrq(NetInterface *interface);
649 
650 void dp83640EventHandler(NetInterface *interface);
651 
652 void dp83640WritePhyReg(NetInterface *interface, uint8_t address,
653  uint16_t data);
654 
655 uint16_t dp83640ReadPhyReg(NetInterface *interface, uint8_t address);
656 
657 void dp83640DumpPhyReg(NetInterface *interface);
658 
659 //C++ guard
660 #ifdef __cplusplus
661 }
662 #endif
663 
664 #endif
PHY driver.
Definition: nic.h:214
void dp83640EventHandler(NetInterface *interface)
DP83640 event handler.
void dp83640DisableIrq(NetInterface *interface)
Disable interrupts.
error_t
Error codes.
Definition: error.h:42
void dp83640EnableIrq(NetInterface *interface)
Enable interrupts.
#define NetInterface
Definition: net.h:36
const PhyDriver dp83640PhyDriver
DP83640 Ethernet PHY driver.
void dp83640DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
void dp83640Tick(NetInterface *interface)
DP83640 timer handler.
uint16_t dp83640ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
Network interface controller abstraction layer.
error_t dp83640Init(NetInterface *interface)
DP83640 PHY transceiver initialization.
Ipv6Addr address
uint8_t data[]
Definition: dtls_misc.h:176
void dp83640WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.