dp83tg720_driver.c
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1 /**
2  * @file dp83tg720_driver.c
3  * @brief DP83TG720 1000Base-T1 Ethernet PHY driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.4
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "core/net.h"
37 #include "debug.h"
38 
39 
40 /**
41  * @brief DP83TG720 Ethernet PHY driver
42  **/
43 
45 {
51 };
52 
53 
54 /**
55  * @brief DP83TG720 PHY transceiver initialization
56  * @param[in] interface Underlying network interface
57  * @return Error code
58  **/
59 
61 {
62  //Debug message
63  TRACE_INFO("Initializing DP83TG720...\r\n");
64 
65  //Undefined PHY address?
66  if(interface->phyAddr >= 32)
67  {
68  //Use the default address
69  interface->phyAddr = DP83TG720_PHY_ADDR;
70  }
71 
72  //Initialize serial management interface
73  if(interface->smiDriver != NULL)
74  {
75  interface->smiDriver->init();
76  }
77 
78  //Initialize external interrupt line driver
79  if(interface->extIntDriver != NULL)
80  {
81  interface->extIntDriver->init();
82  }
83 
84  //Reset PHY transceiver
86 
87  //Wait for the reset to complete
88  while(dp83tg720ReadPhyReg(interface, DP83TG720_BMCR) &
90  {
91  }
92 
93  //Dump PHY registers for debugging purpose
94  dp83tg720DumpPhyReg(interface);
95 
96  //Perform custom configuration
97  dp83tg720InitHook(interface);
98 
99  //Force the TCP/IP stack to poll the link state at startup
100  interface->phyEvent = TRUE;
101  //Notify the TCP/IP stack of the event
103 
104  //Successful initialization
105  return NO_ERROR;
106 }
107 
108 
109 /**
110  * @brief DP83TG720 custom configuration
111  * @param[in] interface Underlying network interface
112  **/
113 
114 __weak_func void dp83tg720InitHook(NetInterface *interface)
115 {
116 }
117 
118 
119 /**
120  * @brief DP83TG720 timer handler
121  * @param[in] interface Underlying network interface
122  **/
123 
124 void dp83tg720Tick(NetInterface *interface)
125 {
126  uint16_t value;
127  bool_t linkState;
128 
129  //No external interrupt line driver?
130  if(interface->extIntDriver == NULL)
131  {
132  //Read PHY status register
134  //Retrieve current link state
135  linkState = (value & DP83TG720_BMSR_LINK_STATUS) ? TRUE : FALSE;
136 
137  //Link up event?
138  if(linkState && !interface->linkState)
139  {
140  //Set event flag
141  interface->phyEvent = TRUE;
142  //Notify the TCP/IP stack of the event
144  }
145  //Link down event?
146  else if(!linkState && interface->linkState)
147  {
148  //Set event flag
149  interface->phyEvent = TRUE;
150  //Notify the TCP/IP stack of the event
152  }
153  }
154 }
155 
156 
157 /**
158  * @brief Enable interrupts
159  * @param[in] interface Underlying network interface
160  **/
161 
163 {
164  //Enable PHY transceiver interrupts
165  if(interface->extIntDriver != NULL)
166  {
167  interface->extIntDriver->enableIrq();
168  }
169 }
170 
171 
172 /**
173  * @brief Disable interrupts
174  * @param[in] interface Underlying network interface
175  **/
176 
178 {
179  //Disable PHY transceiver interrupts
180  if(interface->extIntDriver != NULL)
181  {
182  interface->extIntDriver->disableIrq();
183  }
184 }
185 
186 
187 /**
188  * @brief DP83TG720 event handler
189  * @param[in] interface Underlying network interface
190  **/
191 
193 {
194  uint16_t value;
195 
196  //Read PHY status register
198 
199  //Link is up?
200  if((value & DP83TG720_BMSR_LINK_STATUS) != 0)
201  {
202  //The PHY is only able to operate in 1 Gbps mode
203  interface->linkSpeed = NIC_LINK_SPEED_1GBPS;
204  interface->duplexMode = NIC_FULL_DUPLEX_MODE;
205 
206  //Adjust MAC configuration parameters for proper operation
207  interface->nicDriver->updateMacConfig(interface);
208 
209  //Update link state
210  interface->linkState = TRUE;
211  }
212  else
213  {
214  //Update link state
215  interface->linkState = FALSE;
216  }
217 
218  //Process link state change event
219  nicNotifyLinkChange(interface);
220 }
221 
222 
223 /**
224  * @brief Write PHY register
225  * @param[in] interface Underlying network interface
226  * @param[in] address PHY register address
227  * @param[in] data Register value
228  **/
229 
230 void dp83tg720WritePhyReg(NetInterface *interface, uint8_t address,
231  uint16_t data)
232 {
233  //Write the specified PHY register
234  if(interface->smiDriver != NULL)
235  {
236  interface->smiDriver->writePhyReg(SMI_OPCODE_WRITE,
237  interface->phyAddr, address, data);
238  }
239  else
240  {
241  interface->nicDriver->writePhyReg(SMI_OPCODE_WRITE,
242  interface->phyAddr, address, data);
243  }
244 }
245 
246 
247 /**
248  * @brief Read PHY register
249  * @param[in] interface Underlying network interface
250  * @param[in] address PHY register address
251  * @return Register value
252  **/
253 
254 uint16_t dp83tg720ReadPhyReg(NetInterface *interface, uint8_t address)
255 {
256  uint16_t data;
257 
258  //Read the specified PHY register
259  if(interface->smiDriver != NULL)
260  {
261  data = interface->smiDriver->readPhyReg(SMI_OPCODE_READ,
262  interface->phyAddr, address);
263  }
264  else
265  {
266  data = interface->nicDriver->readPhyReg(SMI_OPCODE_READ,
267  interface->phyAddr, address);
268  }
269 
270  //Return the value of the PHY register
271  return data;
272 }
273 
274 
275 /**
276  * @brief Dump PHY registers for debugging purpose
277  * @param[in] interface Underlying network interface
278  **/
279 
281 {
282  uint8_t i;
283 
284  //Loop through PHY registers
285  for(i = 0; i < 32; i++)
286  {
287  //Display current PHY register
288  TRACE_DEBUG("%02" PRIu8 ": 0x%04" PRIX16 "\r\n", i,
289  dp83tg720ReadPhyReg(interface, i));
290  }
291 
292  //Terminate with a line feed
293  TRACE_DEBUG("\r\n");
294 }
295 
296 
297 /**
298  * @brief Write MMD register
299  * @param[in] interface Underlying network interface
300  * @param[in] devAddr Device address
301  * @param[in] regAddr Register address
302  * @param[in] data MMD register value
303  **/
304 
305 void dp83tg720WriteMmdReg(NetInterface *interface, uint8_t devAddr,
306  uint16_t regAddr, uint16_t data)
307 {
308  //Select register operation
311 
312  //Write MMD register address
314 
315  //Select data operation
318 
319  //Write the content of the MMD register
321 }
322 
323 
324 /**
325  * @brief Read MMD register
326  * @param[in] interface Underlying network interface
327  * @param[in] devAddr Device address
328  * @param[in] regAddr Register address
329  * @return MMD register value
330  **/
331 
332 uint16_t dp83tg720ReadMmdReg(NetInterface *interface, uint8_t devAddr,
333  uint16_t regAddr)
334 {
335  //Select register operation
338 
339  //Write MMD register address
341 
342  //Select data operation
345 
346  //Read the content of the MMD register
347  return dp83tg720ReadPhyReg(interface, DP83TG720_ADDAR);
348 }
void nicNotifyLinkChange(NetInterface *interface)
Process link state change notification.
Definition: nic.c:559
@ NIC_LINK_SPEED_1GBPS
Definition: nic.h:113
void dp83tg720WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
int bool_t
Definition: compiler_port.h:53
#define netEvent
Definition: net_legacy.h:196
#define DP83TG720_BMSR_LINK_STATUS
@ NIC_FULL_DUPLEX_MODE
Definition: nic.h:125
#define DP83TG720_ADDAR
#define TRUE
Definition: os_port.h:50
Ethernet PHY driver.
Definition: nic.h:311
uint8_t data[]
Definition: ethernet.h:222
#define DP83TG720_PHY_ADDR
const PhyDriver dp83tg720PhyDriver
DP83TG720 Ethernet PHY driver.
void dp83tg720EventHandler(NetInterface *interface)
DP83TG720 event handler.
#define SMI_OPCODE_WRITE
Definition: nic.h:66
void dp83tg720WriteMmdReg(NetInterface *interface, uint8_t devAddr, uint16_t regAddr, uint16_t data)
Write MMD register.
#define FALSE
Definition: os_port.h:46
error_t
Error codes.
Definition: error.h:43
#define DP83TG720_BMCR_MII_RESET
#define NetInterface
Definition: net.h:36
#define SMI_OPCODE_READ
Definition: nic.h:67
uint16_t dp83tg720ReadMmdReg(NetInterface *interface, uint8_t devAddr, uint16_t regAddr)
Read MMD register.
#define TRACE_INFO(...)
Definition: debug.h:95
#define DP83TG720_REGCR_DEVAD
#define TRACE_DEBUG(...)
Definition: debug.h:107
error_t dp83tg720Init(NetInterface *interface)
DP83TG720 PHY transceiver initialization.
uint16_t regAddr
Ipv6Addr address[]
Definition: ipv6.h:325
uint8_t value[]
Definition: tcp.h:369
void dp83tg720Tick(NetInterface *interface)
DP83TG720 timer handler.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
__weak_func void dp83tg720InitHook(NetInterface *interface)
DP83TG720 custom configuration.
void dp83tg720DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
TCP/IP stack core.
#define DP83TG720_BMSR
void dp83tg720DisableIrq(NetInterface *interface)
Disable interrupts.
void dp83tg720EnableIrq(NetInterface *interface)
Enable interrupts.
#define DP83TG720_REGCR
#define DP83TG720_REGCR_CMD_ADDR
uint16_t dp83tg720ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
@ NO_ERROR
Success.
Definition: error.h:44
Debugging facilities.
DP83TG720 1000Base-T1 Ethernet PHY driver.
#define DP83TG720_BMCR
#define DP83TG720_REGCR_CMD_DATA_NO_POST_INC