enc624j600_driver.h
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1 /**
2  * @file enc624j600_driver.h
3  * @brief ENC624J600/ENC424J600 Ethernet controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _ENC624J600_DRIVER_H
32 #define _ENC624J600_DRIVER_H
33 
34 //Receive and transmit buffers
35 #define ENC624J600_TX_BUFFER_START 0x0000
36 #define ENC624J600_TX_BUFFER_STOP 0x17FE
37 #define ENC624J600_RX_BUFFER_START 0x1800
38 #define ENC624J600_RX_BUFFER_STOP 0x5FFE
39 
40 //SPI command set
41 #define ENC624J600_CMD_B0SEL 0xC0 //Bank 0 Select
42 #define ENC624J600_CMD_B1SEL 0xC2 //Bank 1 Select
43 #define ENC624J600_CMD_B2SEL 0xC4 //Bank 2 Select
44 #define ENC624J600_CMD_B3SEL 0xC6 //Bank 3 Select
45 #define ENC624J600_CMD_SETETHRST 0xCA //System Reset
46 #define ENC624J600_CMD_FCDISABLE 0xE0 //Flow Control Disable
47 #define ENC624J600_CMD_FCSINGLE 0xE2 //Flow Control Single
48 #define ENC624J600_CMD_FCMULTIPLE 0xE4 //Flow Control Multiple
49 #define ENC624J600_CMD_FCCLEAR 0xE6 //Flow Control Clear
50 #define ENC624J600_CMD_SETPKTDEC 0xCC //Decrement Packet Counter
51 #define ENC624J600_CMD_DMASTOP 0xD2 //DMA Stop
52 #define ENC624J600_CMD_DMACKSUM 0xD8 //DMA Start Checksum
53 #define ENC624J600_CMD_DMACKSUMS 0xDA //DMA Start Checksum with Seed
54 #define ENC624J600_CMD_DMACOPY 0xDC //DMA Start Copy
55 #define ENC624J600_CMD_DMACOPYS 0xDE //DMA Start Copy and Checksum with Seed
56 #define ENC624J600_CMD_SETTXRTS 0xD4 //Request Packet Transmission
57 #define ENC624J600_CMD_ENABLERX 0xE8 //Enable RX
58 #define ENC624J600_CMD_DISABLERX 0xEA //Disable RX
59 #define ENC624J600_CMD_SETEIE 0xEC //Enable Interrupts
60 #define ENC624J600_CMD_CLREIE 0xEE //Disable Interrupts
61 #define ENC624J600_CMD_RBSEL 0xC8 //Read Bank Select
62 #define ENC624J600_CMD_WGPRDPT 0x60 //Write EGPRDPT
63 #define ENC624J600_CMD_RGPRDPT 0x62 //Read EGPRDPT
64 #define ENC624J600_CMD_WRXRDPT 0x64 //Write ERXRDPT
65 #define ENC624J600_CMD_RRXRDPT 0x66 //Read ERXRDPT
66 #define ENC624J600_CMD_WUDARDPT 0x68 //Write EUDARDPT
67 #define ENC624J600_CMD_RUDARDPT 0x6A //Read EUDARDPT
68 #define ENC624J600_CMD_WGPWRPT 0x6C //Write EGPWRPT
69 #define ENC624J600_CMD_RGPWRPT 0x6E //Read EGPWRPT
70 #define ENC624J600_CMD_WRXWRPT 0x70 //Write ERXWRPT
71 #define ENC624J600_CMD_RRXWRPT 0x72 //Read ERXWRPT
72 #define ENC624J600_CMD_WUDAWRPT 0x74 //Write EUDAWRPT
73 #define ENC624J600_CMD_RUDAWRPT 0x76 //Read EUDAWRPT
74 #define ENC624J600_CMD_RCR 0x00 //Read Control Register
75 #define ENC624J600_CMD_WCR 0x40 //Write Control Register
76 #define ENC624J600_CMD_RCRU 0x20 //Read Control Register Unbanked
77 #define ENC624J600_CMD_WCRU 0x22 //Write Control Register Unbanked
78 #define ENC624J600_CMD_BFS 0x80 //Bit Field Set
79 #define ENC624J600_CMD_BFC 0xA0 //Bit Field Clear
80 #define ENC624J600_CMD_BFSU 0x24 //Bit Field Set Unbanked
81 #define ENC624J600_CMD_BFCU 0x26 //Bit Field Clear Unbanked
82 #define ENC624J600_CMD_RGPDATA 0x28 //Read EGPDATA
83 #define ENC624J600_CMD_WGPDATA 0x2A //Write EGPDATA
84 #define ENC624J600_CMD_RRXDATA 0x2C //Read ERXDATA
85 #define ENC624J600_CMD_WRXDATA 0x2E //Write ERXDATA
86 #define ENC624J600_CMD_RUDADATA 0x30 //Read EUDADATA
87 #define ENC624J600_CMD_WUDADATA 0x32 //Write EUDADATA
88 
89 //ENC624J600 registers
90 #define ENC624J600_REG_ETXST 0x00
91 #define ENC624J600_REG_ETXLEN 0x02
92 #define ENC624J600_REG_ERXST 0x04
93 #define ENC624J600_REG_ERXTAIL 0x06
94 #define ENC624J600_REG_ERXHEAD 0x08
95 #define ENC624J600_REG_EDMAST 0x0A
96 #define ENC624J600_REG_EDMALEN 0x0C
97 #define ENC624J600_REG_EDMADST 0x0E
98 #define ENC624J600_REG_EDMACS 0x10
99 #define ENC624J600_REG_ETXSTAT 0x12
100 #define ENC624J600_REG_ETXWIRE 0x14
101 #define ENC624J600_REG_EUDAST 0x16
102 #define ENC624J600_REG_EUDAND 0x18
103 #define ENC624J600_REG_ESTAT 0x1A
104 #define ENC624J600_REG_EIR 0x1C
105 #define ENC624J600_REG_ECON1 0x1E
106 #define ENC624J600_REG_EHT1 0x20
107 #define ENC624J600_REG_EHT2 0x22
108 #define ENC624J600_REG_EHT3 0x24
109 #define ENC624J600_REG_EHT4 0x26
110 #define ENC624J600_REG_EPMM1 0x28
111 #define ENC624J600_REG_EPMM2 0x2A
112 #define ENC624J600_REG_EPMM3 0x2C
113 #define ENC624J600_REG_EPMM4 0x2E
114 #define ENC624J600_REG_EPMCS 0x30
115 #define ENC624J600_REG_EPMO 0x32
116 #define ENC624J600_REG_ERXFCON 0x34
117 #define ENC624J600_REG_MACON1 0x40
118 #define ENC624J600_REG_MACON2 0x42
119 #define ENC624J600_REG_MABBIPG 0x44
120 #define ENC624J600_REG_MAIPG 0x46
121 #define ENC624J600_REG_MACLCON 0x48
122 #define ENC624J600_REG_MAMXFL 0x4A
123 #define ENC624J600_REG_MICMD 0x52
124 #define ENC624J600_REG_MIREGADR 0x54
125 #define ENC624J600_REG_MAADR3 0x60
126 #define ENC624J600_REG_MAADR2 0x62
127 #define ENC624J600_REG_MAADR1 0x64
128 #define ENC624J600_REG_MIWR 0x66
129 #define ENC624J600_REG_MIRD 0x68
130 #define ENC624J600_REG_MISTAT 0x6A
131 #define ENC624J600_REG_EPAUS 0x6C
132 #define ENC624J600_REG_ECON2 0x6E
133 #define ENC624J600_REG_ERXWM 0x70
134 #define ENC624J600_REG_EIE 0x72
135 #define ENC624J600_REG_EIDLED 0x74
136 #define ENC624J600_REG_EGPDATA 0x80
137 #define ENC624J600_REG_ERXDATA 0x82
138 #define ENC624J600_REG_EUDADATA 0x84
139 #define ENC624J600_REG_EGPRDPT 0x86
140 #define ENC624J600_REG_EGPWRPT 0x88
141 #define ENC624J600_REG_ERXRDPT 0x8A
142 #define ENC624J600_REG_ERXWRPT 0x8C
143 #define ENC624J600_REG_EUDARDPT 0x8E
144 #define ENC624J600_REG_EUDAWRPT 0x90
145 
146 //ENC624J600 PHY registers
147 #define ENC624J600_PHY_REG_PHCON1 0x00
148 #define ENC624J600_PHY_REG_PHSTAT1 0x01
149 #define ENC624J600_PHY_REG_PHANA 0x04
150 #define ENC624J600_PHY_REG_PHANLPA 0x05
151 #define ENC624J600_PHY_REG_PHANE 0x06
152 #define ENC624J600_PHY_REG_PHCON2 0x11
153 #define ENC624J600_PHY_REG_PHSTAT2 0x1B
154 #define ENC624J600_PHY_REG_PHSTAT3 0x1F
155 
156 //ESTAT register
157 #define ESTAT_INT 0x8000
158 #define ESTAT_FCIDLE 0x4000
159 #define ESTAT_RXBUSY 0x2000
160 #define ESTAT_CLKRDY 0x1000
161 #define ESTAT_R11 0x0800
162 #define ESTAT_PHYDPX 0x0400
163 #define ESTAT_R9 0x0200
164 #define ESTAT_PHYLNK 0x0100
165 #define ESTAT_PKTCNT 0x00FF
166 
167 //EIR register
168 #define EIR_CRYPTEN 0x8000
169 #define EIR_MODEXIF 0x4000
170 #define EIR_HASHIF 0x2000
171 #define EIR_AESIF 0x1000
172 #define EIR_LINKIF 0x0800
173 #define EIR_R10 0x0400
174 #define EIR_R9 0x0200
175 #define EIR_R8 0x0100
176 #define EIR_R7 0x0080
177 #define EIR_PKTIF 0x0040
178 #define EIR_DMAIF 0x0020
179 #define EIR_R4 0x0010
180 #define EIR_TXIF 0x0008
181 #define EIR_TXABTIF 0x0004
182 #define EIR_RXABTIF 0x0002
183 #define EIR_PCFULIF 0x0001
184 
185 //ECON1 register
186 #define ECON1_MODEXST 0x8000
187 #define ECON1_HASHEN 0x4000
188 #define ECON1_HASHOP 0x2000
189 #define ECON1_HASHLST 0x1000
190 #define ECON1_AESST 0x0800
191 #define ECON1_AESOP1 0x0400
192 #define ECON1_AESOP0 0x0200
193 #define ECON1_PKTDEC 0x0100
194 #define ECON1_FCOP1 0x0080
195 #define ECON1_FCOP0 0x0040
196 #define ECON1_DMAST 0x0020
197 #define ECON1_DMACPY 0x0010
198 #define ECON1_DMACSSD 0x0008
199 #define ECON1_DMANOCS 0x0004
200 #define ECON1_TXRTS 0x0002
201 #define ECON1_RXEN 0x0001
202 
203 //ETXSTAT register
204 #define ETXSTAT_R12 0x1000
205 #define ETXSTAT_R11 0x0800
206 #define ETXSTAT_LATECOL 0x0400
207 #define ETXSTAT_MAXCOL 0x0200
208 #define ETXSTAT_EXDEFER 0x0100
209 #define ETXSTAT_DEFER 0x0080
210 #define ETXSTAT_R6 0x0040
211 #define ETXSTAT_R5 0x0020
212 #define ETXSTAT_CRCBAD 0x0010
213 #define ETXSTAT_COLCNT 0x000F
214 
215 //ERXFCON register
216 #define ERXFCON_HTEN 0x8000
217 #define ERXFCON_MPEN 0x4000
218 #define ERXFCON_NOTPM 0x1000
219 #define ERXFCON_PMEN3 0x0800
220 #define ERXFCON_PMEN2 0x0400
221 #define ERXFCON_PMEN1 0x0200
222 #define ERXFCON_PMEN0 0x0100
223 #define ERXFCON_CRCEEN 0x0080
224 #define ERXFCON_CRCEN 0x0040
225 #define ERXFCON_RUNTEEN 0x0020
226 #define ERXFCON_RUNTEN 0x0010
227 #define ERXFCON_UCEN 0x0008
228 #define ERXFCON_NOTMEEN 0x0004
229 #define ERXFCON_MCEN 0x0002
230 #define ERXFCON_BCEN 0x0001
231 
232 //MACON1 register
233 #define MACON1_R15 0x8000
234 #define MACON1_R14 0x4000
235 #define MACON1_R11 0x0800
236 #define MACON1_R10 0x0400
237 #define MACON1_R9 0x0200
238 #define MACON1_R8 0x0100
239 #define MACON1_LOOPBK 0x0010
240 #define MACON1_R3 0x0008
241 #define MACON1_RXPAUS 0x0004
242 #define MACON1_PASSALL 0x0002
243 #define MACON1_R0 0x0001
244 
245 //MACON2 register
246 #define MACON2_DEFER 0x4000
247 #define MACON2_BPEN 0x2000
248 #define MACON2_NOBKOFF 0x1000
249 #define MACON2_R9 0x0200
250 #define MACON2_R8 0x0100
251 #define MACON2_PADCFG2 0x0080
252 #define MACON2_PADCFG1 0x0040
253 #define MACON2_PADCFG0 0x0020
254 #define MACON2_TXCRCEN 0x0010
255 #define MACON2_PHDREN 0x0008
256 #define MACON2_HFRMEN 0x0004
257 #define MACON2_R1 0x0002
258 #define MACON2_FULDPX 0x0001
259 
260 //MABBIPG register
261 #define MABBIPG_BBIPG 0x007F
262 
263 //MAIPG register
264 #define MAIPG_R14 0x4000
265 #define MAIPG_R13 0x2000
266 #define MAIPG_R12 0x1000
267 #define MAIPG_R11 0x0800
268 #define MAIPG_R10 0x0400
269 #define MAIPG_R9 0x0200
270 #define MAIPG_R8 0x0100
271 #define MAIPG_IPG 0x007F
272 
273 //MACLCON register
274 #define MACLCON_R13 0x2000
275 #define MACLCON_R12 0x1000
276 #define MACLCON_R11 0x0800
277 #define MACLCON_R10 0x0400
278 #define MACLCON_R9 0x0200
279 #define MACLCON_R8 0x0100
280 #define MACLCON_MAXRET 0x000F
281 
282 //MICMD register
283 #define MICMD_MIISCAN 0x0002
284 #define MICMD_MIIRD 0x0001
285 
286 //MIREGADR register
287 #define MIREGADR_R12 0x1000
288 #define MIREGADR_R11 0x0800
289 #define MIREGADR_R10 0x0400
290 #define MIREGADR_R9 0x0200
291 #define MIREGADR_R8 0x0100
292 #define MIREGADR_PHREG 0x001F
293 
294 //MISTAT register
295 #define MISTAT_R3 0x0008
296 #define MISTAT_NVALID 0x0004
297 #define MISTAT_SCAN 0x0002
298 #define MISTAT_BUSY 0x0001
299 
300 //ECON2 register
301 #define ECON2_ETHEN 0x8000
302 #define ECON2_STRCH 0x4000
303 #define ECON2_TXMAC 0x2000
304 #define ECON2_SHA1MD5 0x1000
305 #define ECON2_COCON3 0x0800
306 #define ECON2_COCON2 0x0400
307 #define ECON2_COCON1 0x0200
308 #define ECON2_COCON0 0x0100
309 #define ECON2_AUTOFC 0x0080
310 #define ECON2_TXRST 0x0040
311 #define ECON2_RXRST 0x0020
312 #define ECON2_ETHRST 0x0010
313 #define ECON2_MODLEN1 0x0008
314 #define ECON2_MODLEN0 0x0004
315 #define ECON2_AESLEN1 0x0002
316 #define ECON2_AESLEN0 0x0001
317 
318 //ERXWM register
319 #define ERXWM_RXFWM 0xFF00
320 #define ERXWM_RXEWM 0x00FF
321 
322 //EIE register
323 #define EIE_INTIE 0x8000
324 #define EIE_MODEXIE 0x4000
325 #define EIE_HASHIE 0x2000
326 #define EIE_AESIE 0x1000
327 #define EIE_LINKIE 0x0800
328 #define EIE_R10 0x0400
329 #define EIE_R9 0x0200
330 #define EIE_R8 0x0100
331 #define EIE_R7 0x0080
332 #define EIE_PKTIE 0x0040
333 #define EIE_DMAIE 0x0020
334 #define EIE_R4 0x0010
335 #define EIE_TXIE 0x0008
336 #define EIE_TXABTIE 0x0004
337 #define EIE_RXABTIE 0x0002
338 #define EIE_PCFULIE 0x0001
339 
340 //EIDLED register
341 #define EIDLED_LACFG3 0x8000
342 #define EIDLED_LACFG2 0x4000
343 #define EIDLED_LACFG1 0x2000
344 #define EIDLED_LACFG0 0x1000
345 #define EIDLED_LBCFG3 0x0800
346 #define EIDLED_LBCFG2 0x0400
347 #define EIDLED_LBCFG1 0x0200
348 #define EIDLED_LBCFG0 0x0100
349 #define EIDLED_DEVID 0x00FF
350 
351 //PHCON1 register
352 #define PHCON1_PRST 0x8000
353 #define PHCON1_PLOOPBK 0x4000
354 #define PHCON1_SPD100 0x2000
355 #define PHCON1_ANEN 0x1000
356 #define PHCON1_PSLEEP 0x0800
357 #define PHCON1_RENEG 0x0200
358 #define PHCON1_PFULDPX 0x0100
359 
360 //PHSTAT1 register
361 #define PHSTAT1_FULL100 0x4000
362 #define PHSTAT1_HALF100 0x2000
363 #define PHSTAT1_FULL10 0x1000
364 #define PHSTAT1_HALF10 0x0800
365 #define PHSTAT1_ANDONE 0x0020
366 #define PHSTAT1_LRFAULT 0x0010
367 #define PHSTAT1_ANABLE 0x0008
368 #define PHSTAT1_LLSTAT 0x0004
369 #define PHSTAT1_EXTREGS 0x0001
370 
371 //PHANA register
372 #define PHANA_ADNP 0x8000
373 #define PHANA_ADFAULT 0x2000
374 #define PHANA_ADPAUS1 0x0800
375 #define PHANA_ADPAUS0 0x0400
376 #define PHANA_AD100FD 0x0100
377 #define PHANA_AD100 0x0080
378 #define PHANA_AD10FD 0x0040
379 #define PHANA_AD10 0x0020
380 #define PHANA_ADIEEE4 0x0010
381 #define PHANA_ADIEEE3 0x0008
382 #define PHANA_ADIEEE2 0x0004
383 #define PHANA_ADIEEE1 0x0002
384 #define PHANA_ADIEEE0 0x0001
385 
386 //PHANLPA register
387 #define PHANLPA_LPNP 0x8000
388 #define PHANLPA_LPACK 0x4000
389 #define PHANLPA_LPFAULT 0x2000
390 #define PHANLPA_LPPAUS1 0x0800
391 #define PHANLPA_LPPAUS0 0x0400
392 #define PHANLPA_LP100T4 0x0200
393 #define PHANLPA_LP100FD 0x0100
394 #define PHANLPA_LP100 0x0080
395 #define PHANLPA_LP10FD 0x0040
396 #define PHANLPA_LP10 0x0020
397 #define PHANLPA_LPIEEE 0x001F
398 #define PHANLPA_LPIEEE4 0x0010
399 #define PHANLPA_LPIEEE3 0x0008
400 #define PHANLPA_LPIEEE2 0x0004
401 #define PHANLPA_LPIEEE1 0x0002
402 #define PHANLPA_LPIEEE0 0x0001
403 
404 //PHANE register
405 #define PHANE_PDFLT 0x0010
406 #define PHANE_LPARCD 0x0002
407 #define PHANE_LPANABL 0x0001
408 
409 //PHCON2 register
410 #define PHCON2_EDPWRDN 0x2000
411 #define PHCON2_EDTHRES 0x0800
412 #define PHCON2_FRCLNK 0x0004
413 #define PHCON2_EDSTAT 0x0002
414 
415 //PHSTAT2 register
416 #define PHSTAT2_PLRITY 0x0010
417 
418 //PHSTAT3 register
419 #define PHSTAT3_SPDDPX2 0x0010
420 #define PHSTAT3_SPDDPX1 0x0008
421 #define PHSTAT3_SPDDPX0 0x0004
422 
423 //Receive status vector
424 #define RSV_UNICAST_FILTER 0x00100000
425 #define RSV_PATTERN_MATCH_FILTER 0x00080000
426 #define RSV_MAGIC_PACKET_FILTER 0x00040000
427 #define RSV_HASH_FILTER 0x00020000
428 #define RSV_NOT_ME_FILTER 0x00010000
429 #define RSV_RUNT_FILTER 0x00008000
430 #define RSV_VLAN_TYPE 0x00004000
431 #define RSV_UNKNOWN_OPCODE 0x00002000
432 #define RSV_PAUSE_CONTROL_FRAME 0x00001000
433 #define RSV_CONTROL_FRAME 0x00000800
434 #define RSV_DRIBBLE_NIBBLE 0x00000400
435 #define RSV_BROADCAST_PACKET 0x00000200
436 #define RSV_MULTICAST_PACKET 0x00000100
437 #define RSV_RECEIVED_OK 0x00000080
438 #define RSV_LENGTH_OUT_OF_RANGE 0x00000040
439 #define RSV_LENGTH_CHECK_ERROR 0x00000020
440 #define RSV_CRC_ERROR 0x00000010
441 #define RSV_CARRIER_EVENT 0x00000004
442 #define RSV_PACKET_IGNORED 0x00000001
443 
444 //C++ guard
445 #ifdef __cplusplus
446 extern "C" {
447 #endif
448 
449 
450 /**
451  * @brief ENC624J600 driver context
452  **/
453 
454 typedef struct
455 {
456  uint16_t nextPacket; ///<Next packet in the receive buffer
457  uint8_t *rxBuffer; ///<Receive buffer
459 
460 
461 //ENC624J600 driver
462 extern const NicDriver enc624j600Driver;
463 
464 //ENC624J600 related functions
466 
467 void enc624j600Tick(NetInterface *interface);
468 
469 void enc624j600EnableIrq(NetInterface *interface);
470 void enc624j600DisableIrq(NetInterface *interface);
472 void enc624j600EventHandler(NetInterface *interface);
473 
475  const NetBuffer *buffer, size_t offset);
476 
478 
480 void enc624j600UpdateMacConfig(NetInterface *interface);
481 
483 
484 void enc624j600WriteReg(NetInterface *interface, uint8_t address,
485  uint16_t data);
486 
487 uint16_t enc624j600ReadReg(NetInterface *interface, uint8_t address);
488 
489 void enc624j600WritePhyReg(NetInterface *interface, uint8_t address,
490  uint16_t data);
491 
492 uint16_t enc624j600ReadPhyReg(NetInterface *interface, uint8_t address);
493 
494 void enc624j600WriteBuffer(NetInterface *interface,
495  uint8_t opcode, const NetBuffer *buffer, size_t offset);
496 
497 void enc624j600ReadBuffer(NetInterface *interface,
498  uint8_t opcode, uint8_t *data, size_t length);
499 
500 void enc624j600SetBit(NetInterface *interface, uint8_t address,
501  uint16_t mask);
502 
503 void enc624j600ClearBit(NetInterface *interface, uint8_t address,
504  uint16_t mask);
505 
506 uint32_t enc624j600CalcCrc(const void *data, size_t length);
507 
508 void enc624j600DumpReg(NetInterface *interface);
509 void enc624j600DumpPhyReg(NetInterface *interface);
510 
511 //C++ guard
512 #ifdef __cplusplus
513 }
514 #endif
515 
516 #endif
void enc624j600WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
uint8_t length
Definition: dtls_misc.h:149
void enc624j600ClearBit(NetInterface *interface, uint8_t address, uint16_t mask)
Clear bit field.
uint8_t opcode
Definition: dns_common.h:172
bool_t enc624j600IrqHandler(NetInterface *interface)
ENC624J600 interrupt service routine.
void enc624j600WriteBuffer(NetInterface *interface, uint8_t opcode, const NetBuffer *buffer, size_t offset)
Write SRAM buffer.
int bool_t
Definition: compiler_port.h:49
void enc624j600DumpReg(NetInterface *interface)
Dump registers for debugging purpose.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
uint16_t nextPacket
Next packet in the receive buffer.
uint32_t enc624j600CalcCrc(const void *data, size_t length)
CRC calculation using the polynomial 0x4C11DB7.
uint16_t enc624j600ReadReg(NetInterface *interface, uint8_t address)
Read ENC624J600 register.
void enc624j600WriteReg(NetInterface *interface, uint8_t address, uint16_t data)
Write ENC624J600 register.
void enc624j600DisableIrq(NetInterface *interface)
Disable interrupts.
void enc624j600EnableIrq(NetInterface *interface)
Enable interrupts.
void enc624j600DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
error_t
Error codes.
Definition: error.h:42
ENC624J600 driver context.
#define NetInterface
Definition: net.h:36
uint8_t mask
Definition: web_socket.h:317
error_t enc624j600Init(NetInterface *interface)
ENC624J600 controller initialization.
uint16_t enc624j600ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
error_t enc624j600UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
error_t enc624j600ReceivePacket(NetInterface *interface)
Receive a packet.
void enc624j600UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void enc624j600ReadBuffer(NetInterface *interface, uint8_t opcode, uint8_t *data, size_t length)
Read SRAM buffer.
error_t enc624j600SoftReset(NetInterface *interface)
Reset ENC624J600 controller.
void enc624j600Tick(NetInterface *interface)
ENC624J600 timer handler.
void enc624j600SetBit(NetInterface *interface, uint8_t address, uint16_t mask)
Set bit field.
uint8_t * rxBuffer
Receive buffer.
Ipv6Addr address
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
error_t enc624j600SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
const NicDriver enc624j600Driver
ENC624J600 driver.
void enc624j600EventHandler(NetInterface *interface)
ENC624J600 event handler.