enc624j600_driver.h
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1 /**
2  * @file enc624j600_driver.h
3  * @brief ENC624J600/ENC424J600 Ethernet controller
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _ENC624J600_DRIVER_H
30 #define _ENC624J600_DRIVER_H
31 
32 //Receive and transmit buffers
33 #define ENC624J600_TX_BUFFER_START 0x0000
34 #define ENC624J600_TX_BUFFER_STOP 0x17FE
35 #define ENC624J600_RX_BUFFER_START 0x1800
36 #define ENC624J600_RX_BUFFER_STOP 0x5FFE
37 
38 //SPI command set
39 #define ENC624J600_CMD_B0SEL 0xC0 //Bank 0 Select
40 #define ENC624J600_CMD_B1SEL 0xC2 //Bank 1 Select
41 #define ENC624J600_CMD_B2SEL 0xC4 //Bank 2 Select
42 #define ENC624J600_CMD_B3SEL 0xC6 //Bank 3 Select
43 #define ENC624J600_CMD_SETETHRST 0xCA //System Reset
44 #define ENC624J600_CMD_FCDISABLE 0xE0 //Flow Control Disable
45 #define ENC624J600_CMD_FCSINGLE 0xE2 //Flow Control Single
46 #define ENC624J600_CMD_FCMULTIPLE 0xE4 //Flow Control Multiple
47 #define ENC624J600_CMD_FCCLEAR 0xE6 //Flow Control Clear
48 #define ENC624J600_CMD_SETPKTDEC 0xCC //Decrement Packet Counter
49 #define ENC624J600_CMD_DMASTOP 0xD2 //DMA Stop
50 #define ENC624J600_CMD_DMACKSUM 0xD8 //DMA Start Checksum
51 #define ENC624J600_CMD_DMACKSUMS 0xDA //DMA Start Checksum with Seed
52 #define ENC624J600_CMD_DMACOPY 0xDC //DMA Start Copy
53 #define ENC624J600_CMD_DMACOPYS 0xDE //DMA Start Copy and Checksum with Seed
54 #define ENC624J600_CMD_SETTXRTS 0xD4 //Request Packet Transmission
55 #define ENC624J600_CMD_ENABLERX 0xE8 //Enable RX
56 #define ENC624J600_CMD_DISABLERX 0xEA //Disable RX
57 #define ENC624J600_CMD_SETEIE 0xEC //Enable Interrupts
58 #define ENC624J600_CMD_CLREIE 0xEE //Disable Interrupts
59 #define ENC624J600_CMD_RBSEL 0xC8 //Read Bank Select
60 #define ENC624J600_CMD_WGPRDPT 0x60 //Write EGPRDPT
61 #define ENC624J600_CMD_RGPRDPT 0x62 //Read EGPRDPT
62 #define ENC624J600_CMD_WRXRDPT 0x64 //Write ERXRDPT
63 #define ENC624J600_CMD_RRXRDPT 0x66 //Read ERXRDPT
64 #define ENC624J600_CMD_WUDARDPT 0x68 //Write EUDARDPT
65 #define ENC624J600_CMD_RUDARDPT 0x6A //Read EUDARDPT
66 #define ENC624J600_CMD_WGPWRPT 0x6C //Write EGPWRPT
67 #define ENC624J600_CMD_RGPWRPT 0x6E //Read EGPWRPT
68 #define ENC624J600_CMD_WRXWRPT 0x70 //Write ERXWRPT
69 #define ENC624J600_CMD_RRXWRPT 0x72 //Read ERXWRPT
70 #define ENC624J600_CMD_WUDAWRPT 0x74 //Write EUDAWRPT
71 #define ENC624J600_CMD_RUDAWRPT 0x76 //Read EUDAWRPT
72 #define ENC624J600_CMD_RCR 0x00 //Read Control Register
73 #define ENC624J600_CMD_WCR 0x40 //Write Control Register
74 #define ENC624J600_CMD_RCRU 0x20 //Read Control Register Unbanked
75 #define ENC624J600_CMD_WCRU 0x22 //Write Control Register Unbanked
76 #define ENC624J600_CMD_BFS 0x80 //Bit Field Set
77 #define ENC624J600_CMD_BFC 0xA0 //Bit Field Clear
78 #define ENC624J600_CMD_BFSU 0x24 //Bit Field Set Unbanked
79 #define ENC624J600_CMD_BFCU 0x26 //Bit Field Clear Unbanked
80 #define ENC624J600_CMD_RGPDATA 0x28 //Read EGPDATA
81 #define ENC624J600_CMD_WGPDATA 0x2A //Write EGPDATA
82 #define ENC624J600_CMD_RRXDATA 0x2C //Read ERXDATA
83 #define ENC624J600_CMD_WRXDATA 0x2E //Write ERXDATA
84 #define ENC624J600_CMD_RUDADATA 0x30 //Read EUDADATA
85 #define ENC624J600_CMD_WUDADATA 0x32 //Write EUDADATA
86 
87 //ENC624J600 registers
88 #define ENC624J600_REG_ETXST 0x00
89 #define ENC624J600_REG_ETXLEN 0x02
90 #define ENC624J600_REG_ERXST 0x04
91 #define ENC624J600_REG_ERXTAIL 0x06
92 #define ENC624J600_REG_ERXHEAD 0x08
93 #define ENC624J600_REG_EDMAST 0x0A
94 #define ENC624J600_REG_EDMALEN 0x0C
95 #define ENC624J600_REG_EDMADST 0x0E
96 #define ENC624J600_REG_EDMACS 0x10
97 #define ENC624J600_REG_ETXSTAT 0x12
98 #define ENC624J600_REG_ETXWIRE 0x14
99 #define ENC624J600_REG_EUDAST 0x16
100 #define ENC624J600_REG_EUDAND 0x18
101 #define ENC624J600_REG_ESTAT 0x1A
102 #define ENC624J600_REG_EIR 0x1C
103 #define ENC624J600_REG_ECON1 0x1E
104 #define ENC624J600_REG_EHT1 0x20
105 #define ENC624J600_REG_EHT2 0x22
106 #define ENC624J600_REG_EHT3 0x24
107 #define ENC624J600_REG_EHT4 0x26
108 #define ENC624J600_REG_EPMM1 0x28
109 #define ENC624J600_REG_EPMM2 0x2A
110 #define ENC624J600_REG_EPMM3 0x2C
111 #define ENC624J600_REG_EPMM4 0x2E
112 #define ENC624J600_REG_EPMCS 0x30
113 #define ENC624J600_REG_EPMO 0x32
114 #define ENC624J600_REG_ERXFCON 0x34
115 #define ENC624J600_REG_MACON1 0x40
116 #define ENC624J600_REG_MACON2 0x42
117 #define ENC624J600_REG_MABBIPG 0x44
118 #define ENC624J600_REG_MAIPG 0x46
119 #define ENC624J600_REG_MACLCON 0x48
120 #define ENC624J600_REG_MAMXFL 0x4A
121 #define ENC624J600_REG_MICMD 0x52
122 #define ENC624J600_REG_MIREGADR 0x54
123 #define ENC624J600_REG_MAADR3 0x60
124 #define ENC624J600_REG_MAADR2 0x62
125 #define ENC624J600_REG_MAADR1 0x64
126 #define ENC624J600_REG_MIWR 0x66
127 #define ENC624J600_REG_MIRD 0x68
128 #define ENC624J600_REG_MISTAT 0x6A
129 #define ENC624J600_REG_EPAUS 0x6C
130 #define ENC624J600_REG_ECON2 0x6E
131 #define ENC624J600_REG_ERXWM 0x70
132 #define ENC624J600_REG_EIE 0x72
133 #define ENC624J600_REG_EIDLED 0x74
134 #define ENC624J600_REG_EGPDATA 0x80
135 #define ENC624J600_REG_ERXDATA 0x82
136 #define ENC624J600_REG_EUDADATA 0x84
137 #define ENC624J600_REG_EGPRDPT 0x86
138 #define ENC624J600_REG_EGPWRPT 0x88
139 #define ENC624J600_REG_ERXRDPT 0x8A
140 #define ENC624J600_REG_ERXWRPT 0x8C
141 #define ENC624J600_REG_EUDARDPT 0x8E
142 #define ENC624J600_REG_EUDAWRPT 0x90
143 
144 //ENC624J600 PHY registers
145 #define ENC624J600_PHY_REG_PHCON1 0x00
146 #define ENC624J600_PHY_REG_PHSTAT1 0x01
147 #define ENC624J600_PHY_REG_PHANA 0x04
148 #define ENC624J600_PHY_REG_PHANLPA 0x05
149 #define ENC624J600_PHY_REG_PHANE 0x06
150 #define ENC624J600_PHY_REG_PHCON2 0x11
151 #define ENC624J600_PHY_REG_PHSTAT2 0x1B
152 #define ENC624J600_PHY_REG_PHSTAT3 0x1F
153 
154 //ESTAT register
155 #define ESTAT_INT 0x8000
156 #define ESTAT_FCIDLE 0x4000
157 #define ESTAT_RXBUSY 0x2000
158 #define ESTAT_CLKRDY 0x1000
159 #define ESTAT_R11 0x0800
160 #define ESTAT_PHYDPX 0x0400
161 #define ESTAT_R9 0x0200
162 #define ESTAT_PHYLNK 0x0100
163 #define ESTAT_PKTCNT 0x00FF
164 
165 //EIR register
166 #define EIR_CRYPTEN 0x8000
167 #define EIR_MODEXIF 0x4000
168 #define EIR_HASHIF 0x2000
169 #define EIR_AESIF 0x1000
170 #define EIR_LINKIF 0x0800
171 #define EIR_R10 0x0400
172 #define EIR_R9 0x0200
173 #define EIR_R8 0x0100
174 #define EIR_R7 0x0080
175 #define EIR_PKTIF 0x0040
176 #define EIR_DMAIF 0x0020
177 #define EIR_R4 0x0010
178 #define EIR_TXIF 0x0008
179 #define EIR_TXABTIF 0x0004
180 #define EIR_RXABTIF 0x0002
181 #define EIR_PCFULIF 0x0001
182 
183 //ECON1 register
184 #define ECON1_MODEXST 0x8000
185 #define ECON1_HASHEN 0x4000
186 #define ECON1_HASHOP 0x2000
187 #define ECON1_HASHLST 0x1000
188 #define ECON1_AESST 0x0800
189 #define ECON1_AESOP1 0x0400
190 #define ECON1_AESOP0 0x0200
191 #define ECON1_PKTDEC 0x0100
192 #define ECON1_FCOP1 0x0080
193 #define ECON1_FCOP0 0x0040
194 #define ECON1_DMAST 0x0020
195 #define ECON1_DMACPY 0x0010
196 #define ECON1_DMACSSD 0x0008
197 #define ECON1_DMANOCS 0x0004
198 #define ECON1_TXRTS 0x0002
199 #define ECON1_RXEN 0x0001
200 
201 //ETXSTAT register
202 #define ETXSTAT_R12 0x1000
203 #define ETXSTAT_R11 0x0800
204 #define ETXSTAT_LATECOL 0x0400
205 #define ETXSTAT_MAXCOL 0x0200
206 #define ETXSTAT_EXDEFER 0x0100
207 #define ETXSTAT_DEFER 0x0080
208 #define ETXSTAT_R6 0x0040
209 #define ETXSTAT_R5 0x0020
210 #define ETXSTAT_CRCBAD 0x0010
211 #define ETXSTAT_COLCNT 0x000F
212 
213 //ERXFCON register
214 #define ERXFCON_HTEN 0x8000
215 #define ERXFCON_MPEN 0x4000
216 #define ERXFCON_NOTPM 0x1000
217 #define ERXFCON_PMEN3 0x0800
218 #define ERXFCON_PMEN2 0x0400
219 #define ERXFCON_PMEN1 0x0200
220 #define ERXFCON_PMEN0 0x0100
221 #define ERXFCON_CRCEEN 0x0080
222 #define ERXFCON_CRCEN 0x0040
223 #define ERXFCON_RUNTEEN 0x0020
224 #define ERXFCON_RUNTEN 0x0010
225 #define ERXFCON_UCEN 0x0008
226 #define ERXFCON_NOTMEEN 0x0004
227 #define ERXFCON_MCEN 0x0002
228 #define ERXFCON_BCEN 0x0001
229 
230 //MACON1 register
231 #define MACON1_R15 0x8000
232 #define MACON1_R14 0x4000
233 #define MACON1_R11 0x0800
234 #define MACON1_R10 0x0400
235 #define MACON1_R9 0x0200
236 #define MACON1_R8 0x0100
237 #define MACON1_LOOPBK 0x0010
238 #define MACON1_R3 0x0008
239 #define MACON1_RXPAUS 0x0004
240 #define MACON1_PASSALL 0x0002
241 #define MACON1_R0 0x0001
242 
243 //MACON2 register
244 #define MACON2_DEFER 0x4000
245 #define MACON2_BPEN 0x2000
246 #define MACON2_NOBKOFF 0x1000
247 #define MACON2_R9 0x0200
248 #define MACON2_R8 0x0100
249 #define MACON2_PADCFG2 0x0080
250 #define MACON2_PADCFG1 0x0040
251 #define MACON2_PADCFG0 0x0020
252 #define MACON2_TXCRCEN 0x0010
253 #define MACON2_PHDREN 0x0008
254 #define MACON2_HFRMEN 0x0004
255 #define MACON2_R1 0x0002
256 #define MACON2_FULDPX 0x0001
257 
258 //MABBIPG register
259 #define MABBIPG_BBIPG 0x007F
260 
261 //MAIPG register
262 #define MAIPG_R14 0x4000
263 #define MAIPG_R13 0x2000
264 #define MAIPG_R12 0x1000
265 #define MAIPG_R11 0x0800
266 #define MAIPG_R10 0x0400
267 #define MAIPG_R9 0x0200
268 #define MAIPG_R8 0x0100
269 #define MAIPG_IPG 0x007F
270 
271 //MACLCON register
272 #define MACLCON_R13 0x2000
273 #define MACLCON_R12 0x1000
274 #define MACLCON_R11 0x0800
275 #define MACLCON_R10 0x0400
276 #define MACLCON_R9 0x0200
277 #define MACLCON_R8 0x0100
278 #define MACLCON_MAXRET 0x000F
279 
280 //MICMD register
281 #define MICMD_MIISCAN 0x0002
282 #define MICMD_MIIRD 0x0001
283 
284 //MIREGADR register
285 #define MIREGADR_R12 0x1000
286 #define MIREGADR_R11 0x0800
287 #define MIREGADR_R10 0x0400
288 #define MIREGADR_R9 0x0200
289 #define MIREGADR_R8 0x0100
290 #define MIREGADR_PHREG 0x001F
291 
292 //MISTAT register
293 #define MISTAT_R3 0x0008
294 #define MISTAT_NVALID 0x0004
295 #define MISTAT_SCAN 0x0002
296 #define MISTAT_BUSY 0x0001
297 
298 //ECON2 register
299 #define ECON2_ETHEN 0x8000
300 #define ECON2_STRCH 0x4000
301 #define ECON2_TXMAC 0x2000
302 #define ECON2_SHA1MD5 0x1000
303 #define ECON2_COCON3 0x0800
304 #define ECON2_COCON2 0x0400
305 #define ECON2_COCON1 0x0200
306 #define ECON2_COCON0 0x0100
307 #define ECON2_AUTOFC 0x0080
308 #define ECON2_TXRST 0x0040
309 #define ECON2_RXRST 0x0020
310 #define ECON2_ETHRST 0x0010
311 #define ECON2_MODLEN1 0x0008
312 #define ECON2_MODLEN0 0x0004
313 #define ECON2_AESLEN1 0x0002
314 #define ECON2_AESLEN0 0x0001
315 
316 //ERXWM register
317 #define ERXWM_RXFWM 0xFF00
318 #define ERXWM_RXEWM 0x00FF
319 
320 //EIE register
321 #define EIE_INTIE 0x8000
322 #define EIE_MODEXIE 0x4000
323 #define EIE_HASHIE 0x2000
324 #define EIE_AESIE 0x1000
325 #define EIE_LINKIE 0x0800
326 #define EIE_R10 0x0400
327 #define EIE_R9 0x0200
328 #define EIE_R8 0x0100
329 #define EIE_R7 0x0080
330 #define EIE_PKTIE 0x0040
331 #define EIE_DMAIE 0x0020
332 #define EIE_R4 0x0010
333 #define EIE_TXIE 0x0008
334 #define EIE_TXABTIE 0x0004
335 #define EIE_RXABTIE 0x0002
336 #define EIE_PCFULIE 0x0001
337 
338 //EIDLED register
339 #define EIDLED_LACFG3 0x8000
340 #define EIDLED_LACFG2 0x4000
341 #define EIDLED_LACFG1 0x2000
342 #define EIDLED_LACFG0 0x1000
343 #define EIDLED_LBCFG3 0x0800
344 #define EIDLED_LBCFG2 0x0400
345 #define EIDLED_LBCFG1 0x0200
346 #define EIDLED_LBCFG0 0x0100
347 #define EIDLED_DEVID 0x00FF
348 
349 //PHCON1 register
350 #define PHCON1_PRST 0x8000
351 #define PHCON1_PLOOPBK 0x4000
352 #define PHCON1_SPD100 0x2000
353 #define PHCON1_ANEN 0x1000
354 #define PHCON1_PSLEEP 0x0800
355 #define PHCON1_RENEG 0x0200
356 #define PHCON1_PFULDPX 0x0100
357 
358 //PHSTAT1 register
359 #define PHSTAT1_FULL100 0x4000
360 #define PHSTAT1_HALF100 0x2000
361 #define PHSTAT1_FULL10 0x1000
362 #define PHSTAT1_HALF10 0x0800
363 #define PHSTAT1_ANDONE 0x0020
364 #define PHSTAT1_LRFAULT 0x0010
365 #define PHSTAT1_ANABLE 0x0008
366 #define PHSTAT1_LLSTAT 0x0004
367 #define PHSTAT1_EXTREGS 0x0001
368 
369 //PHANA register
370 #define PHANA_ADNP 0x8000
371 #define PHANA_ADFAULT 0x2000
372 #define PHANA_ADPAUS1 0x0800
373 #define PHANA_ADPAUS0 0x0400
374 #define PHANA_AD100FD 0x0100
375 #define PHANA_AD100 0x0080
376 #define PHANA_AD10FD 0x0040
377 #define PHANA_AD10 0x0020
378 #define PHANA_ADIEEE4 0x0010
379 #define PHANA_ADIEEE3 0x0008
380 #define PHANA_ADIEEE2 0x0004
381 #define PHANA_ADIEEE1 0x0002
382 #define PHANA_ADIEEE0 0x0001
383 
384 //PHANLPA register
385 #define PHANLPA_LPNP 0x8000
386 #define PHANLPA_LPACK 0x4000
387 #define PHANLPA_LPFAULT 0x2000
388 #define PHANLPA_LPPAUS1 0x0800
389 #define PHANLPA_LPPAUS0 0x0400
390 #define PHANLPA_LP100T4 0x0200
391 #define PHANLPA_LP100FD 0x0100
392 #define PHANLPA_LP100 0x0080
393 #define PHANLPA_LP10FD 0x0040
394 #define PHANLPA_LP10 0x0020
395 #define PHANLPA_LPIEEE 0x001F
396 #define PHANLPA_LPIEEE4 0x0010
397 #define PHANLPA_LPIEEE3 0x0008
398 #define PHANLPA_LPIEEE2 0x0004
399 #define PHANLPA_LPIEEE1 0x0002
400 #define PHANLPA_LPIEEE0 0x0001
401 
402 //PHANE register
403 #define PHANE_PDFLT 0x0010
404 #define PHANE_LPARCD 0x0002
405 #define PHANE_LPANABL 0x0001
406 
407 //PHCON2 register
408 #define PHCON2_EDPWRDN 0x2000
409 #define PHCON2_EDTHRES 0x0800
410 #define PHCON2_FRCLNK 0x0004
411 #define PHCON2_EDSTAT 0x0002
412 
413 //PHSTAT2 register
414 #define PHSTAT2_PLRITY 0x0010
415 
416 //PHSTAT3 register
417 #define PHSTAT3_SPDDPX2 0x0010
418 #define PHSTAT3_SPDDPX1 0x0008
419 #define PHSTAT3_SPDDPX0 0x0004
420 
421 //Receive status vector
422 #define RSV_UNICAST_FILTER 0x00100000
423 #define RSV_PATTERN_MATCH_FILTER 0x00080000
424 #define RSV_MAGIC_PACKET_FILTER 0x00040000
425 #define RSV_HASH_FILTER 0x00020000
426 #define RSV_NOT_ME_FILTER 0x00010000
427 #define RSV_RUNT_FILTER 0x00008000
428 #define RSV_VLAN_TYPE 0x00004000
429 #define RSV_UNKNOWN_OPCODE 0x00002000
430 #define RSV_PAUSE_CONTROL_FRAME 0x00001000
431 #define RSV_CONTROL_FRAME 0x00000800
432 #define RSV_DRIBBLE_NIBBLE 0x00000400
433 #define RSV_BROADCAST_PACKET 0x00000200
434 #define RSV_MULTICAST_PACKET 0x00000100
435 #define RSV_RECEIVED_OK 0x00000080
436 #define RSV_LENGTH_OUT_OF_RANGE 0x00000040
437 #define RSV_LENGTH_CHECK_ERROR 0x00000020
438 #define RSV_CRC_ERROR 0x00000010
439 #define RSV_CARRIER_EVENT 0x00000004
440 #define RSV_PACKET_IGNORED 0x00000001
441 
442 //C++ guard
443 #ifdef __cplusplus
444  extern "C" {
445 #endif
446 
447 
448 /**
449  * @brief ENC624J600 driver context
450  **/
451 
452 typedef struct
453 {
454  uint16_t nextPacket; ///<Next packet in the receive buffer
455  uint8_t *rxBuffer; ///<Receive buffer
457 
458 
459 //ENC624J600 driver
460 extern const NicDriver enc624j600Driver;
461 
462 //ENC624J600 related functions
464 
465 void enc624j600Tick(NetInterface *interface);
466 
467 void enc624j600EnableIrq(NetInterface *interface);
468 void enc624j600DisableIrq(NetInterface *interface);
470 void enc624j600EventHandler(NetInterface *interface);
471 
473  const NetBuffer *buffer, size_t offset);
474 
476 
478 void enc624j600UpdateMacConfig(NetInterface *interface);
479 
481 
482 void enc624j600WriteReg(NetInterface *interface, uint8_t address, uint16_t data);
483 uint16_t enc624j600ReadReg(NetInterface *interface, uint8_t address);
484 
485 void enc624j600WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
486 uint16_t enc624j600ReadPhyReg(NetInterface *interface, uint8_t address);
487 
488 void enc624j600WriteBuffer(NetInterface *interface,
489  uint8_t opcode, const NetBuffer *buffer, size_t offset);
490 
491 void enc624j600ReadBuffer(NetInterface *interface,
492  uint8_t opcode, uint8_t *data, size_t length);
493 
494 void enc624j600SetBit(NetInterface *interface, uint8_t address, uint16_t mask);
495 void enc624j600ClearBit(NetInterface *interface, uint8_t address, uint16_t mask);
496 
497 uint32_t enc624j600CalcCrc(const void *data, size_t length);
498 
499 void enc624j600DumpReg(NetInterface *interface);
500 void enc624j600DumpPhyReg(NetInterface *interface);
501 
502 //C++ guard
503 #ifdef __cplusplus
504  }
505 #endif
506 
507 #endif
void enc624j600DumpReg(NetInterface *interface)
Dump registers for debugging purpose.
error_t enc624j600SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
void enc624j600ReadBuffer(NetInterface *interface, uint8_t opcode, uint8_t *data, size_t length)
Read SRAM buffer.
void enc624j600SetBit(NetInterface *interface, uint8_t address, uint16_t mask)
Set bit field.
error_t enc624j600Init(NetInterface *interface)
ENC624J600 controller initialization.
void enc624j600WriteReg(NetInterface *interface, uint8_t address, uint16_t data)
Write ENC624J600 register.
ENC624J600 driver context.
void enc624j600ClearBit(NetInterface *interface, uint8_t address, uint16_t mask)
Clear bit field.
uint16_t enc624j600ReadReg(NetInterface *interface, uint8_t address)
Read ENC624J600 register.
uint16_t enc624j600ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
error_t enc624j600ReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t * rxBuffer
Receive buffer.
uint8_t mask
Definition: web_socket.h:315
void enc624j600DisableIrq(NetInterface *interface)
Disable interrupts.
uint32_t enc624j600CalcCrc(const void *data, size_t length)
CRC calculation using the polynomial 0x4C11DB7.
error_t enc624j600UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void enc624j600Tick(NetInterface *interface)
ENC624J600 timer handler.
NIC driver.
Definition: nic.h:161
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:86
void enc624j600EnableIrq(NetInterface *interface)
Enable interrupts.
error_t enc624j600SoftReset(NetInterface *interface)
Reset ENC624J600 controller.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
void enc624j600WriteBuffer(NetInterface *interface, uint8_t opcode, const NetBuffer *buffer, size_t offset)
Write SRAM buffer.
void enc624j600EventHandler(NetInterface *interface)
ENC624J600 event handler.
void enc624j600DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint16_t nextPacket
Next packet in the receive buffer.
void enc624j600UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void enc624j600WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
uint8_t length
Definition: dtls_misc.h:140
bool_t enc624j600IrqHandler(NetInterface *interface)
ENC624J600 interrupt service routine.
uint16_t opcode
Definition: dns_common.h:170
int bool_t
Definition: compiler_port.h:47
const NicDriver enc624j600Driver
ENC624J600 driver.