32 #define TRACE_LEVEL CRYPTO_TRACE_LEVEL
35 #include "hal/sha_types.h"
36 #include "soc/hwcrypto_reg.h"
37 #include "soc/dport_access.h"
38 #include "esp_private/periph_ctrl.h"
46 #if (ESP32_CRYPTO_HASH_SUPPORT == ENABLED)
56 periph_module_enable(PERIPH_SHA_MODULE);
73 DPORT_REG_WRITE(SHA_TEXT_BASE, temp);
75 DPORT_REG_WRITE(SHA_TEXT_BASE + 4, temp);
77 DPORT_REG_WRITE(SHA_TEXT_BASE + 8, temp);
79 DPORT_REG_WRITE(SHA_TEXT_BASE + 12, temp);
81 DPORT_REG_WRITE(SHA_TEXT_BASE + 16, temp);
83 DPORT_REG_WRITE(SHA_TEXT_BASE + 20, temp);
85 DPORT_REG_WRITE(SHA_TEXT_BASE + 24, temp);
87 DPORT_REG_WRITE(SHA_TEXT_BASE + 28, temp);
89 DPORT_REG_WRITE(SHA_TEXT_BASE + 32, temp);
91 DPORT_REG_WRITE(SHA_TEXT_BASE + 36, temp);
93 DPORT_REG_WRITE(SHA_TEXT_BASE + 40, temp);
95 DPORT_REG_WRITE(SHA_TEXT_BASE + 44, temp);
97 DPORT_REG_WRITE(SHA_TEXT_BASE + 48, temp);
99 DPORT_REG_WRITE(SHA_TEXT_BASE + 52, temp);
101 DPORT_REG_WRITE(SHA_TEXT_BASE + 56, temp);
103 DPORT_REG_WRITE(SHA_TEXT_BASE + 60, temp);
106 if(algo == SHA2_384 || algo == SHA2_512)
109 DPORT_REG_WRITE(SHA_TEXT_BASE + 64, temp);
111 DPORT_REG_WRITE(SHA_TEXT_BASE + 68, temp);
113 DPORT_REG_WRITE(SHA_TEXT_BASE + 72, temp);
115 DPORT_REG_WRITE(SHA_TEXT_BASE + 76, temp);
117 DPORT_REG_WRITE(SHA_TEXT_BASE + 80, temp);
119 DPORT_REG_WRITE(SHA_TEXT_BASE + 84, temp);
121 DPORT_REG_WRITE(SHA_TEXT_BASE + 88, temp);
123 DPORT_REG_WRITE(SHA_TEXT_BASE + 92, temp);
125 DPORT_REG_WRITE(SHA_TEXT_BASE + 96, temp);
127 DPORT_REG_WRITE(SHA_TEXT_BASE + 100, temp);
129 DPORT_REG_WRITE(SHA_TEXT_BASE + 104, temp);
131 DPORT_REG_WRITE(SHA_TEXT_BASE + 108, temp);
133 DPORT_REG_WRITE(SHA_TEXT_BASE + 112, temp);
135 DPORT_REG_WRITE(SHA_TEXT_BASE + 116, temp);
137 DPORT_REG_WRITE(SHA_TEXT_BASE + 120, temp);
139 DPORT_REG_WRITE(SHA_TEXT_BASE + 124, temp);
149 DPORT_REG_WRITE(SHA_1_START_REG, 1);
153 DPORT_REG_WRITE(SHA_1_CONTINUE_REG, 1);
157 while(DPORT_REG_READ(SHA_1_BUSY_REG) != 0)
161 else if(algo == SHA2_256)
166 DPORT_REG_WRITE(SHA_256_START_REG, 1);
170 DPORT_REG_WRITE(SHA_256_CONTINUE_REG, 1);
174 while(DPORT_REG_READ(SHA_256_BUSY_REG) != 0)
178 else if(algo == SHA2_384)
183 DPORT_REG_WRITE(SHA_384_START_REG, 1);
187 DPORT_REG_WRITE(SHA_384_CONTINUE_REG, 1);
191 while(DPORT_REG_READ(SHA_384_BUSY_REG) != 0)
200 DPORT_REG_WRITE(SHA_512_START_REG, 1);
204 DPORT_REG_WRITE(SHA_512_CONTINUE_REG, 1);
208 while(DPORT_REG_READ(SHA_512_BUSY_REG) != 0)
218 #if (SHA1_SUPPORT == ENABLED)
271 DPORT_REG_WRITE(SHA_1_LOAD_REG, 1);
274 while(DPORT_REG_READ(SHA_1_BUSY_REG) != 0)
279 DPORT_INTERRUPT_DISABLE();
280 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE);
282 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 4);
284 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 8);
286 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 12);
288 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 16);
290 DPORT_INTERRUPT_RESTORE();
300 #if (SHA256_SUPPORT == ENABLED)
353 DPORT_REG_WRITE(SHA_256_LOAD_REG, 1);
356 while(DPORT_REG_READ(SHA_256_BUSY_REG) != 0)
361 DPORT_INTERRUPT_DISABLE();
362 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE);
364 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 4);
366 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 8);
368 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 12);
370 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 16);
372 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 20);
374 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 24);
376 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 28);
378 DPORT_INTERRUPT_RESTORE();
388 #if (SHA384_SUPPORT == ENABLED)
441 DPORT_REG_WRITE(SHA_384_LOAD_REG, 1);
444 while(DPORT_REG_READ(SHA_384_BUSY_REG) != 0)
449 DPORT_INTERRUPT_DISABLE();
450 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE);
452 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 4);
454 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 8);
456 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 12);
458 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 16);
460 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 20);
462 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 24);
464 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 28);
466 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 32);
468 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 36);
470 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 40);
472 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 44);
474 DPORT_INTERRUPT_RESTORE();
484 #if (SHA512_SUPPORT == ENABLED)
537 DPORT_REG_WRITE(SHA_512_LOAD_REG, 1);
540 while(DPORT_REG_READ(SHA_512_BUSY_REG) != 0)
545 DPORT_INTERRUPT_DISABLE();
546 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE);
548 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 4);
550 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 8);
552 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 12);
554 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 16);
556 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 20);
558 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 24);
560 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 28);
562 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 32);
564 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 36);
566 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 40);
568 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 44);
570 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 48);
572 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 52);
574 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 56);
576 temp = DPORT_SEQUENCE_REG_READ(SHA_TEXT_BASE + 60);
578 DPORT_INTERRUPT_RESTORE();