32 #define TRACE_LEVEL CRYPTO_TRACE_LEVEL
35 #include "soc/hwcrypto_reg.h"
36 #include "soc/dport_access.h"
37 #include "esp_private/periph_ctrl.h"
46 #if (ESP32_CRYPTO_PKC_SUPPORT == ENABLED)
56 periph_module_enable(PERIPH_RSA_MODULE);
61 while(DPORT_REG_READ(RSA_CLEAN_REG) == 0)
67 #if (MPI_SUPPORT == ENABLED)
91 if(aLen <= 64 && bLen <= 64)
103 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
105 DPORT_REG_WRITE(RSA_MULT_MODE_REG, (
n / 8) - 1 + 8);
108 for(i = 0; i <
n; i++)
112 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
a->data[i]);
116 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4, 0);
122 for(i = 0; i <
n; i++)
124 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + i * 4, 0);
129 for(i = 0; i <
n; i++)
133 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4,
b->data[i]);
137 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4, 0);
142 DPORT_REG_WRITE(RSA_MULT_START_REG, 1);
145 while(DPORT_REG_READ(RSA_INTERRUPT_REG) == 0)
150 r->sign = (
a->sign ==
b->sign) ? 1 : -1;
159 DPORT_INTERRUPT_DISABLE();
162 for(i = 0; i <
r->size; i++)
166 r->data[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
175 DPORT_INTERRUPT_RESTORE();
179 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
225 if(modLen > 0 && modLen <= 128 && expLen > 0 && expLen <= 128)
228 n =
MAX(modLen, expLen);
257 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
259 DPORT_REG_WRITE(RSA_MODEXP_MODE_REG, (
n / 16) - 1);
262 for(i = 0; i <
n; i++)
266 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
t.data[i]);
270 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4, 0);
275 for(i = 0; i <
n; i++)
279 DPORT_REG_WRITE(RSA_MEM_Y_BLOCK_BASE + i * 4, e->
data[i]);
283 DPORT_REG_WRITE(RSA_MEM_Y_BLOCK_BASE + i * 4, 0);
288 for(i = 0; i <
n; i++)
292 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4,
p->data[i]);
296 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, 0);
301 for(i = 0; i <
n; i++)
305 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, r2.
data[i]);
309 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0);
314 for(
m =
p->data[0], i = 0; i < 4; i++)
316 m =
m * (2U -
m *
p->data[0]);
323 DPORT_REG_WRITE(RSA_M_DASH_REG,
m);
326 DPORT_REG_WRITE(RSA_MODEXP_START_REG, 1);
329 while(DPORT_REG_READ(RSA_INTERRUPT_REG) == 0)
340 DPORT_INTERRUPT_DISABLE();
343 for(i = 0; i <
r->size; i++)
347 r->data[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
356 DPORT_INTERRUPT_RESTORE();
360 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
381 #if (EC_SUPPORT == ENABLED)
406 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
408 DPORT_REG_WRITE(RSA_MULT_MODE_REG, (
m / 8) - 1 + 8);
411 for(i = 0; i <
m; i++)
415 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
a[i]);
419 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4, 0);
425 for(i = 0; i <
m; i++)
427 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + i * 4, 0);
432 for(i = 0; i <
m; i++)
436 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
m + i) * 4,
b[i]);
440 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
m + i) * 4, 0);
445 DPORT_REG_WRITE(RSA_MULT_START_REG, 1);
448 while(DPORT_REG_READ(RSA_INTERRUPT_REG) == 0)
453 DPORT_INTERRUPT_DISABLE();
459 for(i = 0; i <
n; i++)
461 rl[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
469 for(i = 0; i <
n; i++)
471 rh[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4);
476 DPORT_INTERRUPT_RESTORE();
478 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);