32 #define TRACE_LEVEL CRYPTO_TRACE_LEVEL
35 #include "soc/hwcrypto_reg.h"
36 #include "soc/dport_access.h"
37 #include "esp_private/periph_ctrl.h"
46 #if (ESP32_CRYPTO_PKC_SUPPORT == ENABLED)
56 periph_module_enable(PERIPH_RSA_MODULE);
61 while(DPORT_REG_READ(RSA_CLEAN_REG) == 0)
89 if(aLen <= 64 && bLen <= 64)
101 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
103 DPORT_REG_WRITE(RSA_MULT_MODE_REG, (
n / 8) - 1 + 8);
106 for(i = 0; i <
n; i++)
110 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
a->data[i]);
114 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4, 0);
120 for(i = 0; i <
n; i++)
122 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + i * 4, 0);
127 for(i = 0; i <
n; i++)
131 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4,
b->data[i]);
135 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4, 0);
140 DPORT_REG_WRITE(RSA_MULT_START_REG, 1);
143 while(DPORT_REG_READ(RSA_INTERRUPT_REG) == 0)
148 r->sign = (
a->sign ==
b->sign) ? 1 : -1;
157 DPORT_INTERRUPT_DISABLE();
160 for(i = 0; i <
r->size; i++)
164 r->data[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
173 DPORT_INTERRUPT_RESTORE();
177 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
223 if(modLen > 0 && modLen <= 128 && expLen > 0 && expLen <= 128)
226 n =
MAX(modLen, expLen);
255 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
257 DPORT_REG_WRITE(RSA_MODEXP_MODE_REG, (
n / 16) - 1);
260 for(i = 0; i <
n; i++)
264 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
t.data[i]);
268 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4, 0);
273 for(i = 0; i <
n; i++)
277 DPORT_REG_WRITE(RSA_MEM_Y_BLOCK_BASE + i * 4, e->
data[i]);
281 DPORT_REG_WRITE(RSA_MEM_Y_BLOCK_BASE + i * 4, 0);
286 for(i = 0; i <
n; i++)
290 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4,
p->data[i]);
294 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, 0);
299 for(i = 0; i <
n; i++)
303 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, r2.
data[i]);
307 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0);
312 for(
m = 2 -
p->data[0], i = 0; i < 4; i++)
314 m =
m * (2 -
m *
p->data[0]);
321 DPORT_REG_WRITE(RSA_M_DASH_REG,
m);
324 DPORT_REG_WRITE(RSA_MODEXP_START_REG, 1);
327 while(DPORT_REG_READ(RSA_INTERRUPT_REG) == 0)
338 DPORT_INTERRUPT_DISABLE();
341 for(i = 0; i <
r->size; i++)
345 r->data[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
354 DPORT_INTERRUPT_RESTORE();
358 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
379 #if (X25519_SUPPORT == ENABLED || ED25519_SUPPORT == ENABLED)
398 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
400 DPORT_REG_WRITE(RSA_MULT_MODE_REG, 8);
403 for(i = 0; i < 8; i++)
405 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
a[i]);
410 for(i = 0; i < 8; i++)
412 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + i * 4, 0);
417 for(i = 0; i < 8; i++)
419 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + 32 + i * 4,
b[i]);
423 DPORT_REG_WRITE(RSA_MULT_START_REG, 1);
426 while(DPORT_REG_READ(RSA_INTERRUPT_REG) == 0)
431 DPORT_INTERRUPT_DISABLE();
434 for(i = 0; i < 16; i++)
436 u[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
440 DPORT_INTERRUPT_RESTORE();
442 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
448 temp = (
u[7] >> 31) * 19;
453 for(i = 0; i < 8; i++)
456 temp += (uint64_t)
u[i + 8] * 38;
457 u[i] = temp & 0xFFFFFFFF;
464 temp += (
u[7] >> 31) * 19;
469 for(i = 0; i < 8; i++)
472 u[i] = temp & 0xFFFFFFFF;
481 #if (X448_SUPPORT == ENABLED || ED448_SUPPORT == ENABLED)
498 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
500 DPORT_REG_WRITE(RSA_MULT_MODE_REG, 0);
503 for(i = 0; i < 14; i++)
505 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
a[i]);
509 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + 56, 0);
510 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + 60, 0);
513 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE, 0xFFFFFFFF);
514 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 4, 0xFFFFFFFF);
515 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 8, 0xFFFFFFFF);
516 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 12, 0xFFFFFFFF);
517 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 16, 0xFFFFFFFF);
518 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 20, 0xFFFFFFFF);
519 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 24, 0xFFFFFFFF);
520 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 28, 0xFFFFFFFE);
521 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 32, 0xFFFFFFFF);
522 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 36, 0xFFFFFFFF);
523 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 40, 0xFFFFFFFF);
524 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 44, 0xFFFFFFFF);
525 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 48, 0xFFFFFFFF);
526 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 52, 0xFFFFFFFF);
527 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 56, 0x00000000);
528 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + 60, 0x00000000);
531 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE, 0x00000000);
532 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 4, 0x00000000);
533 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 8, 0x00000000);
534 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 12, 0x00000000);
535 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 16, 0x00000002);
536 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 20, 0x00000000);
537 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 24, 0x00000000);
538 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 28, 0x00000000);
539 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 32, 0x00000000);
540 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 36, 0x00000000);
541 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 40, 0x00000000);
542 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 44, 0x00000003);
543 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 48, 0x00000000);
544 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 52, 0x00000000);
545 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 56, 0x00000000);
546 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + 60, 0x00000000);
549 DPORT_REG_WRITE(RSA_M_DASH_REG, 0x00000001);
551 DPORT_REG_WRITE(RSA_MULT_START_REG, 1);
554 while(DPORT_REG_READ(RSA_INTERRUPT_REG) == 0)
559 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);
562 for(i = 0; i < 14; i++)
564 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
b[i]);
568 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + 56, 0);
569 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + 60, 0);
572 DPORT_REG_WRITE(RSA_MULT_START_REG, 1);
575 while(DPORT_REG_READ(RSA_INTERRUPT_REG) == 0)
580 DPORT_INTERRUPT_DISABLE();
583 for(i = 0; i < 14; i++)
585 r[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
589 DPORT_INTERRUPT_RESTORE();
591 DPORT_REG_WRITE(RSA_INTERRUPT_REG, 1);