32 #define TRACE_LEVEL CRYPTO_TRACE_LEVEL
35 #include "esp_crypto_lock.h"
36 #include "soc/system_reg.h"
37 #include "soc/hwcrypto_reg.h"
38 #include "soc/dport_reg.h"
39 #include "soc/dport_access.h"
40 #include "esp_private/periph_ctrl.h"
49 #if (ESP32_S2_CRYPTO_PKC_SUPPORT == ENABLED)
52 #define SECP224R1_PRIME_M 0xFFFFFFFF
53 #define SECP256K1_PRIME_M 0xD2253531
54 #define SECP256R1_PRIME_M 0x00000001
55 #define SECP384R1_PRIME_M 0x00000001
56 #define SECP521R1_PRIME_M 0x00000001
57 #define BRAINPOOLP256R1_PRIME_M 0xCEFD89B9
58 #define BRAINPOOLP384R1_PRIME_M 0xEA9EC825
59 #define BRAINPOOLP512R1_PRIME_M 0x7D89EFC5
60 #define FRP256V1_PRIME_M 0x164E1155
61 #define SM2_PRIME_M 0x00000001
62 #define CURVE25519_PRIME_M 0x286BCA1B
63 #define CURVE448_PRIME_M 0x00000001
66 #define SECP224R1_ORDER_M 0x6A1FC2EB
67 #define SECP256K1_ORDER_M 0x5588B13F
68 #define SECP256R1_ORDER_M 0xEE00BC4F
69 #define SECP384R1_ORDER_M 0xE88FDC45
70 #define SECP521R1_ORDER_M 0x79A995C7
71 #define BRAINPOOLP256R1_ORDER_M 0xCBB40EE9
72 #define BRAINPOOLP384R1_ORDER_M 0x5CB5BB93
73 #define BRAINPOOLP512R1_ORDER_M 0x0F1B7027
74 #define FRP256V1_ORDER_M 0x4FFF51DF
75 #define SM2_ORDER_M 0x72350975
78 static const uint32_t SECP224R1_PRIME_R2[7] =
80 0x00000001, 0x00000000, 0x00000000, 0xFFFFFFFE, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000
84 static const uint32_t SECP224R1_ORDER_R2[7] =
86 0x3AD01289, 0x6BDAAE6C, 0x97A54552, 0x6AD09D91, 0xB1E97961, 0x1822BC47, 0xD4BAA4CF
90 static const uint32_t SECP256K1_PRIME_R2[8] =
92 0x000E90A1, 0x000007A2, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
96 static const uint32_t SECP256K1_ORDER_R2[8] =
98 0x67D7D140, 0x896CF214, 0x0E7CF878, 0x741496C2, 0x5BCD07C6, 0xE697F5E4, 0x81C69BC5, 0x9D671CD5
102 static const uint32_t SECP256R1_PRIME_R2[8] =
104 0x00000003, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFB, 0xFFFFFFFE, 0xFFFFFFFF, 0xFFFFFFFD, 0x00000004
108 static const uint32_t SECP256R1_ORDER_R2[8] =
110 0xBE79EEA2, 0x83244C95, 0x49BD6FA6, 0x4699799C, 0x2B6BEC59, 0x2845B239, 0xF3D95620, 0x66E12D94
114 static const uint32_t SECP384R1_PRIME_R2[12] =
116 0x00000001, 0xFFFFFFFE, 0x00000000, 0x00000002, 0x00000000, 0xFFFFFFFE, 0x00000000, 0x00000002,
117 0x00000001, 0x00000000, 0x00000000, 0x00000000
121 static const uint32_t SECP384R1_ORDER_R2[12] =
123 0x19B409A9, 0x2D319B24, 0xDF1AA419, 0xFF3D81E5, 0xFCB82947, 0xBC3E483A, 0x4AAB1CC5, 0xD40D4917,
124 0x28266895, 0x3FB05B7A, 0x2B39BF21, 0x0C84EE01
128 static const uint32_t SECP521R1_PRIME_R2[17] =
130 0x00000000, 0x00004000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
131 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
136 static const uint32_t SECP521R1_ORDER_R2[17] =
138 0x61C64CA7, 0x1163115A, 0x4374A642, 0x18354A56, 0x0791D9DC, 0x5D4DD6D3, 0xD3402705, 0x4FB35B72,
139 0xB7756E3A, 0xCFF3D142, 0xA8E567BC, 0x5BCC6D61, 0x492D0D45, 0x2D8E03D1, 0x8C44383D, 0x5B5A3AFE,
144 static const uint32_t BRAINPOOLP256R1_PRIME_R2[8] =
146 0xA6465B6C, 0x8CFEDF7B, 0x614D4F4D, 0x5CCE4C26, 0x6B1AC807, 0xA1ECDACD, 0xE5957FA8, 0x4717AA21
150 static const uint32_t BRAINPOOLP256R1_ORDER_R2[8] =
152 0x3312FCA6, 0xE1D8D8DE, 0x1134E4A0, 0xF35D176A, 0x6C815CB0, 0x9B7F25E7, 0xC3236762, 0x0B25F1B9
156 static const uint32_t BRAINPOOLP384R1_PRIME_R2[12] =
158 0x40B64BDE, 0x087CEFFF, 0x3D7FD965, 0x53528334, 0xC9940899, 0x8E28F99C, 0x9918D5AF, 0x62140191,
159 0xA57E052C, 0xD5C6EF3B, 0x178DF842, 0x36BF6883
163 static const uint32_t BRAINPOOLP384R1_ORDER_R2[12] =
165 0xDE771C8E, 0xAC4ED3A2, 0x2F2B6B6E, 0x37264E20, 0x9802688A, 0x2A927E3B, 0x52D748FF, 0x574A74CB,
166 0x65165FDB, 0x8F886DC9, 0x614E97C2, 0x0CE8941A
170 static const uint32_t BRAINPOOLP512R1_PRIME_R2[16] =
172 0x6158F205, 0x49AD144A, 0x27157905, 0x793FB130, 0x905AFFD3, 0x53B7F9BC, 0x83514A25, 0xE0C19A77,
173 0xD5898057, 0x19486FD8, 0xD42BFF83, 0xA16DAA5F, 0x2056EECC, 0x202E1940, 0xA9FF6450, 0x3C4C9D05
177 static const uint32_t BRAINPOOLP512R1_ORDER_R2[16] =
179 0xCDA81671, 0xD2A3681E, 0x95283DDD, 0x0886B758, 0x33B7627F, 0x3EC64BD0, 0x2F0207E8, 0xA6F230C7,
180 0x3B790DE3, 0xD7F9CC26, 0x2F16BBDF, 0x723C37A2, 0x194B2E56, 0x95DF1B4C, 0x718407B0, 0xA794586A
184 static const uint32_t FRP256V1_PRIME_R2[8] =
186 0xC99F1513, 0xB0C24E77, 0x0C960F92, 0x846F8083, 0xCE137EEE, 0x62B7012F, 0x88EB98AC, 0xB02C8F9F
190 static const uint32_t FRP256V1_ORDER_R2[8] =
192 0xF849D44D, 0x1416B735, 0xBCC2D0E1, 0xB551ADB5, 0xC380D52D, 0xCFB26475, 0x15C243BB, 0x0DF1A20D
196 static const uint32_t SM2_PRIME_R2[8] =
198 0x00000003, 0x00000002, 0xFFFFFFFF, 0x00000002, 0x00000001, 0x00000001, 0x00000002, 0x00000004
202 static const uint32_t SM2_ORDER_R2[8] =
204 0x7C114F20, 0x901192AF, 0xDE6FA2FA, 0x3464504A, 0x3AFFE0D4, 0x620FC84C, 0xA22B3D3B, 0x1EB5E412
215 periph_module_enable(PERIPH_RSA_MODULE);
218 DPORT_REG_CLR_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_MEM_PD);
223 while(DPORT_REG_READ(RSA_QUERY_CLEAN_REG) == 0)
229 #if (MPI_SUPPORT == ENABLED)
253 if(aLen <= 64 && bLen <= 64)
261 esp_crypto_mpi_lock_acquire();
264 DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
266 DPORT_REG_WRITE(RSA_LENGTH_REG, (2 *
n) - 1);
269 for(i = 0; i <
n; i++)
273 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
a->data[i]);
277 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4, 0);
283 for(i = 0; i <
n; i++)
285 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + i * 4, 0);
290 for(i = 0; i <
n; i++)
294 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4,
b->data[i]);
298 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4, 0);
303 DPORT_REG_WRITE(RSA_MULT_START_REG, 1);
306 while(DPORT_REG_READ(RSA_QUERY_INTERRUPT_REG) == 0)
311 r->sign = (
a->sign ==
b->sign) ? 1 : -1;
320 DPORT_INTERRUPT_DISABLE();
323 for(i = 0; i <
r->size; i++)
327 r->data[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
336 DPORT_INTERRUPT_RESTORE();
340 DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
343 esp_crypto_mpi_lock_release();
386 if(modLen > 0 && modLen <= 4096 && expLen > 0 && expLen <= 4096)
389 n =
MAX(modLen, expLen);
415 esp_crypto_mpi_lock_acquire();
418 DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
420 DPORT_REG_WRITE(RSA_LENGTH_REG,
n - 1);
423 for(i = 0; i <
n; i++)
427 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
t.data[i]);
431 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4, 0);
436 for(i = 0; i <
n; i++)
440 DPORT_REG_WRITE(RSA_MEM_Y_BLOCK_BASE + i * 4, e->
data[i]);
444 DPORT_REG_WRITE(RSA_MEM_Y_BLOCK_BASE + i * 4, 0);
449 for(i = 0; i <
n; i++)
453 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4,
p->data[i]);
457 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, 0);
462 for(i = 0; i <
n; i++)
466 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, r2.
data[i]);
470 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, 0);
475 for(
m =
p->data[0], i = 0; i < 4; i++)
477 m =
m * (2U -
m *
p->data[0]);
484 DPORT_REG_WRITE(RSA_M_DASH_REG,
m);
487 DPORT_REG_WRITE(RSA_SEARCH_OPEN_REG, 1);
488 DPORT_REG_WRITE(RSA_SEARCH_POS_REG, expLen - 1);
491 DPORT_REG_WRITE(RSA_MODEXP_START_REG, 1);
494 while(DPORT_REG_READ(RSA_QUERY_INTERRUPT_REG) == 0)
505 DPORT_INTERRUPT_DISABLE();
508 for(i = 0; i <
r->size; i++)
512 r->data[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
521 DPORT_INTERRUPT_RESTORE();
525 DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
528 esp_crypto_mpi_lock_release();
546 #if (EC_SUPPORT == ENABLED)
563 esp_crypto_mpi_lock_acquire();
566 DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
568 DPORT_REG_WRITE(RSA_LENGTH_REG, (2 *
n) - 1);
571 for(i = 0; i <
n; i++)
573 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
a[i]);
578 for(i = 0; i <
n; i++)
580 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + i * 4, 0);
585 for(i = 0; i <
n; i++)
587 DPORT_REG_WRITE(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4,
b[i]);
591 DPORT_REG_WRITE(RSA_MULT_START_REG, 1);
594 while(DPORT_REG_READ(RSA_QUERY_INTERRUPT_REG) == 0)
599 DPORT_INTERRUPT_DISABLE();
605 for(i = 0; i <
n; i++)
607 rl[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
615 for(i = 0; i <
n; i++)
617 rh[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + (
n + i) * 4);
622 DPORT_INTERRUPT_RESTORE();
624 DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
627 esp_crypto_mpi_lock_release();
662 n = (curve->fieldSize + 31) / 32;
665 if(
osStrcmp(curve->name,
"secp224r1") == 0)
667 r2 = SECP224R1_PRIME_R2;
670 else if(
osStrcmp(curve->name,
"secp256k1") == 0)
672 r2 = SECP256K1_PRIME_R2;
675 else if(
osStrcmp(curve->name,
"secp256r1") == 0)
677 r2 = SECP256R1_PRIME_R2;
680 else if(
osStrcmp(curve->name,
"secp384r1") == 0)
682 r2 = SECP384R1_PRIME_R2;
685 else if(
osStrcmp(curve->name,
"secp521r1") == 0)
687 r2 = SECP521R1_PRIME_R2;
690 else if(
osStrcmp(curve->name,
"brainpoolP256r1") == 0)
692 r2 = BRAINPOOLP256R1_PRIME_R2;
695 else if(
osStrcmp(curve->name,
"brainpoolP384r1") == 0)
697 r2 = BRAINPOOLP384R1_PRIME_R2;
700 else if(
osStrcmp(curve->name,
"brainpoolP512r1") == 0)
702 r2 = BRAINPOOLP512R1_PRIME_R2;
705 else if(
osStrcmp(curve->name,
"FRP256v1") == 0)
707 r2 = FRP256V1_PRIME_R2;
710 else if(
osStrcmp(curve->name,
"curveSM2") == 0)
722 if(r2 != NULL &&
m != 0)
725 esp_crypto_mpi_lock_acquire();
728 DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
730 DPORT_REG_WRITE(RSA_LENGTH_REG,
n - 1);
733 for(i = 0; i <
n; i++)
735 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
a[i]);
739 for(i = 0; i <
n; i++)
741 DPORT_REG_WRITE(RSA_MEM_Y_BLOCK_BASE + i * 4,
b[i]);
745 for(i = 0; i <
n; i++)
747 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, curve->p[i]);
751 for(i = 0; i <
n; i++)
753 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, r2[i]);
757 DPORT_REG_WRITE(RSA_M_DASH_REG,
m);
759 DPORT_REG_WRITE(RSA_MOD_MULT_START_REG, 1);
762 while(DPORT_REG_READ(RSA_QUERY_INTERRUPT_REG) == 0)
767 DPORT_INTERRUPT_DISABLE();
770 for(i = 0; i <
n; i++)
772 r[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
776 DPORT_INTERRUPT_RESTORE();
778 DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
781 esp_crypto_mpi_lock_release();
789 curve->fieldMod(curve,
r,
u);
825 n = (curve->orderSize + 31) / 32;
828 if(
osStrcmp(curve->name,
"secp224r1") == 0)
830 r2 = SECP224R1_ORDER_R2;
833 else if(
osStrcmp(curve->name,
"secp256k1") == 0)
835 r2 = SECP256K1_ORDER_R2;
838 else if(
osStrcmp(curve->name,
"secp256r1") == 0)
840 r2 = SECP256R1_ORDER_R2;
843 else if(
osStrcmp(curve->name,
"secp384r1") == 0)
845 r2 = SECP384R1_ORDER_R2;
848 else if(
osStrcmp(curve->name,
"secp521r1") == 0)
850 r2 = SECP521R1_ORDER_R2;
853 else if(
osStrcmp(curve->name,
"brainpoolP256r1") == 0)
855 r2 = BRAINPOOLP256R1_ORDER_R2;
858 else if(
osStrcmp(curve->name,
"brainpoolP384r1") == 0)
860 r2 = BRAINPOOLP384R1_ORDER_R2;
863 else if(
osStrcmp(curve->name,
"brainpoolP512r1") == 0)
865 r2 = BRAINPOOLP512R1_ORDER_R2;
868 else if(
osStrcmp(curve->name,
"FRP256v1") == 0)
870 r2 = FRP256V1_ORDER_R2;
873 else if(
osStrcmp(curve->name,
"curveSM2") == 0)
885 if(r2 != NULL &&
m != 0)
888 esp_crypto_mpi_lock_acquire();
891 DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
893 DPORT_REG_WRITE(RSA_LENGTH_REG,
n - 1);
896 for(i = 0; i <
n; i++)
898 DPORT_REG_WRITE(RSA_MEM_X_BLOCK_BASE + i * 4,
a[i]);
902 for(i = 0; i <
n; i++)
904 DPORT_REG_WRITE(RSA_MEM_Y_BLOCK_BASE + i * 4,
b[i]);
908 for(i = 0; i <
n; i++)
910 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, curve->q[i]);
914 for(i = 0; i <
n; i++)
916 DPORT_REG_WRITE(RSA_MEM_RB_BLOCK_BASE + i * 4, r2[i]);
920 DPORT_REG_WRITE(RSA_M_DASH_REG,
m);
922 DPORT_REG_WRITE(RSA_MOD_MULT_START_REG, 1);
925 while(DPORT_REG_READ(RSA_QUERY_INTERRUPT_REG) == 0)
930 DPORT_INTERRUPT_DISABLE();
933 for(i = 0; i <
n; i++)
935 r[i] = DPORT_SEQUENCE_REG_READ(RSA_MEM_Z_BLOCK_BASE + i * 4);
939 DPORT_INTERRUPT_RESTORE();
941 DPORT_REG_WRITE(RSA_CLEAR_INTERRUPT_REG, 1);
944 esp_crypto_mpi_lock_release();
952 curve->scalarMod(curve,
r,
u);