TMS320F2838xD Ethernet MAC driver. More...

#include "core/nic.h"

Data Structures
struct	F2838xTxDmaDesc
	Transmit descriptor. More...

struct	F2838xRxDmaDesc
	Receive descriptor. More...

Macros
#define	F2838X_ETH_TX_BUFFER_COUNT 2

#define	F2838X_ETH_TX_BUFFER_SIZE 1536

#define	F2838X_ETH_RX_BUFFER_COUNT 4

#define	F2838X_ETH_RX_BUFFER_SIZE 1536

#define	F2838X_ETH_IRQ_PRIORITY 6

#define	ETHERNET_MAC_CONFIGURATION_R HWREG(EMAC_BASE + ETHERNET_O_MAC_CONFIGURATION)

#define	ETHERNET_MAC_EXT_CONFIGURATION_R HWREG(EMAC_BASE + ETHERNET_O_MAC_EXT_CONFIGURATION)

#define	ETHERNET_MAC_PACKET_FILTER_R HWREG(EMAC_BASE + ETHERNET_O_MAC_PACKET_FILTER)

#define	ETHERNET_MAC_WATCHDOG_TIMEOUT_R HWREG(EMAC_BASE + ETHERNET_O_MAC_WATCHDOG_TIMEOUT)

#define	ETHERNET_MAC_HASH_TABLE_REG0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HASH_TABLE_REG0)

#define	ETHERNET_MAC_HASH_TABLE_REG1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HASH_TABLE_REG1)

#define	ETHERNET_MAC_VLAN_TAG_CTRL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_VLAN_TAG_CTRL)

#define	ETHERNET_MAC_VLAN_TAG_DATA_R HWREG(EMAC_BASE + ETHERNET_O_MAC_VLAN_TAG_DATA)

#define	ETHERNET_MAC_VLAN_HASH_TABLE_R HWREG(EMAC_BASE + ETHERNET_O_MAC_VLAN_HASH_TABLE)

#define	ETHERNET_MAC_VLAN_INCL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_VLAN_INCL)

#define	ETHERNET_MAC_INNER_VLAN_INCL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_INNER_VLAN_INCL)

#define	ETHERNET_MAC_Q0_TX_FLOW_CTRL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_Q0_TX_FLOW_CTRL)

#define	ETHERNET_MAC_RX_FLOW_CTRL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RX_FLOW_CTRL)

#define	ETHERNET_MAC_RXQ_CTRL4_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RXQ_CTRL4)

#define	ETHERNET_MAC_RXQ_CTRL0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RXQ_CTRL0)

#define	ETHERNET_MAC_RXQ_CTRL1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RXQ_CTRL1)

#define	ETHERNET_MAC_RXQ_CTRL2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RXQ_CTRL2)

#define	ETHERNET_MAC_INTERRUPT_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_INTERRUPT_STATUS)

#define	ETHERNET_MAC_INTERRUPT_ENABLE_R HWREG(EMAC_BASE + ETHERNET_O_MAC_INTERRUPT_ENABLE)

#define	ETHERNET_MAC_RX_TX_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RX_TX_STATUS)

#define	ETHERNET_MAC_PMT_CONTROL_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_PMT_CONTROL_STATUS)

#define	ETHERNET_MAC_RWK_PACKET_FILTER_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RWK_PACKET_FILTER)

#define	ETHERNET_MAC_LPI_CONTROL_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LPI_CONTROL_STATUS)

#define	ETHERNET_MAC_LPI_TIMERS_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LPI_TIMERS_CONTROL)

#define	ETHERNET_MAC_LPI_ENTRY_TIMER_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LPI_ENTRY_TIMER)

#define	ETHERNET_MAC_1US_TIC_COUNTER_R HWREG(EMAC_BASE + ETHERNET_O_MAC_1US_TIC_COUNTER)

#define	ETHERNET_MAC_VERSION_R HWREG(EMAC_BASE + ETHERNET_O_MAC_VERSION)

#define	ETHERNET_MAC_DEBUG_R HWREG(EMAC_BASE + ETHERNET_O_MAC_DEBUG)

#define	ETHERNET_MAC_HW_FEATURE0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HW_FEATURE0)

#define	ETHERNET_MAC_HW_FEATURE1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HW_FEATURE1)

#define	ETHERNET_MAC_HW_FEATURE2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HW_FEATURE2)

#define	ETHERNET_MAC_HW_FEATURE3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HW_FEATURE3)

#define	ETHERNET_MAC_MDIO_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_MDIO_ADDRESS)

#define	ETHERNET_MAC_MDIO_DATA_R HWREG(EMAC_BASE + ETHERNET_O_MAC_MDIO_DATA)

#define	ETHERNET_MAC_ARP_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ARP_ADDRESS)

#define	ETHERNET_MAC_ADDRESS0_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS0_HIGH)

#define	ETHERNET_MAC_ADDRESS0_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS0_LOW)

#define	ETHERNET_MAC_ADDRESS1_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS1_HIGH)

#define	ETHERNET_MAC_ADDRESS1_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS1_LOW)

#define	ETHERNET_MAC_ADDRESS2_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS2_HIGH)

#define	ETHERNET_MAC_ADDRESS2_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS2_LOW)

#define	ETHERNET_MAC_ADDRESS3_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS3_HIGH)

#define	ETHERNET_MAC_ADDRESS3_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS3_LOW)

#define	ETHERNET_MAC_ADDRESS4_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS4_HIGH)

#define	ETHERNET_MAC_ADDRESS4_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS4_LOW)

#define	ETHERNET_MAC_ADDRESS5_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS5_HIGH)

#define	ETHERNET_MAC_ADDRESS5_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS5_LOW)

#define	ETHERNET_MAC_ADDRESS6_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS6_HIGH)

#define	ETHERNET_MAC_ADDRESS6_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS6_LOW)

#define	ETHERNET_MAC_ADDRESS7_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS7_HIGH)

#define	ETHERNET_MAC_ADDRESS7_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS7_LOW)

#define	ETHERNET_MMC_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MMC_CONTROL)

#define	ETHERNET_MMC_RX_INTERRUPT_R HWREG(EMAC_BASE + ETHERNET_O_MMC_RX_INTERRUPT)

#define	ETHERNET_MMC_TX_INTERRUPT_R HWREG(EMAC_BASE + ETHERNET_O_MMC_TX_INTERRUPT)

#define	ETHERNET_MMC_RX_INTERRUPT_MASK_R HWREG(EMAC_BASE + ETHERNET_O_MMC_RX_INTERRUPT_MASK)

#define	ETHERNET_MMC_TX_INTERRUPT_MASK_R HWREG(EMAC_BASE + ETHERNET_O_MMC_TX_INTERRUPT_MASK)

#define	ETHERNET_TX_OCTET_COUNT_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_OCTET_COUNT_GOOD_BAD)

#define	ETHERNET_TX_PACKET_COUNT_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_PACKET_COUNT_GOOD_BAD)

#define	ETHERNET_TX_BROADCAST_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_BROADCAST_PACKETS_GOOD)

#define	ETHERNET_TX_MULTICAST_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_MULTICAST_PACKETS_GOOD)

#define	ETHERNET_TX_64OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_64OCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_TX_65TO127OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_65TO127OCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_TX_128TO255OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_128TO255OCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_TX_256TO511OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_256TO511OCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_512TO1023OCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_TX_UNICAST_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_UNICAST_PACKETS_GOOD_BAD)

#define	ETHERNET_TX_MULTICAST_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_MULTICAST_PACKETS_GOOD_BAD)

#define	ETHERNET_TX_BROADCAST_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_BROADCAST_PACKETS_GOOD_BAD)

#define	ETHERNET_TX_UNDERFLOW_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_UNDERFLOW_ERROR_PACKETS)

#define	ETHERNET_TX_SINGLE_COLLISION_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_SINGLE_COLLISION_GOOD_PACKETS)

#define	ETHERNET_TX_MULTIPLE_COLLISION_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_MULTIPLE_COLLISION_GOOD_PACKETS)

#define	ETHERNET_TX_DEFERRED_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_DEFERRED_PACKETS)

#define	ETHERNET_TX_LATE_COLLISION_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_LATE_COLLISION_PACKETS)

#define	ETHERNET_TX_EXCESSIVE_COLLISION_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_EXCESSIVE_COLLISION_PACKETS)

#define	ETHERNET_TX_CARRIER_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_CARRIER_ERROR_PACKETS)

#define	ETHERNET_TX_OCTET_COUNT_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_OCTET_COUNT_GOOD)

#define	ETHERNET_TX_PACKET_COUNT_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_PACKET_COUNT_GOOD)

#define	ETHERNET_TX_EXCESSIVE_DEFERRAL_ERROR_R HWREG(EMAC_BASE + ETHERNET_O_TX_EXCESSIVE_DEFERRAL_ERROR)

#define	ETHERNET_TX_PAUSE_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_PAUSE_PACKETS)

#define	ETHERNET_TX_VLAN_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_VLAN_PACKETS_GOOD)

#define	ETHERNET_TX_OSIZE_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_OSIZE_PACKETS_GOOD)

#define	ETHERNET_RX_PACKETS_COUNT_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_PACKETS_COUNT_GOOD_BAD)

#define	ETHERNET_RX_OCTET_COUNT_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_OCTET_COUNT_GOOD_BAD)

#define	ETHERNET_RX_OCTET_COUNT_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_OCTET_COUNT_GOOD)

#define	ETHERNET_RX_BROADCAST_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_BROADCAST_PACKETS_GOOD)

#define	ETHERNET_RX_MULTICAST_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_MULTICAST_PACKETS_GOOD)

#define	ETHERNET_RX_CRC_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_CRC_ERROR_PACKETS)

#define	ETHERNET_RX_ALIGNMENT_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_ALIGNMENT_ERROR_PACKETS)

#define	ETHERNET_RX_RUNT_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_RUNT_ERROR_PACKETS)

#define	ETHERNET_RX_JABBER_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_JABBER_ERROR_PACKETS)

#define	ETHERNET_RX_UNDERSIZE_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_UNDERSIZE_PACKETS_GOOD)

#define	ETHERNET_RX_OVERSIZE_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_OVERSIZE_PACKETS_GOOD)

#define	ETHERNET_RX_64OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_64OCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_RX_65TO127OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_65TO127OCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_RX_128TO255OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_128TO255OCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_RX_256TO511OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_256TO511OCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_512TO1023OCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD)

#define	ETHERNET_RX_UNICAST_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_UNICAST_PACKETS_GOOD)

#define	ETHERNET_RX_LENGTH_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_LENGTH_ERROR_PACKETS)

#define	ETHERNET_RX_OUT_OF_RANGE_TYPE_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_OUT_OF_RANGE_TYPE_PACKETS)

#define	ETHERNET_RX_PAUSE_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_PAUSE_PACKETS)

#define	ETHERNET_RX_FIFO_OVERFLOW_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_FIFO_OVERFLOW_PACKETS)

#define	ETHERNET_RX_VLAN_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_VLAN_PACKETS_GOOD_BAD)

#define	ETHERNET_RX_WATCHDOG_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_WATCHDOG_ERROR_PACKETS)

#define	ETHERNET_RX_RECEIVE_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_RECEIVE_ERROR_PACKETS)

#define	ETHERNET_RX_CONTROL_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_CONTROL_PACKETS_GOOD)

#define	ETHERNET_TX_LPI_USEC_CNTR_R HWREG(EMAC_BASE + ETHERNET_O_TX_LPI_USEC_CNTR)

#define	ETHERNET_TX_LPI_TRAN_CNTR_R HWREG(EMAC_BASE + ETHERNET_O_TX_LPI_TRAN_CNTR)

#define	ETHERNET_RX_LPI_USEC_CNTR_R HWREG(EMAC_BASE + ETHERNET_O_RX_LPI_USEC_CNTR)

#define	ETHERNET_RX_LPI_TRAN_CNTR_R HWREG(EMAC_BASE + ETHERNET_O_RX_LPI_TRAN_CNTR)

#define	ETHERNET_MMC_IPC_RX_INTERRUPT_MASK_R HWREG(EMAC_BASE + ETHERNET_O_MMC_IPC_RX_INTERRUPT_MASK)

#define	ETHERNET_MMC_IPC_RX_INTERRUPT_R HWREG(EMAC_BASE + ETHERNET_O_MMC_IPC_RX_INTERRUPT)

#define	ETHERNET_RXIPV4_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_GOOD_PACKETS)

#define	ETHERNET_RXIPV4_HEADER_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_HEADER_ERROR_PACKETS)

#define	ETHERNET_RXIPV4_NO_PAYLOAD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_NO_PAYLOAD_PACKETS)

#define	ETHERNET_RXIPV4_FRAGMENTED_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_FRAGMENTED_PACKETS)

#define	ETHERNET_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS)

#define	ETHERNET_RXIPV6_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_GOOD_PACKETS)

#define	ETHERNET_RXIPV6_HEADER_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_HEADER_ERROR_PACKETS)

#define	ETHERNET_RXIPV6_NO_PAYLOAD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_NO_PAYLOAD_PACKETS)

#define	ETHERNET_RXUDP_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXUDP_GOOD_PACKETS)

#define	ETHERNET_RXUDP_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXUDP_ERROR_PACKETS)

#define	ETHERNET_RXTCP_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXTCP_GOOD_PACKETS)

#define	ETHERNET_RXTCP_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXTCP_ERROR_PACKETS)

#define	ETHERNET_RXICMP_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXICMP_GOOD_PACKETS)

#define	ETHERNET_RXICMP_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXICMP_ERROR_PACKETS)

#define	ETHERNET_RXIPV4_GOOD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_GOOD_OCTETS)

#define	ETHERNET_RXIPV4_HEADER_ERROR_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_HEADER_ERROR_OCTETS)

#define	ETHERNET_RXIPV4_NO_PAYLOAD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_NO_PAYLOAD_OCTETS)

#define	ETHERNET_RXIPV4_FRAGMENTED_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_FRAGMENTED_OCTETS)

#define	ETHERNET_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS)

#define	ETHERNET_RXIPV6_GOOD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_GOOD_OCTETS)

#define	ETHERNET_RXIPV6_HEADER_ERROR_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_HEADER_ERROR_OCTETS)

#define	ETHERNET_RXIPV6_NO_PAYLOAD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_NO_PAYLOAD_OCTETS)

#define	ETHERNET_RXUDP_GOOD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXUDP_GOOD_OCTETS)

#define	ETHERNET_RXUDP_ERROR_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXUDP_ERROR_OCTETS)

#define	ETHERNET_RXTCP_GOOD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXTCP_GOOD_OCTETS)

#define	ETHERNET_RXTCP_ERROR_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXTCP_ERROR_OCTETS)

#define	ETHERNET_RXICMP_GOOD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXICMP_GOOD_OCTETS)

#define	ETHERNET_RXICMP_ERROR_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXICMP_ERROR_OCTETS)

#define	ETHERNET_MAC_L3_L4_CONTROL0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_L3_L4_CONTROL0)

#define	ETHERNET_MAC_LAYER4_ADDRESS0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER4_ADDRESS0)

#define	ETHERNET_MAC_LAYER3_ADDR0_REG0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR0_REG0)

#define	ETHERNET_MAC_LAYER3_ADDR1_REG0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR1_REG0)

#define	ETHERNET_MAC_LAYER3_ADDR2_REG0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR2_REG0)

#define	ETHERNET_MAC_LAYER3_ADDR3_REG0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR3_REG0)

#define	ETHERNET_MAC_L3_L4_CONTROL1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_L3_L4_CONTROL1)

#define	ETHERNET_MAC_LAYER4_ADDRESS1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER4_ADDRESS1)

#define	ETHERNET_MAC_LAYER3_ADDR0_REG1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR0_REG1)

#define	ETHERNET_MAC_LAYER3_ADDR1_REG1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR1_REG1)

#define	ETHERNET_MAC_LAYER3_ADDR2_REG1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR2_REG1)

#define	ETHERNET_MAC_LAYER3_ADDR3_REG1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR3_REG1)

#define	ETHERNET_MAC_L3_L4_CONTROL2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_L3_L4_CONTROL2)

#define	ETHERNET_MAC_LAYER4_ADDRESS2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER4_ADDRESS2)

#define	ETHERNET_MAC_LAYER3_ADDR0_REG2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR0_REG2)

#define	ETHERNET_MAC_LAYER3_ADDR1_REG2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR1_REG2)

#define	ETHERNET_MAC_LAYER3_ADDR2_REG2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR2_REG2)

#define	ETHERNET_MAC_LAYER3_ADDR3_REG2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR3_REG2)

#define	ETHERNET_MAC_L3_L4_CONTROL3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_L3_L4_CONTROL3)

#define	ETHERNET_MAC_LAYER4_ADDRESS3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER4_ADDRESS3)

#define	ETHERNET_MAC_LAYER3_ADDR0_REG3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR0_REG3)

#define	ETHERNET_MAC_LAYER3_ADDR1_REG3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR1_REG3)

#define	ETHERNET_MAC_LAYER3_ADDR2_REG3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR2_REG3)

#define	ETHERNET_MAC_LAYER3_ADDR3_REG3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR3_REG3)

#define	ETHERNET_MAC_TIMESTAMP_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_CONTROL)

#define	ETHERNET_MAC_SUB_SECOND_INCREMENT_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SUB_SECOND_INCREMENT)

#define	ETHERNET_MAC_SYSTEM_TIME_SECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SYSTEM_TIME_SECONDS)

#define	ETHERNET_MAC_SYSTEM_TIME_NANOSECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SYSTEM_TIME_NANOSECONDS)

#define	ETHERNET_MAC_SYSTEM_TIME_SECONDS_UPDATE_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SYSTEM_TIME_SECONDS_UPDATE)

#define	ETHERNET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE)

#define	ETHERNET_MAC_TIMESTAMP_ADDEND_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_ADDEND)

#define	ETHERNET_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS)

#define	ETHERNET_MAC_TIMESTAMP_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_STATUS)

#define	ETHERNET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS)

#define	ETHERNET_MAC_TX_TIMESTAMP_STATUS_SECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TX_TIMESTAMP_STATUS_SECONDS)

#define	ETHERNET_MAC_AUXILIARY_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_AUXILIARY_CONTROL)

#define	ETHERNET_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS)

#define	ETHERNET_MAC_AUXILIARY_TIMESTAMP_SECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_AUXILIARY_TIMESTAMP_SECONDS)

#define	ETHERNET_MAC_TIMESTAMP_INGRESS_ASYM_CORR_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_INGRESS_ASYM_CORR)

#define	ETHERNET_MAC_TIMESTAMP_EGRESS_ASYM_CORR_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_EGRESS_ASYM_CORR)

#define	ETHERNET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND)

#define	ETHERNET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND)

#define	ETHERNET_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC)

#define	ETHERNET_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC)

#define	ETHERNET_MAC_PPS_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_PPS_CONTROL)

#define	ETHERNET_MAC_PTO_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_PTO_CONTROL)

#define	ETHERNET_MAC_SOURCE_PORT_IDENTITY0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SOURCE_PORT_IDENTITY0)

#define	ETHERNET_MAC_SOURCE_PORT_IDENTITY1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SOURCE_PORT_IDENTITY1)

#define	ETHERNET_MAC_SOURCE_PORT_IDENTITY2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SOURCE_PORT_IDENTITY2)

#define	ETHERNET_MAC_LOG_MESSAGE_INTERVAL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LOG_MESSAGE_INTERVAL)

#define	ETHERNET_DMA_MODE_R HWREG(EMAC_BASE + ETHERNET_O_DMA_MODE)

#define	ETHERNET_DMA_SYSBUS_MODE_R HWREG(EMAC_BASE + ETHERNET_O_DMA_SYSBUS_MODE)

#define	ETHERNET_DMA_INTERRUPT_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_INTERRUPT_STATUS)

#define	ETHERNET_DMA_DEBUG_STATUS0_R HWREG(EMAC_BASE + ETHERNET_O_DMA_DEBUG_STATUS0)

#define	ETHERNET_DMA_CH0_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_CONTROL)

#define	ETHERNET_DMA_CH0_TX_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_TX_CONTROL)

#define	ETHERNET_DMA_CH0_RX_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_RX_CONTROL)

#define	ETHERNET_DMA_CH0_TXDESC_LIST_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_TXDESC_LIST_ADDRESS)

#define	ETHERNET_DMA_CH0_RXDESC_LIST_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_RXDESC_LIST_ADDRESS)

#define	ETHERNET_DMA_CH0_TXDESC_TAIL_POINTER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_TXDESC_TAIL_POINTER)

#define	ETHERNET_DMA_CH0_RXDESC_TAIL_POINTER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_RXDESC_TAIL_POINTER)

#define	ETHERNET_DMA_CH0_TXDESC_RING_LENGTH_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_TXDESC_RING_LENGTH)

#define	ETHERNET_DMA_CH0_RXDESC_RING_LENGTH_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_RXDESC_RING_LENGTH)

#define	ETHERNET_DMA_CH0_INTERRUPT_ENABLE_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_INTERRUPT_ENABLE)

#define	ETHERNET_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER)

#define	ETHERNET_DMA_CH0_CURRENT_APP_TXDESC_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_CURRENT_APP_TXDESC)

#define	ETHERNET_DMA_CH0_CURRENT_APP_RXDESC_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_CURRENT_APP_RXDESC)

#define	ETHERNET_DMA_CH0_CURRENT_APP_TXBUFFER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_CURRENT_APP_TXBUFFER)

#define	ETHERNET_DMA_CH0_CURRENT_APP_RXBUFFER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_CURRENT_APP_RXBUFFER)

#define	ETHERNET_DMA_CH0_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_STATUS)

#define	ETHERNET_DMA_CH0_MISS_FRAME_CNT_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_MISS_FRAME_CNT)

#define	ETHERNET_DMA_CH1_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_CONTROL)

#define	ETHERNET_DMA_CH1_TX_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_TX_CONTROL)

#define	ETHERNET_DMA_CH1_RX_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_RX_CONTROL)

#define	ETHERNET_DMA_CH1_TXDESC_LIST_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_TXDESC_LIST_ADDRESS)

#define	ETHERNET_DMA_CH1_RXDESC_LIST_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_RXDESC_LIST_ADDRESS)

#define	ETHERNET_DMA_CH1_TXDESC_TAIL_POINTER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_TXDESC_TAIL_POINTER)

#define	ETHERNET_DMA_CH1_RXDESC_TAIL_POINTER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_RXDESC_TAIL_POINTER)

#define	ETHERNET_DMA_CH1_TXDESC_RING_LENGTH_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_TXDESC_RING_LENGTH)

#define	ETHERNET_DMA_CH1_RXDESC_RING_LENGTH_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_RXDESC_RING_LENGTH)

#define	ETHERNET_DMA_CH1_INTERRUPT_ENABLE_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_INTERRUPT_ENABLE)

#define	ETHERNET_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER)

#define	ETHERNET_DMA_CH1_CURRENT_APP_TXDESC_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_CURRENT_APP_TXDESC)

#define	ETHERNET_DMA_CH1_CURRENT_APP_RXDESC_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_CURRENT_APP_RXDESC)

#define	ETHERNET_DMA_CH1_CURRENT_APP_TXBUFFER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_CURRENT_APP_TXBUFFER)

#define	ETHERNET_DMA_CH1_CURRENT_APP_RXBUFFER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_CURRENT_APP_RXBUFFER)

#define	ETHERNET_DMA_CH1_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_STATUS)

#define	ETHERNET_DMA_CH1_MISS_FRAME_CNT_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_MISS_FRAME_CNT)

#define	ETHERNET_MTL_OPERATION_MODE_R HWREG(EMAC_BASE + ETHERNET_O_MTL_OPERATION_MODE)

#define	ETHERNET_MTL_DBG_CTL_R HWREG(EMAC_BASE + ETHERNET_O_MTL_DBG_CTL)

#define	ETHERNET_MTL_DBG_STS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_DBG_STS)

#define	ETHERNET_MTL_FIFO_DEBUG_DATA_R HWREG(EMAC_BASE + ETHERNET_O_MTL_FIFO_DEBUG_DATA)

#define	ETHERNET_MTL_INTERRUPT_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_INTERRUPT_STATUS)

#define	ETHERNET_MTL_RXQ_DMA_MAP0_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ_DMA_MAP0)

#define	ETHERNET_MTL_TXQ0_OPERATION_MODE_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ0_OPERATION_MODE)

#define	ETHERNET_MTL_TXQ0_UNDERFLOW_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ0_UNDERFLOW)

#define	ETHERNET_MTL_TXQ0_DEBUG_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ0_DEBUG)

#define	ETHERNET_MTL_TXQ0_ETS_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ0_ETS_STATUS)

#define	ETHERNET_MTL_TXQ0_QUANTUM_WEIGHT_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ0_QUANTUM_WEIGHT)

#define	ETHERNET_MTL_Q0_INTERRUPT_CONTROL_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_Q0_INTERRUPT_CONTROL_STATUS)

#define	ETHERNET_MTL_RXQ0_OPERATION_MODE_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ0_OPERATION_MODE)

#define	ETHERNET_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT)

#define	ETHERNET_MTL_RXQ0_DEBUG_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ0_DEBUG)

#define	ETHERNET_MTL_RXQ0_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ0_CONTROL)

#define	ETHERNET_MTL_TXQ1_OPERATION_MODE_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ1_OPERATION_MODE)

#define	ETHERNET_MTL_TXQ1_UNDERFLOW_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ1_UNDERFLOW)

#define	ETHERNET_MTL_TXQ1_DEBUG_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ1_DEBUG)

#define	ETHERNET_MTL_TXQ1_ETS_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ1_ETS_STATUS)

#define	ETHERNET_MTL_TXQ1_QUANTUM_WEIGHT_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ1_QUANTUM_WEIGHT)

#define	ETHERNET_MTL_Q1_INTERRUPT_CONTROL_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_Q1_INTERRUPT_CONTROL_STATUS)

#define	ETHERNET_MTL_RXQ1_OPERATION_MODE_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ1_OPERATION_MODE)

#define	ETHERNET_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT)

#define	ETHERNET_MTL_RXQ1_DEBUG_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ1_DEBUG)

#define	ETHERNET_MTL_RXQ1_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ1_CONTROL)

#define	ETHERNETSS_IPREVNUM_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_IPREVNUM)

#define	ETHERNETSS_CTRLSTS_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_CTRLSTS)

#define	ETHERNETSS_PTPTSTRIGSEL0_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPTSTRIGSEL0)

#define	ETHERNETSS_PTPTSTRIGSEL1_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPTSTRIGSEL1)

#define	ETHERNETSS_PTPTSSWTRIG0_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPTSSWTRIG0)

#define	ETHERNETSS_PTPTSSWTRIG1_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPTSSWTRIG1)

#define	ETHERNETSS_PTPPPSR0_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPPPSR0)

#define	ETHERNETSS_PTPPPSR1_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPPPSR1)

#define	ETHERNETSS_PTP_TSRL_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTP_TSRL)

#define	ETHERNETSS_PTP_TSRH_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTP_TSRH)

#define	ETHERNETSS_PTP_TSWL_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTP_TSWL)

#define	ETHERNETSS_PTP_TSWH_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTP_TSWH)

#define	ETHERNETSS_REVMII_CTRL_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_REVMII_CTRL)

#define	ETH_TDES0_BUF1AP 0xFFFFFFFF

#define	ETH_TDES1_BUF2AP 0xFFFFFFFF

#define	ETH_TDES2_IOC 0x80000000

#define	ETH_TDES2_TTSE 0x40000000

#define	ETH_TDES2_B2L 0x3FFF0000

#define	ETH_TDES2_VTIR 0x0000C000

#define	ETH_TDES2_B1L 0x00003FFF

#define	ETH_TDES3_OWN 0x80000000

#define	ETH_TDES3_CTXT 0x40000000

#define	ETH_TDES3_FD 0x20000000

#define	ETH_TDES3_LD 0x10000000

#define	ETH_TDES3_CPC 0x0C000000

#define	ETH_TDES3_SAIC 0x03800000

#define	ETH_TDES3_THL 0x00780000

#define	ETH_TDES3_TSE 0x00040000

#define	ETH_TDES3_CIC 0x00030000

#define	ETH_TDES3_FL 0x00007FFF

#define	ETH_TDES0_TTSL 0xFFFFFFFF

#define	ETH_TDES1_TTSH 0xFFFFFFFF

#define	ETH_TDES3_OWN 0x80000000

#define	ETH_TDES3_CTXT 0x40000000

#define	ETH_TDES3_FD 0x20000000

#define	ETH_TDES3_LD 0x10000000

#define	ETH_TDES3_TTSS 0x00020000

#define	ETH_TDES3_ES 0x00008000

#define	ETH_TDES3_JT 0x00004000

#define	ETH_TDES3_FF 0x00002000

#define	ETH_TDES3_PCE 0x00001000

#define	ETH_TDES3_LOC 0x00000800

#define	ETH_TDES3_NC 0x00000400

#define	ETH_TDES3_LC 0x00000200

#define	ETH_TDES3_EC 0x00000100

#define	ETH_TDES3_CC 0x000000F0

#define	ETH_TDES3_ED 0x00000008

#define	ETH_TDES3_UF 0x00000004

#define	ETH_TDES3_DB 0x00000002

#define	ETH_TDES3_IHE 0x00000001

#define	ETH_TDES0_TTSL 0xFFFFFFFF

#define	ETH_TDES1_TTSH 0xFFFFFFFF

#define	ETH_TDES2_IVT 0xFFFF0000

#define	ETH_TDES2_MSS 0x00003FFF

#define	ETH_TDES3_OWN 0x80000000

#define	ETH_TDES3_CTXT 0x40000000

#define	ETH_TDES3_OSTC 0x08000000

#define	ETH_TDES3_TCMSSV 0x04000000

#define	ETH_TDES3_CDE 0x00800000

#define	ETH_TDES3_IVLTV 0x00020000

#define	ETH_TDES3_VLTV 0x00010000

#define	ETH_TDES3_VT 0x0000FFFF

#define	ETH_RDES0_BUF1AP 0xFFFFFFFF

#define	ETH_RDES2_BUF2AP 0xFFFFFFFF

#define	ETH_RDES3_OWN 0x80000000

#define	ETH_RDES3_IOC 0x40000000

#define	ETH_RDES3_BUF2V 0x02000000

#define	ETH_RDES3_BUF1V 0x01000000

#define	ETH_RDES0_IVT 0xFFFF0000

#define	ETH_RDES0_OVT 0x0000FFFF

#define	ETH_RDES1_OPC 0xFFFF0000

#define	ETH_RDES1_TD 0x00008000

#define	ETH_RDES1_TSA 0x00004000

#define	ETH_RDES1_PV 0x00002000

#define	ETH_RDES1_PFT 0x00001000

#define	ETH_RDES1_PMT 0x00000F00

#define	ETH_RDES1_IPCE 0x00000080

#define	ETH_RDES1_IPCB 0x00000040

#define	ETH_RDES1_IPV6 0x00000020

#define	ETH_RDES1_IPV4 0x00000010

#define	ETH_RDES1_IPHE 0x00000008

#define	ETH_RDES1_PT 0x00000007

#define	ETH_RDES2_L3L4FM 0xE0000000

#define	ETH_RDES2_L4FM 0x10000000

#define	ETH_RDES2_L3FM 0x08000000

#define	ETH_RDES2_MADRM 0x07F80000

#define	ETH_RDES2_HF 0x00040000

#define	ETH_RDES2_DAF 0x00020000

#define	ETH_RDES2_SAF 0x00010000

#define	ETH_RDES2_VF 0x00008000

#define	ETH_RDES2_ARPRN 0x00000400

#define	ETH_RDES3_OWN 0x80000000

#define	ETH_RDES3_CTXT 0x40000000

#define	ETH_RDES3_FD 0x20000000

#define	ETH_RDES3_LD 0x10000000

#define	ETH_RDES3_RS2V 0x08000000

#define	ETH_RDES3_RS1V 0x04000000

#define	ETH_RDES3_RS0V 0x02000000

#define	ETH_RDES3_CE 0x01000000

#define	ETH_RDES3_GP 0x00800000

#define	ETH_RDES3_RWT 0x00400000

#define	ETH_RDES3_OE 0x00200000

#define	ETH_RDES3_RE 0x00100000

#define	ETH_RDES3_DE 0x00080000

#define	ETH_RDES3_LT 0x00070000

#define	ETH_RDES3_ES 0x00008000

#define	ETH_RDES3_PL 0x00007FFF

#define	ETH_RDES0_RTSL 0xFFFFFFFF

#define	ETH_RDES1_RTSH 0xFFFFFFFF

#define	ETH_RDES3_OWN 0x80000000

#define	ETH_RDES3_CTXT 0x40000000

Functions
error_t	f2838xEthInit (NetInterface *interface)
	TMS320F2838xD Ethernet MAC initialization. More...

void	f2838xEthInitGpio (NetInterface *interface)
	GPIO configuration. More...

void	f2838xEthInitDmaDesc (NetInterface *interface)
	Initialize DMA descriptor lists. More...

void	f2838xEthTick (NetInterface *interface)
	TMS320F2838xD Ethernet MAC timer handler. More...

void	f2838xEthEnableIrq (NetInterface *interface)
	Enable interrupts. More...

void	f2838xEthDisableIrq (NetInterface *interface)
	Disable interrupts. More...

void	f2838xEthIrqHandler (void)
	TMS320F2838xD Ethernet MAC interrupt service routine. More...

void	f2838xEthEventHandler (NetInterface *interface)
	TMS320F2838xD Ethernet MAC event handler. More...

error_t	f2838xEthSendPacket (NetInterface interface, const NetBuffer buffer, size_t offset, NetTxAncillary *ancillary)
	Send a packet. More...

error_t	f2838xEthReceivePacket (NetInterface *interface)
	Receive a packet. More...

error_t	f2838xEthUpdateMacAddrFilter (NetInterface *interface)
	Configure MAC address filtering. More...

error_t	f2838xEthUpdateMacConfig (NetInterface *interface)
	Adjust MAC configuration parameters for proper operation. More...

void	f2838xEthWritePhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
	Write PHY register. More...

uint16_t	f2838xEthReadPhyReg (uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
	Read PHY register. More...

uint32_t	f2838xEthCalcCrc (const void *data, size_t length)
	CRC calculation. More...

Variables
const NicDriver	f2838xEthDriver
	TMS320F2838xD Ethernet MAC driver. More...

Detailed Description

TMS320F2838xD Ethernet MAC driver.

License

SPDX-License-Identifier: GPL-2.0-or-later

This file is part of CycloneTCP Open.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.

Author: Oryx Embedded SARL (www.oryx-embedded.com)

Version: 2.4.4

Definition in file f2838x_eth_driver.h.

Macro Definition Documentation

◆ ETH_RDES0_BUF1AP

#define ETH_RDES0_BUF1AP 0xFFFFFFFF

Definition at line 401 of file f2838x_eth_driver.h.

◆ ETH_RDES0_IVT

#define ETH_RDES0_IVT 0xFFFF0000

Definition at line 409 of file f2838x_eth_driver.h.

◆ ETH_RDES0_OVT

#define ETH_RDES0_OVT 0x0000FFFF

Definition at line 410 of file f2838x_eth_driver.h.

◆ ETH_RDES0_RTSL

#define ETH_RDES0_RTSL 0xFFFFFFFF

Definition at line 450 of file f2838x_eth_driver.h.

◆ ETH_RDES1_IPCB

#define ETH_RDES1_IPCB 0x00000040

Definition at line 418 of file f2838x_eth_driver.h.

◆ ETH_RDES1_IPCE

#define ETH_RDES1_IPCE 0x00000080

Definition at line 417 of file f2838x_eth_driver.h.

◆ ETH_RDES1_IPHE

#define ETH_RDES1_IPHE 0x00000008

Definition at line 421 of file f2838x_eth_driver.h.

◆ ETH_RDES1_IPV4

#define ETH_RDES1_IPV4 0x00000010

Definition at line 420 of file f2838x_eth_driver.h.

◆ ETH_RDES1_IPV6

#define ETH_RDES1_IPV6 0x00000020

Definition at line 419 of file f2838x_eth_driver.h.

◆ ETH_RDES1_OPC

#define ETH_RDES1_OPC 0xFFFF0000

Definition at line 411 of file f2838x_eth_driver.h.

◆ ETH_RDES1_PFT

#define ETH_RDES1_PFT 0x00001000

Definition at line 415 of file f2838x_eth_driver.h.

◆ ETH_RDES1_PMT

#define ETH_RDES1_PMT 0x00000F00

Definition at line 416 of file f2838x_eth_driver.h.

◆ ETH_RDES1_PT

#define ETH_RDES1_PT 0x00000007

Definition at line 422 of file f2838x_eth_driver.h.

◆ ETH_RDES1_PV

#define ETH_RDES1_PV 0x00002000

Definition at line 414 of file f2838x_eth_driver.h.

◆ ETH_RDES1_RTSH

#define ETH_RDES1_RTSH 0xFFFFFFFF

Definition at line 451 of file f2838x_eth_driver.h.

◆ ETH_RDES1_TD

#define ETH_RDES1_TD 0x00008000

Definition at line 412 of file f2838x_eth_driver.h.

◆ ETH_RDES1_TSA

#define ETH_RDES1_TSA 0x00004000

Definition at line 413 of file f2838x_eth_driver.h.

◆ ETH_RDES2_ARPRN

#define ETH_RDES2_ARPRN 0x00000400

Definition at line 431 of file f2838x_eth_driver.h.

◆ ETH_RDES2_BUF2AP

#define ETH_RDES2_BUF2AP 0xFFFFFFFF

Definition at line 402 of file f2838x_eth_driver.h.

◆ ETH_RDES2_DAF

#define ETH_RDES2_DAF 0x00020000

Definition at line 428 of file f2838x_eth_driver.h.

◆ ETH_RDES2_HF

#define ETH_RDES2_HF 0x00040000

Definition at line 427 of file f2838x_eth_driver.h.

◆ ETH_RDES2_L3FM

#define ETH_RDES2_L3FM 0x08000000

Definition at line 425 of file f2838x_eth_driver.h.

◆ ETH_RDES2_L3L4FM

#define ETH_RDES2_L3L4FM 0xE0000000

Definition at line 423 of file f2838x_eth_driver.h.

◆ ETH_RDES2_L4FM

#define ETH_RDES2_L4FM 0x10000000

Definition at line 424 of file f2838x_eth_driver.h.

◆ ETH_RDES2_MADRM

#define ETH_RDES2_MADRM 0x07F80000

Definition at line 426 of file f2838x_eth_driver.h.

◆ ETH_RDES2_SAF

#define ETH_RDES2_SAF 0x00010000

Definition at line 429 of file f2838x_eth_driver.h.

◆ ETH_RDES2_VF

#define ETH_RDES2_VF 0x00008000

Definition at line 430 of file f2838x_eth_driver.h.

◆ ETH_RDES3_BUF1V

#define ETH_RDES3_BUF1V 0x01000000

Definition at line 406 of file f2838x_eth_driver.h.

◆ ETH_RDES3_BUF2V

#define ETH_RDES3_BUF2V 0x02000000

Definition at line 405 of file f2838x_eth_driver.h.

◆ ETH_RDES3_CE

#define ETH_RDES3_CE 0x01000000

Definition at line 439 of file f2838x_eth_driver.h.

◆ ETH_RDES3_CTXT [1/2]

#define ETH_RDES3_CTXT 0x40000000

Definition at line 453 of file f2838x_eth_driver.h.

◆ ETH_RDES3_CTXT [2/2]

#define ETH_RDES3_CTXT 0x40000000

Definition at line 453 of file f2838x_eth_driver.h.

◆ ETH_RDES3_DE

#define ETH_RDES3_DE 0x00080000

Definition at line 444 of file f2838x_eth_driver.h.

◆ ETH_RDES3_ES

#define ETH_RDES3_ES 0x00008000

Definition at line 446 of file f2838x_eth_driver.h.

◆ ETH_RDES3_FD

#define ETH_RDES3_FD 0x20000000

Definition at line 434 of file f2838x_eth_driver.h.

◆ ETH_RDES3_GP

#define ETH_RDES3_GP 0x00800000

Definition at line 440 of file f2838x_eth_driver.h.

◆ ETH_RDES3_IOC

#define ETH_RDES3_IOC 0x40000000

Definition at line 404 of file f2838x_eth_driver.h.

◆ ETH_RDES3_LD

#define ETH_RDES3_LD 0x10000000

Definition at line 435 of file f2838x_eth_driver.h.

◆ ETH_RDES3_LT

#define ETH_RDES3_LT 0x00070000

Definition at line 445 of file f2838x_eth_driver.h.

◆ ETH_RDES3_OE

#define ETH_RDES3_OE 0x00200000

Definition at line 442 of file f2838x_eth_driver.h.

◆ ETH_RDES3_OWN [1/3]

#define ETH_RDES3_OWN 0x80000000

Definition at line 452 of file f2838x_eth_driver.h.

◆ ETH_RDES3_OWN [2/3]

#define ETH_RDES3_OWN 0x80000000

Definition at line 452 of file f2838x_eth_driver.h.

◆ ETH_RDES3_OWN [3/3]

#define ETH_RDES3_OWN 0x80000000

Definition at line 452 of file f2838x_eth_driver.h.

◆ ETH_RDES3_PL

#define ETH_RDES3_PL 0x00007FFF

Definition at line 447 of file f2838x_eth_driver.h.

◆ ETH_RDES3_RE

#define ETH_RDES3_RE 0x00100000

Definition at line 443 of file f2838x_eth_driver.h.

◆ ETH_RDES3_RS0V

#define ETH_RDES3_RS0V 0x02000000

Definition at line 438 of file f2838x_eth_driver.h.

◆ ETH_RDES3_RS1V

#define ETH_RDES3_RS1V 0x04000000

Definition at line 437 of file f2838x_eth_driver.h.

◆ ETH_RDES3_RS2V

#define ETH_RDES3_RS2V 0x08000000

Definition at line 436 of file f2838x_eth_driver.h.

◆ ETH_RDES3_RWT

#define ETH_RDES3_RWT 0x00400000

Definition at line 441 of file f2838x_eth_driver.h.

◆ ETH_TDES0_BUF1AP

#define ETH_TDES0_BUF1AP 0xFFFFFFFF

Definition at line 346 of file f2838x_eth_driver.h.

◆ ETH_TDES0_TTSL [1/2]

#define ETH_TDES0_TTSL 0xFFFFFFFF

Definition at line 387 of file f2838x_eth_driver.h.

◆ ETH_TDES0_TTSL [2/2]

#define ETH_TDES0_TTSL 0xFFFFFFFF

Definition at line 387 of file f2838x_eth_driver.h.

◆ ETH_TDES1_BUF2AP

#define ETH_TDES1_BUF2AP 0xFFFFFFFF

Definition at line 347 of file f2838x_eth_driver.h.

◆ ETH_TDES1_TTSH [1/2]

#define ETH_TDES1_TTSH 0xFFFFFFFF

Definition at line 388 of file f2838x_eth_driver.h.

◆ ETH_TDES1_TTSH [2/2]

#define ETH_TDES1_TTSH 0xFFFFFFFF

Definition at line 388 of file f2838x_eth_driver.h.

◆ ETH_TDES2_B1L

#define ETH_TDES2_B1L 0x00003FFF

Definition at line 352 of file f2838x_eth_driver.h.

◆ ETH_TDES2_B2L

#define ETH_TDES2_B2L 0x3FFF0000

Definition at line 350 of file f2838x_eth_driver.h.

◆ ETH_TDES2_IOC

#define ETH_TDES2_IOC 0x80000000

Definition at line 348 of file f2838x_eth_driver.h.

◆ ETH_TDES2_IVT

#define ETH_TDES2_IVT 0xFFFF0000

Definition at line 389 of file f2838x_eth_driver.h.

◆ ETH_TDES2_MSS

#define ETH_TDES2_MSS 0x00003FFF

Definition at line 390 of file f2838x_eth_driver.h.

◆ ETH_TDES2_TTSE

#define ETH_TDES2_TTSE 0x40000000

Definition at line 349 of file f2838x_eth_driver.h.

◆ ETH_TDES2_VTIR

#define ETH_TDES2_VTIR 0x0000C000

Definition at line 351 of file f2838x_eth_driver.h.

◆ ETH_TDES3_CC

#define ETH_TDES3_CC 0x000000F0

Definition at line 380 of file f2838x_eth_driver.h.

◆ ETH_TDES3_CDE

#define ETH_TDES3_CDE 0x00800000

Definition at line 395 of file f2838x_eth_driver.h.

◆ ETH_TDES3_CIC

#define ETH_TDES3_CIC 0x00030000

Definition at line 361 of file f2838x_eth_driver.h.

◆ ETH_TDES3_CPC

#define ETH_TDES3_CPC 0x0C000000

Definition at line 357 of file f2838x_eth_driver.h.

◆ ETH_TDES3_CTXT [1/3]

#define ETH_TDES3_CTXT 0x40000000

Definition at line 392 of file f2838x_eth_driver.h.

◆ ETH_TDES3_CTXT [2/3]

#define ETH_TDES3_CTXT 0x40000000

Definition at line 392 of file f2838x_eth_driver.h.

◆ ETH_TDES3_CTXT [3/3]

#define ETH_TDES3_CTXT 0x40000000

Definition at line 392 of file f2838x_eth_driver.h.

◆ ETH_TDES3_DB

#define ETH_TDES3_DB 0x00000002

Definition at line 383 of file f2838x_eth_driver.h.

◆ ETH_TDES3_EC

#define ETH_TDES3_EC 0x00000100

Definition at line 379 of file f2838x_eth_driver.h.

◆ ETH_TDES3_ED

#define ETH_TDES3_ED 0x00000008

Definition at line 381 of file f2838x_eth_driver.h.

◆ ETH_TDES3_ES

#define ETH_TDES3_ES 0x00008000

Definition at line 372 of file f2838x_eth_driver.h.

◆ ETH_TDES3_FD [1/2]

#define ETH_TDES3_FD 0x20000000

Definition at line 369 of file f2838x_eth_driver.h.

◆ ETH_TDES3_FD [2/2]

#define ETH_TDES3_FD 0x20000000

Definition at line 369 of file f2838x_eth_driver.h.

◆ ETH_TDES3_FF

#define ETH_TDES3_FF 0x00002000

Definition at line 374 of file f2838x_eth_driver.h.

◆ ETH_TDES3_FL

#define ETH_TDES3_FL 0x00007FFF

Definition at line 362 of file f2838x_eth_driver.h.

◆ ETH_TDES3_IHE

#define ETH_TDES3_IHE 0x00000001

Definition at line 384 of file f2838x_eth_driver.h.

◆ ETH_TDES3_IVLTV

#define ETH_TDES3_IVLTV 0x00020000

Definition at line 396 of file f2838x_eth_driver.h.

◆ ETH_TDES3_JT

#define ETH_TDES3_JT 0x00004000

Definition at line 373 of file f2838x_eth_driver.h.

◆ ETH_TDES3_LC

#define ETH_TDES3_LC 0x00000200

Definition at line 378 of file f2838x_eth_driver.h.

◆ ETH_TDES3_LD [1/2]

#define ETH_TDES3_LD 0x10000000

Definition at line 370 of file f2838x_eth_driver.h.

◆ ETH_TDES3_LD [2/2]

#define ETH_TDES3_LD 0x10000000

Definition at line 370 of file f2838x_eth_driver.h.

◆ ETH_TDES3_LOC

#define ETH_TDES3_LOC 0x00000800

Definition at line 376 of file f2838x_eth_driver.h.

◆ ETH_TDES3_NC

#define ETH_TDES3_NC 0x00000400

Definition at line 377 of file f2838x_eth_driver.h.

◆ ETH_TDES3_OSTC

#define ETH_TDES3_OSTC 0x08000000

Definition at line 393 of file f2838x_eth_driver.h.

◆ ETH_TDES3_OWN [1/3]

#define ETH_TDES3_OWN 0x80000000

Definition at line 391 of file f2838x_eth_driver.h.

◆ ETH_TDES3_OWN [2/3]

#define ETH_TDES3_OWN 0x80000000

Definition at line 391 of file f2838x_eth_driver.h.

◆ ETH_TDES3_OWN [3/3]

#define ETH_TDES3_OWN 0x80000000

Definition at line 391 of file f2838x_eth_driver.h.

◆ ETH_TDES3_PCE

#define ETH_TDES3_PCE 0x00001000

Definition at line 375 of file f2838x_eth_driver.h.

◆ ETH_TDES3_SAIC

#define ETH_TDES3_SAIC 0x03800000

Definition at line 358 of file f2838x_eth_driver.h.

◆ ETH_TDES3_TCMSSV

#define ETH_TDES3_TCMSSV 0x04000000

Definition at line 394 of file f2838x_eth_driver.h.

◆ ETH_TDES3_THL

#define ETH_TDES3_THL 0x00780000

Definition at line 359 of file f2838x_eth_driver.h.

◆ ETH_TDES3_TSE

#define ETH_TDES3_TSE 0x00040000

Definition at line 360 of file f2838x_eth_driver.h.

◆ ETH_TDES3_TTSS

#define ETH_TDES3_TTSS 0x00020000

Definition at line 371 of file f2838x_eth_driver.h.

◆ ETH_TDES3_UF

#define ETH_TDES3_UF 0x00000004

Definition at line 382 of file f2838x_eth_driver.h.

◆ ETH_TDES3_VLTV

#define ETH_TDES3_VLTV 0x00010000

Definition at line 397 of file f2838x_eth_driver.h.

◆ ETH_TDES3_VT

#define ETH_TDES3_VT 0x0000FFFF

Definition at line 398 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_CONTROL_R

#define ETHERNET_DMA_CH0_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_CONTROL)

Definition at line 269 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_CURRENT_APP_RXBUFFER_R

#define ETHERNET_DMA_CH0_CURRENT_APP_RXBUFFER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_CURRENT_APP_RXBUFFER)

Definition at line 283 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_CURRENT_APP_RXDESC_R

#define ETHERNET_DMA_CH0_CURRENT_APP_RXDESC_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_CURRENT_APP_RXDESC)

Definition at line 281 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_CURRENT_APP_TXBUFFER_R

#define ETHERNET_DMA_CH0_CURRENT_APP_TXBUFFER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_CURRENT_APP_TXBUFFER)

Definition at line 282 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_CURRENT_APP_TXDESC_R

#define ETHERNET_DMA_CH0_CURRENT_APP_TXDESC_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_CURRENT_APP_TXDESC)

Definition at line 280 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_INTERRUPT_ENABLE_R

#define ETHERNET_DMA_CH0_INTERRUPT_ENABLE_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_INTERRUPT_ENABLE)

Definition at line 278 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_MISS_FRAME_CNT_R

#define ETHERNET_DMA_CH0_MISS_FRAME_CNT_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_MISS_FRAME_CNT)

Definition at line 285 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_RX_CONTROL_R

#define ETHERNET_DMA_CH0_RX_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_RX_CONTROL)

Definition at line 271 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_R

#define ETHERNET_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER)

Definition at line 279 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_RXDESC_LIST_ADDRESS_R

#define ETHERNET_DMA_CH0_RXDESC_LIST_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_RXDESC_LIST_ADDRESS)

Definition at line 273 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_RXDESC_RING_LENGTH_R

#define ETHERNET_DMA_CH0_RXDESC_RING_LENGTH_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_RXDESC_RING_LENGTH)

Definition at line 277 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_RXDESC_TAIL_POINTER_R

#define ETHERNET_DMA_CH0_RXDESC_TAIL_POINTER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_RXDESC_TAIL_POINTER)

Definition at line 275 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_STATUS_R

#define ETHERNET_DMA_CH0_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_STATUS)

Definition at line 284 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_TX_CONTROL_R

#define ETHERNET_DMA_CH0_TX_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_TX_CONTROL)

Definition at line 270 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_TXDESC_LIST_ADDRESS_R

#define ETHERNET_DMA_CH0_TXDESC_LIST_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_TXDESC_LIST_ADDRESS)

Definition at line 272 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_TXDESC_RING_LENGTH_R

#define ETHERNET_DMA_CH0_TXDESC_RING_LENGTH_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_TXDESC_RING_LENGTH)

Definition at line 276 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH0_TXDESC_TAIL_POINTER_R

#define ETHERNET_DMA_CH0_TXDESC_TAIL_POINTER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH0_TXDESC_TAIL_POINTER)

Definition at line 274 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_CONTROL_R

#define ETHERNET_DMA_CH1_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_CONTROL)

Definition at line 286 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_CURRENT_APP_RXBUFFER_R

#define ETHERNET_DMA_CH1_CURRENT_APP_RXBUFFER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_CURRENT_APP_RXBUFFER)

Definition at line 300 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_CURRENT_APP_RXDESC_R

#define ETHERNET_DMA_CH1_CURRENT_APP_RXDESC_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_CURRENT_APP_RXDESC)

Definition at line 298 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_CURRENT_APP_TXBUFFER_R

#define ETHERNET_DMA_CH1_CURRENT_APP_TXBUFFER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_CURRENT_APP_TXBUFFER)

Definition at line 299 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_CURRENT_APP_TXDESC_R

#define ETHERNET_DMA_CH1_CURRENT_APP_TXDESC_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_CURRENT_APP_TXDESC)

Definition at line 297 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_INTERRUPT_ENABLE_R

#define ETHERNET_DMA_CH1_INTERRUPT_ENABLE_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_INTERRUPT_ENABLE)

Definition at line 295 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_MISS_FRAME_CNT_R

#define ETHERNET_DMA_CH1_MISS_FRAME_CNT_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_MISS_FRAME_CNT)

Definition at line 302 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_RX_CONTROL_R

#define ETHERNET_DMA_CH1_RX_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_RX_CONTROL)

Definition at line 288 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_R

#define ETHERNET_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER)

Definition at line 296 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_RXDESC_LIST_ADDRESS_R

#define ETHERNET_DMA_CH1_RXDESC_LIST_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_RXDESC_LIST_ADDRESS)

Definition at line 290 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_RXDESC_RING_LENGTH_R

#define ETHERNET_DMA_CH1_RXDESC_RING_LENGTH_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_RXDESC_RING_LENGTH)

Definition at line 294 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_RXDESC_TAIL_POINTER_R

#define ETHERNET_DMA_CH1_RXDESC_TAIL_POINTER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_RXDESC_TAIL_POINTER)

Definition at line 292 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_STATUS_R

#define ETHERNET_DMA_CH1_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_STATUS)

Definition at line 301 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_TX_CONTROL_R

#define ETHERNET_DMA_CH1_TX_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_TX_CONTROL)

Definition at line 287 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_TXDESC_LIST_ADDRESS_R

#define ETHERNET_DMA_CH1_TXDESC_LIST_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_TXDESC_LIST_ADDRESS)

Definition at line 289 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_TXDESC_RING_LENGTH_R

#define ETHERNET_DMA_CH1_TXDESC_RING_LENGTH_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_TXDESC_RING_LENGTH)

Definition at line 293 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_CH1_TXDESC_TAIL_POINTER_R

#define ETHERNET_DMA_CH1_TXDESC_TAIL_POINTER_R HWREG(EMAC_BASE + ETHERNET_O_DMA_CH1_TXDESC_TAIL_POINTER)

Definition at line 291 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_DEBUG_STATUS0_R

#define ETHERNET_DMA_DEBUG_STATUS0_R HWREG(EMAC_BASE + ETHERNET_O_DMA_DEBUG_STATUS0)

Definition at line 268 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_INTERRUPT_STATUS_R

#define ETHERNET_DMA_INTERRUPT_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_DMA_INTERRUPT_STATUS)

Definition at line 267 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_MODE_R

#define ETHERNET_DMA_MODE_R HWREG(EMAC_BASE + ETHERNET_O_DMA_MODE)

Definition at line 265 of file f2838x_eth_driver.h.

◆ ETHERNET_DMA_SYSBUS_MODE_R

#define ETHERNET_DMA_SYSBUS_MODE_R HWREG(EMAC_BASE + ETHERNET_O_DMA_SYSBUS_MODE)

Definition at line 266 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_1US_TIC_COUNTER_R

#define ETHERNET_MAC_1US_TIC_COUNTER_R HWREG(EMAC_BASE + ETHERNET_O_MAC_1US_TIC_COUNTER)

Definition at line 98 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS0_HIGH_R

#define ETHERNET_MAC_ADDRESS0_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS0_HIGH)

Definition at line 108 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS0_LOW_R

#define ETHERNET_MAC_ADDRESS0_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS0_LOW)

Definition at line 109 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS1_HIGH_R

#define ETHERNET_MAC_ADDRESS1_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS1_HIGH)

Definition at line 110 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS1_LOW_R

#define ETHERNET_MAC_ADDRESS1_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS1_LOW)

Definition at line 111 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS2_HIGH_R

#define ETHERNET_MAC_ADDRESS2_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS2_HIGH)

Definition at line 112 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS2_LOW_R

#define ETHERNET_MAC_ADDRESS2_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS2_LOW)

Definition at line 113 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS3_HIGH_R

#define ETHERNET_MAC_ADDRESS3_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS3_HIGH)

Definition at line 114 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS3_LOW_R

#define ETHERNET_MAC_ADDRESS3_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS3_LOW)

Definition at line 115 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS4_HIGH_R

#define ETHERNET_MAC_ADDRESS4_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS4_HIGH)

Definition at line 116 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS4_LOW_R

#define ETHERNET_MAC_ADDRESS4_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS4_LOW)

Definition at line 117 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS5_HIGH_R

#define ETHERNET_MAC_ADDRESS5_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS5_HIGH)

Definition at line 118 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS5_LOW_R

#define ETHERNET_MAC_ADDRESS5_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS5_LOW)

Definition at line 119 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS6_HIGH_R

#define ETHERNET_MAC_ADDRESS6_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS6_HIGH)

Definition at line 120 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS6_LOW_R

#define ETHERNET_MAC_ADDRESS6_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS6_LOW)

Definition at line 121 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS7_HIGH_R

#define ETHERNET_MAC_ADDRESS7_HIGH_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS7_HIGH)

Definition at line 122 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ADDRESS7_LOW_R

#define ETHERNET_MAC_ADDRESS7_LOW_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ADDRESS7_LOW)

Definition at line 123 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_ARP_ADDRESS_R

#define ETHERNET_MAC_ARP_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_ARP_ADDRESS)

Definition at line 107 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_AUXILIARY_CONTROL_R

#define ETHERNET_MAC_AUXILIARY_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_AUXILIARY_CONTROL)

Definition at line 250 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_R

#define ETHERNET_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS)

Definition at line 251 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_AUXILIARY_TIMESTAMP_SECONDS_R

#define ETHERNET_MAC_AUXILIARY_TIMESTAMP_SECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_AUXILIARY_TIMESTAMP_SECONDS)

Definition at line 252 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_CONFIGURATION_R

#define ETHERNET_MAC_CONFIGURATION_R HWREG(EMAC_BASE + ETHERNET_O_MAC_CONFIGURATION)

Definition at line 73 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_DEBUG_R

#define ETHERNET_MAC_DEBUG_R HWREG(EMAC_BASE + ETHERNET_O_MAC_DEBUG)

Definition at line 100 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_EXT_CONFIGURATION_R

#define ETHERNET_MAC_EXT_CONFIGURATION_R HWREG(EMAC_BASE + ETHERNET_O_MAC_EXT_CONFIGURATION)

Definition at line 74 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_HASH_TABLE_REG0_R

#define ETHERNET_MAC_HASH_TABLE_REG0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HASH_TABLE_REG0)

Definition at line 77 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_HASH_TABLE_REG1_R

#define ETHERNET_MAC_HASH_TABLE_REG1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HASH_TABLE_REG1)

Definition at line 78 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_HW_FEATURE0_R

#define ETHERNET_MAC_HW_FEATURE0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HW_FEATURE0)

Definition at line 101 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_HW_FEATURE1_R

#define ETHERNET_MAC_HW_FEATURE1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HW_FEATURE1)

Definition at line 102 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_HW_FEATURE2_R

#define ETHERNET_MAC_HW_FEATURE2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HW_FEATURE2)

Definition at line 103 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_HW_FEATURE3_R

#define ETHERNET_MAC_HW_FEATURE3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_HW_FEATURE3)

Definition at line 104 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_INNER_VLAN_INCL_R

#define ETHERNET_MAC_INNER_VLAN_INCL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_INNER_VLAN_INCL)

Definition at line 83 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_INTERRUPT_ENABLE_R

#define ETHERNET_MAC_INTERRUPT_ENABLE_R HWREG(EMAC_BASE + ETHERNET_O_MAC_INTERRUPT_ENABLE)

Definition at line 91 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_INTERRUPT_STATUS_R

#define ETHERNET_MAC_INTERRUPT_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_INTERRUPT_STATUS)

Definition at line 90 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_L3_L4_CONTROL0_R

#define ETHERNET_MAC_L3_L4_CONTROL0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_L3_L4_CONTROL0)

Definition at line 215 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_L3_L4_CONTROL1_R

#define ETHERNET_MAC_L3_L4_CONTROL1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_L3_L4_CONTROL1)

Definition at line 221 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_L3_L4_CONTROL2_R

#define ETHERNET_MAC_L3_L4_CONTROL2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_L3_L4_CONTROL2)

Definition at line 227 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_L3_L4_CONTROL3_R

#define ETHERNET_MAC_L3_L4_CONTROL3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_L3_L4_CONTROL3)

Definition at line 233 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR0_REG0_R

#define ETHERNET_MAC_LAYER3_ADDR0_REG0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR0_REG0)

Definition at line 217 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR0_REG1_R

#define ETHERNET_MAC_LAYER3_ADDR0_REG1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR0_REG1)

Definition at line 223 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR0_REG2_R

#define ETHERNET_MAC_LAYER3_ADDR0_REG2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR0_REG2)

Definition at line 229 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR0_REG3_R

#define ETHERNET_MAC_LAYER3_ADDR0_REG3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR0_REG3)

Definition at line 235 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR1_REG0_R

#define ETHERNET_MAC_LAYER3_ADDR1_REG0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR1_REG0)

Definition at line 218 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR1_REG1_R

#define ETHERNET_MAC_LAYER3_ADDR1_REG1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR1_REG1)

Definition at line 224 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR1_REG2_R

#define ETHERNET_MAC_LAYER3_ADDR1_REG2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR1_REG2)

Definition at line 230 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR1_REG3_R

#define ETHERNET_MAC_LAYER3_ADDR1_REG3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR1_REG3)

Definition at line 236 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR2_REG0_R

#define ETHERNET_MAC_LAYER3_ADDR2_REG0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR2_REG0)

Definition at line 219 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR2_REG1_R

#define ETHERNET_MAC_LAYER3_ADDR2_REG1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR2_REG1)

Definition at line 225 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR2_REG2_R

#define ETHERNET_MAC_LAYER3_ADDR2_REG2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR2_REG2)

Definition at line 231 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR2_REG3_R

#define ETHERNET_MAC_LAYER3_ADDR2_REG3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR2_REG3)

Definition at line 237 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR3_REG0_R

#define ETHERNET_MAC_LAYER3_ADDR3_REG0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR3_REG0)

Definition at line 220 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR3_REG1_R

#define ETHERNET_MAC_LAYER3_ADDR3_REG1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR3_REG1)

Definition at line 226 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR3_REG2_R

#define ETHERNET_MAC_LAYER3_ADDR3_REG2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR3_REG2)

Definition at line 232 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER3_ADDR3_REG3_R

#define ETHERNET_MAC_LAYER3_ADDR3_REG3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER3_ADDR3_REG3)

Definition at line 238 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER4_ADDRESS0_R

#define ETHERNET_MAC_LAYER4_ADDRESS0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER4_ADDRESS0)

Definition at line 216 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER4_ADDRESS1_R

#define ETHERNET_MAC_LAYER4_ADDRESS1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER4_ADDRESS1)

Definition at line 222 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER4_ADDRESS2_R

#define ETHERNET_MAC_LAYER4_ADDRESS2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER4_ADDRESS2)

Definition at line 228 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LAYER4_ADDRESS3_R

#define ETHERNET_MAC_LAYER4_ADDRESS3_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LAYER4_ADDRESS3)

Definition at line 234 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LOG_MESSAGE_INTERVAL_R

#define ETHERNET_MAC_LOG_MESSAGE_INTERVAL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LOG_MESSAGE_INTERVAL)

Definition at line 264 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LPI_CONTROL_STATUS_R

#define ETHERNET_MAC_LPI_CONTROL_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LPI_CONTROL_STATUS)

Definition at line 95 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LPI_ENTRY_TIMER_R

#define ETHERNET_MAC_LPI_ENTRY_TIMER_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LPI_ENTRY_TIMER)

Definition at line 97 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_LPI_TIMERS_CONTROL_R

#define ETHERNET_MAC_LPI_TIMERS_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_LPI_TIMERS_CONTROL)

Definition at line 96 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_MDIO_ADDRESS_R

#define ETHERNET_MAC_MDIO_ADDRESS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_MDIO_ADDRESS)

Definition at line 105 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_MDIO_DATA_R

#define ETHERNET_MAC_MDIO_DATA_R HWREG(EMAC_BASE + ETHERNET_O_MAC_MDIO_DATA)

Definition at line 106 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_PACKET_FILTER_R

#define ETHERNET_MAC_PACKET_FILTER_R HWREG(EMAC_BASE + ETHERNET_O_MAC_PACKET_FILTER)

Definition at line 75 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_PMT_CONTROL_STATUS_R

#define ETHERNET_MAC_PMT_CONTROL_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_PMT_CONTROL_STATUS)

Definition at line 93 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_PPS_CONTROL_R

#define ETHERNET_MAC_PPS_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_PPS_CONTROL)

Definition at line 259 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_PTO_CONTROL_R

#define ETHERNET_MAC_PTO_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_PTO_CONTROL)

Definition at line 260 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_Q0_TX_FLOW_CTRL_R

#define ETHERNET_MAC_Q0_TX_FLOW_CTRL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_Q0_TX_FLOW_CTRL)

Definition at line 84 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_RWK_PACKET_FILTER_R

#define ETHERNET_MAC_RWK_PACKET_FILTER_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RWK_PACKET_FILTER)

Definition at line 94 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_RX_FLOW_CTRL_R

#define ETHERNET_MAC_RX_FLOW_CTRL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RX_FLOW_CTRL)

Definition at line 85 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_RX_TX_STATUS_R

#define ETHERNET_MAC_RX_TX_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RX_TX_STATUS)

Definition at line 92 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_RXQ_CTRL0_R

#define ETHERNET_MAC_RXQ_CTRL0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RXQ_CTRL0)

Definition at line 87 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_RXQ_CTRL1_R

#define ETHERNET_MAC_RXQ_CTRL1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RXQ_CTRL1)

Definition at line 88 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_RXQ_CTRL2_R

#define ETHERNET_MAC_RXQ_CTRL2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RXQ_CTRL2)

Definition at line 89 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_RXQ_CTRL4_R

#define ETHERNET_MAC_RXQ_CTRL4_R HWREG(EMAC_BASE + ETHERNET_O_MAC_RXQ_CTRL4)

Definition at line 86 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_SOURCE_PORT_IDENTITY0_R

#define ETHERNET_MAC_SOURCE_PORT_IDENTITY0_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SOURCE_PORT_IDENTITY0)

Definition at line 261 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_SOURCE_PORT_IDENTITY1_R

#define ETHERNET_MAC_SOURCE_PORT_IDENTITY1_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SOURCE_PORT_IDENTITY1)

Definition at line 262 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_SOURCE_PORT_IDENTITY2_R

#define ETHERNET_MAC_SOURCE_PORT_IDENTITY2_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SOURCE_PORT_IDENTITY2)

Definition at line 263 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_SUB_SECOND_INCREMENT_R

#define ETHERNET_MAC_SUB_SECOND_INCREMENT_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SUB_SECOND_INCREMENT)

Definition at line 240 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_R

#define ETHERNET_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS)

Definition at line 246 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_SYSTEM_TIME_NANOSECONDS_R

#define ETHERNET_MAC_SYSTEM_TIME_NANOSECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SYSTEM_TIME_NANOSECONDS)

Definition at line 242 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_R

#define ETHERNET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE)

Definition at line 244 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_SYSTEM_TIME_SECONDS_R

#define ETHERNET_MAC_SYSTEM_TIME_SECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SYSTEM_TIME_SECONDS)

Definition at line 241 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_SYSTEM_TIME_SECONDS_UPDATE_R

#define ETHERNET_MAC_SYSTEM_TIME_SECONDS_UPDATE_R HWREG(EMAC_BASE + ETHERNET_O_MAC_SYSTEM_TIME_SECONDS_UPDATE)

Definition at line 243 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_TIMESTAMP_ADDEND_R

#define ETHERNET_MAC_TIMESTAMP_ADDEND_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_ADDEND)

Definition at line 245 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_TIMESTAMP_CONTROL_R

#define ETHERNET_MAC_TIMESTAMP_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_CONTROL)

Definition at line 239 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_TIMESTAMP_EGRESS_ASYM_CORR_R

#define ETHERNET_MAC_TIMESTAMP_EGRESS_ASYM_CORR_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_EGRESS_ASYM_CORR)

Definition at line 254 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_R

#define ETHERNET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND)

Definition at line 256 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_R

#define ETHERNET_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC)

Definition at line 258 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_TIMESTAMP_INGRESS_ASYM_CORR_R

#define ETHERNET_MAC_TIMESTAMP_INGRESS_ASYM_CORR_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_INGRESS_ASYM_CORR)

Definition at line 253 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_R

#define ETHERNET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND)

Definition at line 255 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_R

#define ETHERNET_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC)

Definition at line 257 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_TIMESTAMP_STATUS_R

#define ETHERNET_MAC_TIMESTAMP_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TIMESTAMP_STATUS)

Definition at line 247 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_R

#define ETHERNET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS)

Definition at line 248 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_TX_TIMESTAMP_STATUS_SECONDS_R

#define ETHERNET_MAC_TX_TIMESTAMP_STATUS_SECONDS_R HWREG(EMAC_BASE + ETHERNET_O_MAC_TX_TIMESTAMP_STATUS_SECONDS)

Definition at line 249 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_VERSION_R

#define ETHERNET_MAC_VERSION_R HWREG(EMAC_BASE + ETHERNET_O_MAC_VERSION)

Definition at line 99 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_VLAN_HASH_TABLE_R

#define ETHERNET_MAC_VLAN_HASH_TABLE_R HWREG(EMAC_BASE + ETHERNET_O_MAC_VLAN_HASH_TABLE)

Definition at line 81 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_VLAN_INCL_R

#define ETHERNET_MAC_VLAN_INCL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_VLAN_INCL)

Definition at line 82 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_VLAN_TAG_CTRL_R

#define ETHERNET_MAC_VLAN_TAG_CTRL_R HWREG(EMAC_BASE + ETHERNET_O_MAC_VLAN_TAG_CTRL)

Definition at line 79 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_VLAN_TAG_DATA_R

#define ETHERNET_MAC_VLAN_TAG_DATA_R HWREG(EMAC_BASE + ETHERNET_O_MAC_VLAN_TAG_DATA)

Definition at line 80 of file f2838x_eth_driver.h.

◆ ETHERNET_MAC_WATCHDOG_TIMEOUT_R

#define ETHERNET_MAC_WATCHDOG_TIMEOUT_R HWREG(EMAC_BASE + ETHERNET_O_MAC_WATCHDOG_TIMEOUT)

Definition at line 76 of file f2838x_eth_driver.h.

◆ ETHERNET_MMC_CONTROL_R

#define ETHERNET_MMC_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MMC_CONTROL)

Definition at line 124 of file f2838x_eth_driver.h.

◆ ETHERNET_MMC_IPC_RX_INTERRUPT_MASK_R

#define ETHERNET_MMC_IPC_RX_INTERRUPT_MASK_R HWREG(EMAC_BASE + ETHERNET_O_MMC_IPC_RX_INTERRUPT_MASK)

Definition at line 185 of file f2838x_eth_driver.h.

◆ ETHERNET_MMC_IPC_RX_INTERRUPT_R

#define ETHERNET_MMC_IPC_RX_INTERRUPT_R HWREG(EMAC_BASE + ETHERNET_O_MMC_IPC_RX_INTERRUPT)

Definition at line 186 of file f2838x_eth_driver.h.

◆ ETHERNET_MMC_RX_INTERRUPT_MASK_R

#define ETHERNET_MMC_RX_INTERRUPT_MASK_R HWREG(EMAC_BASE + ETHERNET_O_MMC_RX_INTERRUPT_MASK)

Definition at line 127 of file f2838x_eth_driver.h.

◆ ETHERNET_MMC_RX_INTERRUPT_R

#define ETHERNET_MMC_RX_INTERRUPT_R HWREG(EMAC_BASE + ETHERNET_O_MMC_RX_INTERRUPT)

Definition at line 125 of file f2838x_eth_driver.h.

◆ ETHERNET_MMC_TX_INTERRUPT_MASK_R

#define ETHERNET_MMC_TX_INTERRUPT_MASK_R HWREG(EMAC_BASE + ETHERNET_O_MMC_TX_INTERRUPT_MASK)

Definition at line 128 of file f2838x_eth_driver.h.

◆ ETHERNET_MMC_TX_INTERRUPT_R

#define ETHERNET_MMC_TX_INTERRUPT_R HWREG(EMAC_BASE + ETHERNET_O_MMC_TX_INTERRUPT)

Definition at line 126 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_DBG_CTL_R

#define ETHERNET_MTL_DBG_CTL_R HWREG(EMAC_BASE + ETHERNET_O_MTL_DBG_CTL)

Definition at line 304 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_DBG_STS_R

#define ETHERNET_MTL_DBG_STS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_DBG_STS)

Definition at line 305 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_FIFO_DEBUG_DATA_R

#define ETHERNET_MTL_FIFO_DEBUG_DATA_R HWREG(EMAC_BASE + ETHERNET_O_MTL_FIFO_DEBUG_DATA)

Definition at line 306 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_INTERRUPT_STATUS_R

#define ETHERNET_MTL_INTERRUPT_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_INTERRUPT_STATUS)

Definition at line 307 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_OPERATION_MODE_R

#define ETHERNET_MTL_OPERATION_MODE_R HWREG(EMAC_BASE + ETHERNET_O_MTL_OPERATION_MODE)

Definition at line 303 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_Q0_INTERRUPT_CONTROL_STATUS_R

#define ETHERNET_MTL_Q0_INTERRUPT_CONTROL_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_Q0_INTERRUPT_CONTROL_STATUS)

Definition at line 314 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_Q1_INTERRUPT_CONTROL_STATUS_R

#define ETHERNET_MTL_Q1_INTERRUPT_CONTROL_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_Q1_INTERRUPT_CONTROL_STATUS)

Definition at line 324 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_RXQ0_CONTROL_R

#define ETHERNET_MTL_RXQ0_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ0_CONTROL)

Definition at line 318 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_RXQ0_DEBUG_R

#define ETHERNET_MTL_RXQ0_DEBUG_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ0_DEBUG)

Definition at line 317 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_R

#define ETHERNET_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT)

Definition at line 316 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_RXQ0_OPERATION_MODE_R

#define ETHERNET_MTL_RXQ0_OPERATION_MODE_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ0_OPERATION_MODE)

Definition at line 315 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_RXQ1_CONTROL_R

#define ETHERNET_MTL_RXQ1_CONTROL_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ1_CONTROL)

Definition at line 328 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_RXQ1_DEBUG_R

#define ETHERNET_MTL_RXQ1_DEBUG_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ1_DEBUG)

Definition at line 327 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_R

#define ETHERNET_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT)

Definition at line 326 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_RXQ1_OPERATION_MODE_R

#define ETHERNET_MTL_RXQ1_OPERATION_MODE_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ1_OPERATION_MODE)

Definition at line 325 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_RXQ_DMA_MAP0_R

#define ETHERNET_MTL_RXQ_DMA_MAP0_R HWREG(EMAC_BASE + ETHERNET_O_MTL_RXQ_DMA_MAP0)

Definition at line 308 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_TXQ0_DEBUG_R

#define ETHERNET_MTL_TXQ0_DEBUG_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ0_DEBUG)

Definition at line 311 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_TXQ0_ETS_STATUS_R

#define ETHERNET_MTL_TXQ0_ETS_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ0_ETS_STATUS)

Definition at line 312 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_TXQ0_OPERATION_MODE_R

#define ETHERNET_MTL_TXQ0_OPERATION_MODE_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ0_OPERATION_MODE)

Definition at line 309 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_TXQ0_QUANTUM_WEIGHT_R

#define ETHERNET_MTL_TXQ0_QUANTUM_WEIGHT_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ0_QUANTUM_WEIGHT)

Definition at line 313 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_TXQ0_UNDERFLOW_R

#define ETHERNET_MTL_TXQ0_UNDERFLOW_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ0_UNDERFLOW)

Definition at line 310 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_TXQ1_DEBUG_R

#define ETHERNET_MTL_TXQ1_DEBUG_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ1_DEBUG)

Definition at line 321 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_TXQ1_ETS_STATUS_R

#define ETHERNET_MTL_TXQ1_ETS_STATUS_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ1_ETS_STATUS)

Definition at line 322 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_TXQ1_OPERATION_MODE_R

#define ETHERNET_MTL_TXQ1_OPERATION_MODE_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ1_OPERATION_MODE)

Definition at line 319 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_TXQ1_QUANTUM_WEIGHT_R

#define ETHERNET_MTL_TXQ1_QUANTUM_WEIGHT_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ1_QUANTUM_WEIGHT)

Definition at line 323 of file f2838x_eth_driver.h.

◆ ETHERNET_MTL_TXQ1_UNDERFLOW_R

#define ETHERNET_MTL_TXQ1_UNDERFLOW_R HWREG(EMAC_BASE + ETHERNET_O_MTL_TXQ1_UNDERFLOW)

Definition at line 320 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD)

Definition at line 171 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_128TO255OCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_RX_128TO255OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_128TO255OCTETS_PACKETS_GOOD_BAD)

Definition at line 168 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_256TO511OCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_RX_256TO511OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_256TO511OCTETS_PACKETS_GOOD_BAD)

Definition at line 169 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_512TO1023OCTETS_PACKETS_GOOD_BAD)

Definition at line 170 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_64OCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_RX_64OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_64OCTETS_PACKETS_GOOD_BAD)

Definition at line 166 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_65TO127OCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_RX_65TO127OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_65TO127OCTETS_PACKETS_GOOD_BAD)

Definition at line 167 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_ALIGNMENT_ERROR_PACKETS_R

#define ETHERNET_RX_ALIGNMENT_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_ALIGNMENT_ERROR_PACKETS)

Definition at line 161 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_BROADCAST_PACKETS_GOOD_R

#define ETHERNET_RX_BROADCAST_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_BROADCAST_PACKETS_GOOD)

Definition at line 158 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_CONTROL_PACKETS_GOOD_R

#define ETHERNET_RX_CONTROL_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_CONTROL_PACKETS_GOOD)

Definition at line 180 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_CRC_ERROR_PACKETS_R

#define ETHERNET_RX_CRC_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_CRC_ERROR_PACKETS)

Definition at line 160 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_FIFO_OVERFLOW_PACKETS_R

#define ETHERNET_RX_FIFO_OVERFLOW_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_FIFO_OVERFLOW_PACKETS)

Definition at line 176 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_JABBER_ERROR_PACKETS_R

#define ETHERNET_RX_JABBER_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_JABBER_ERROR_PACKETS)

Definition at line 163 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_LENGTH_ERROR_PACKETS_R

#define ETHERNET_RX_LENGTH_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_LENGTH_ERROR_PACKETS)

Definition at line 173 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_LPI_TRAN_CNTR_R

#define ETHERNET_RX_LPI_TRAN_CNTR_R HWREG(EMAC_BASE + ETHERNET_O_RX_LPI_TRAN_CNTR)

Definition at line 184 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_LPI_USEC_CNTR_R

#define ETHERNET_RX_LPI_USEC_CNTR_R HWREG(EMAC_BASE + ETHERNET_O_RX_LPI_USEC_CNTR)

Definition at line 183 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_MULTICAST_PACKETS_GOOD_R

#define ETHERNET_RX_MULTICAST_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_MULTICAST_PACKETS_GOOD)

Definition at line 159 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_OCTET_COUNT_GOOD_BAD_R

#define ETHERNET_RX_OCTET_COUNT_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_OCTET_COUNT_GOOD_BAD)

Definition at line 156 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_OCTET_COUNT_GOOD_R

#define ETHERNET_RX_OCTET_COUNT_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_OCTET_COUNT_GOOD)

Definition at line 157 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_OUT_OF_RANGE_TYPE_PACKETS_R

#define ETHERNET_RX_OUT_OF_RANGE_TYPE_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_OUT_OF_RANGE_TYPE_PACKETS)

Definition at line 174 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_OVERSIZE_PACKETS_GOOD_R

#define ETHERNET_RX_OVERSIZE_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_OVERSIZE_PACKETS_GOOD)

Definition at line 165 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_PACKETS_COUNT_GOOD_BAD_R

#define ETHERNET_RX_PACKETS_COUNT_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_PACKETS_COUNT_GOOD_BAD)

Definition at line 155 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_PAUSE_PACKETS_R

#define ETHERNET_RX_PAUSE_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_PAUSE_PACKETS)

Definition at line 175 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_RECEIVE_ERROR_PACKETS_R

#define ETHERNET_RX_RECEIVE_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_RECEIVE_ERROR_PACKETS)

Definition at line 179 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_RUNT_ERROR_PACKETS_R

#define ETHERNET_RX_RUNT_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_RUNT_ERROR_PACKETS)

Definition at line 162 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_UNDERSIZE_PACKETS_GOOD_R

#define ETHERNET_RX_UNDERSIZE_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_UNDERSIZE_PACKETS_GOOD)

Definition at line 164 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_UNICAST_PACKETS_GOOD_R

#define ETHERNET_RX_UNICAST_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_RX_UNICAST_PACKETS_GOOD)

Definition at line 172 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_VLAN_PACKETS_GOOD_BAD_R

#define ETHERNET_RX_VLAN_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_RX_VLAN_PACKETS_GOOD_BAD)

Definition at line 177 of file f2838x_eth_driver.h.

◆ ETHERNET_RX_WATCHDOG_ERROR_PACKETS_R

#define ETHERNET_RX_WATCHDOG_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RX_WATCHDOG_ERROR_PACKETS)

Definition at line 178 of file f2838x_eth_driver.h.

◆ ETHERNET_RXICMP_ERROR_OCTETS_R

#define ETHERNET_RXICMP_ERROR_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXICMP_ERROR_OCTETS)

Definition at line 214 of file f2838x_eth_driver.h.

◆ ETHERNET_RXICMP_ERROR_PACKETS_R

#define ETHERNET_RXICMP_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXICMP_ERROR_PACKETS)

Definition at line 200 of file f2838x_eth_driver.h.

◆ ETHERNET_RXICMP_GOOD_OCTETS_R

#define ETHERNET_RXICMP_GOOD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXICMP_GOOD_OCTETS)

Definition at line 213 of file f2838x_eth_driver.h.

◆ ETHERNET_RXICMP_GOOD_PACKETS_R

#define ETHERNET_RXICMP_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXICMP_GOOD_PACKETS)

Definition at line 199 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV4_FRAGMENTED_OCTETS_R

#define ETHERNET_RXIPV4_FRAGMENTED_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_FRAGMENTED_OCTETS)

Definition at line 204 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV4_FRAGMENTED_PACKETS_R

#define ETHERNET_RXIPV4_FRAGMENTED_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_FRAGMENTED_PACKETS)

Definition at line 190 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV4_GOOD_OCTETS_R

#define ETHERNET_RXIPV4_GOOD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_GOOD_OCTETS)

Definition at line 201 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV4_GOOD_PACKETS_R

#define ETHERNET_RXIPV4_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_GOOD_PACKETS)

Definition at line 187 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV4_HEADER_ERROR_OCTETS_R

#define ETHERNET_RXIPV4_HEADER_ERROR_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_HEADER_ERROR_OCTETS)

Definition at line 202 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV4_HEADER_ERROR_PACKETS_R

#define ETHERNET_RXIPV4_HEADER_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_HEADER_ERROR_PACKETS)

Definition at line 188 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV4_NO_PAYLOAD_OCTETS_R

#define ETHERNET_RXIPV4_NO_PAYLOAD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_NO_PAYLOAD_OCTETS)

Definition at line 203 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV4_NO_PAYLOAD_PACKETS_R

#define ETHERNET_RXIPV4_NO_PAYLOAD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_NO_PAYLOAD_PACKETS)

Definition at line 189 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_R

#define ETHERNET_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS)

Definition at line 205 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_R

#define ETHERNET_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS)

Definition at line 191 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV6_GOOD_OCTETS_R

#define ETHERNET_RXIPV6_GOOD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_GOOD_OCTETS)

Definition at line 206 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV6_GOOD_PACKETS_R

#define ETHERNET_RXIPV6_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_GOOD_PACKETS)

Definition at line 192 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV6_HEADER_ERROR_OCTETS_R

#define ETHERNET_RXIPV6_HEADER_ERROR_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_HEADER_ERROR_OCTETS)

Definition at line 207 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV6_HEADER_ERROR_PACKETS_R

#define ETHERNET_RXIPV6_HEADER_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_HEADER_ERROR_PACKETS)

Definition at line 193 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV6_NO_PAYLOAD_OCTETS_R

#define ETHERNET_RXIPV6_NO_PAYLOAD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_NO_PAYLOAD_OCTETS)

Definition at line 208 of file f2838x_eth_driver.h.

◆ ETHERNET_RXIPV6_NO_PAYLOAD_PACKETS_R

#define ETHERNET_RXIPV6_NO_PAYLOAD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXIPV6_NO_PAYLOAD_PACKETS)

Definition at line 194 of file f2838x_eth_driver.h.

◆ ETHERNET_RXTCP_ERROR_OCTETS_R

#define ETHERNET_RXTCP_ERROR_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXTCP_ERROR_OCTETS)

Definition at line 212 of file f2838x_eth_driver.h.

◆ ETHERNET_RXTCP_ERROR_PACKETS_R

#define ETHERNET_RXTCP_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXTCP_ERROR_PACKETS)

Definition at line 198 of file f2838x_eth_driver.h.

◆ ETHERNET_RXTCP_GOOD_OCTETS_R

#define ETHERNET_RXTCP_GOOD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXTCP_GOOD_OCTETS)

Definition at line 211 of file f2838x_eth_driver.h.

◆ ETHERNET_RXTCP_GOOD_PACKETS_R

#define ETHERNET_RXTCP_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXTCP_GOOD_PACKETS)

Definition at line 197 of file f2838x_eth_driver.h.

◆ ETHERNET_RXUDP_ERROR_OCTETS_R

#define ETHERNET_RXUDP_ERROR_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXUDP_ERROR_OCTETS)

Definition at line 210 of file f2838x_eth_driver.h.

◆ ETHERNET_RXUDP_ERROR_PACKETS_R

#define ETHERNET_RXUDP_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXUDP_ERROR_PACKETS)

Definition at line 196 of file f2838x_eth_driver.h.

◆ ETHERNET_RXUDP_GOOD_OCTETS_R

#define ETHERNET_RXUDP_GOOD_OCTETS_R HWREG(EMAC_BASE + ETHERNET_O_RXUDP_GOOD_OCTETS)

Definition at line 209 of file f2838x_eth_driver.h.

◆ ETHERNET_RXUDP_GOOD_PACKETS_R

#define ETHERNET_RXUDP_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_RXUDP_GOOD_PACKETS)

Definition at line 195 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD)

Definition at line 138 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_128TO255OCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_TX_128TO255OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_128TO255OCTETS_PACKETS_GOOD_BAD)

Definition at line 135 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_256TO511OCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_TX_256TO511OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_256TO511OCTETS_PACKETS_GOOD_BAD)

Definition at line 136 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_512TO1023OCTETS_PACKETS_GOOD_BAD)

Definition at line 137 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_64OCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_TX_64OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_64OCTETS_PACKETS_GOOD_BAD)

Definition at line 133 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_65TO127OCTETS_PACKETS_GOOD_BAD_R

#define ETHERNET_TX_65TO127OCTETS_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_65TO127OCTETS_PACKETS_GOOD_BAD)

Definition at line 134 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_BROADCAST_PACKETS_GOOD_BAD_R

#define ETHERNET_TX_BROADCAST_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_BROADCAST_PACKETS_GOOD_BAD)

Definition at line 141 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_BROADCAST_PACKETS_GOOD_R

#define ETHERNET_TX_BROADCAST_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_BROADCAST_PACKETS_GOOD)

Definition at line 131 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_CARRIER_ERROR_PACKETS_R

#define ETHERNET_TX_CARRIER_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_CARRIER_ERROR_PACKETS)

Definition at line 148 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_DEFERRED_PACKETS_R

#define ETHERNET_TX_DEFERRED_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_DEFERRED_PACKETS)

Definition at line 145 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_EXCESSIVE_COLLISION_PACKETS_R

#define ETHERNET_TX_EXCESSIVE_COLLISION_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_EXCESSIVE_COLLISION_PACKETS)

Definition at line 147 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_EXCESSIVE_DEFERRAL_ERROR_R

#define ETHERNET_TX_EXCESSIVE_DEFERRAL_ERROR_R HWREG(EMAC_BASE + ETHERNET_O_TX_EXCESSIVE_DEFERRAL_ERROR)

Definition at line 151 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_LATE_COLLISION_PACKETS_R

#define ETHERNET_TX_LATE_COLLISION_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_LATE_COLLISION_PACKETS)

Definition at line 146 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_LPI_TRAN_CNTR_R

#define ETHERNET_TX_LPI_TRAN_CNTR_R HWREG(EMAC_BASE + ETHERNET_O_TX_LPI_TRAN_CNTR)

Definition at line 182 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_LPI_USEC_CNTR_R

#define ETHERNET_TX_LPI_USEC_CNTR_R HWREG(EMAC_BASE + ETHERNET_O_TX_LPI_USEC_CNTR)

Definition at line 181 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_MULTICAST_PACKETS_GOOD_BAD_R

#define ETHERNET_TX_MULTICAST_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_MULTICAST_PACKETS_GOOD_BAD)

Definition at line 140 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_MULTICAST_PACKETS_GOOD_R

#define ETHERNET_TX_MULTICAST_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_MULTICAST_PACKETS_GOOD)

Definition at line 132 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_MULTIPLE_COLLISION_GOOD_PACKETS_R

#define ETHERNET_TX_MULTIPLE_COLLISION_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_MULTIPLE_COLLISION_GOOD_PACKETS)

Definition at line 144 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_OCTET_COUNT_GOOD_BAD_R

#define ETHERNET_TX_OCTET_COUNT_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_OCTET_COUNT_GOOD_BAD)

Definition at line 129 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_OCTET_COUNT_GOOD_R

#define ETHERNET_TX_OCTET_COUNT_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_OCTET_COUNT_GOOD)

Definition at line 149 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_OSIZE_PACKETS_GOOD_R

#define ETHERNET_TX_OSIZE_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_OSIZE_PACKETS_GOOD)

Definition at line 154 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_PACKET_COUNT_GOOD_BAD_R

#define ETHERNET_TX_PACKET_COUNT_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_PACKET_COUNT_GOOD_BAD)

Definition at line 130 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_PACKET_COUNT_GOOD_R

#define ETHERNET_TX_PACKET_COUNT_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_PACKET_COUNT_GOOD)

Definition at line 150 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_PAUSE_PACKETS_R

#define ETHERNET_TX_PAUSE_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_PAUSE_PACKETS)

Definition at line 152 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_SINGLE_COLLISION_GOOD_PACKETS_R

#define ETHERNET_TX_SINGLE_COLLISION_GOOD_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_SINGLE_COLLISION_GOOD_PACKETS)

Definition at line 143 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_UNDERFLOW_ERROR_PACKETS_R

#define ETHERNET_TX_UNDERFLOW_ERROR_PACKETS_R HWREG(EMAC_BASE + ETHERNET_O_TX_UNDERFLOW_ERROR_PACKETS)

Definition at line 142 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_UNICAST_PACKETS_GOOD_BAD_R

#define ETHERNET_TX_UNICAST_PACKETS_GOOD_BAD_R HWREG(EMAC_BASE + ETHERNET_O_TX_UNICAST_PACKETS_GOOD_BAD)

Definition at line 139 of file f2838x_eth_driver.h.

◆ ETHERNET_TX_VLAN_PACKETS_GOOD_R

#define ETHERNET_TX_VLAN_PACKETS_GOOD_R HWREG(EMAC_BASE + ETHERNET_O_TX_VLAN_PACKETS_GOOD)

Definition at line 153 of file f2838x_eth_driver.h.

◆ ETHERNETSS_CTRLSTS_R

#define ETHERNETSS_CTRLSTS_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_CTRLSTS)

Definition at line 332 of file f2838x_eth_driver.h.

◆ ETHERNETSS_IPREVNUM_R

#define ETHERNETSS_IPREVNUM_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_IPREVNUM)

Definition at line 331 of file f2838x_eth_driver.h.

◆ ETHERNETSS_PTP_TSRH_R

#define ETHERNETSS_PTP_TSRH_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTP_TSRH)

Definition at line 340 of file f2838x_eth_driver.h.

◆ ETHERNETSS_PTP_TSRL_R

#define ETHERNETSS_PTP_TSRL_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTP_TSRL)

Definition at line 339 of file f2838x_eth_driver.h.

◆ ETHERNETSS_PTP_TSWH_R

#define ETHERNETSS_PTP_TSWH_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTP_TSWH)

Definition at line 342 of file f2838x_eth_driver.h.

◆ ETHERNETSS_PTP_TSWL_R

#define ETHERNETSS_PTP_TSWL_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTP_TSWL)

Definition at line 341 of file f2838x_eth_driver.h.

◆ ETHERNETSS_PTPPPSR0_R

#define ETHERNETSS_PTPPPSR0_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPPPSR0)

Definition at line 337 of file f2838x_eth_driver.h.

◆ ETHERNETSS_PTPPPSR1_R

#define ETHERNETSS_PTPPPSR1_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPPPSR1)

Definition at line 338 of file f2838x_eth_driver.h.

◆ ETHERNETSS_PTPTSSWTRIG0_R

#define ETHERNETSS_PTPTSSWTRIG0_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPTSSWTRIG0)

Definition at line 335 of file f2838x_eth_driver.h.

◆ ETHERNETSS_PTPTSSWTRIG1_R

#define ETHERNETSS_PTPTSSWTRIG1_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPTSSWTRIG1)

Definition at line 336 of file f2838x_eth_driver.h.

◆ ETHERNETSS_PTPTSTRIGSEL0_R

#define ETHERNETSS_PTPTSTRIGSEL0_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPTSTRIGSEL0)

Definition at line 333 of file f2838x_eth_driver.h.

◆ ETHERNETSS_PTPTSTRIGSEL1_R

#define ETHERNETSS_PTPTSTRIGSEL1_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_PTPTSTRIGSEL1)

Definition at line 334 of file f2838x_eth_driver.h.

◆ ETHERNETSS_REVMII_CTRL_R

#define ETHERNETSS_REVMII_CTRL_R HWREG(EMAC_SS_BASE + ETHERNETSS_O_REVMII_CTRL)

Definition at line 343 of file f2838x_eth_driver.h.

◆ F2838X_ETH_IRQ_PRIORITY

#define F2838X_ETH_IRQ_PRIORITY 6

Definition at line 67 of file f2838x_eth_driver.h.

◆ F2838X_ETH_RX_BUFFER_COUNT

#define F2838X_ETH_RX_BUFFER_COUNT 4

Definition at line 53 of file f2838x_eth_driver.h.

◆ F2838X_ETH_RX_BUFFER_SIZE

#define F2838X_ETH_RX_BUFFER_SIZE 1536

Definition at line 60 of file f2838x_eth_driver.h.

◆ F2838X_ETH_TX_BUFFER_COUNT

#define F2838X_ETH_TX_BUFFER_COUNT 2

Definition at line 39 of file f2838x_eth_driver.h.

◆ F2838X_ETH_TX_BUFFER_SIZE

#define F2838X_ETH_TX_BUFFER_SIZE 1536

Definition at line 46 of file f2838x_eth_driver.h.

Function Documentation

◆ f2838xEthCalcCrc()

uint32_t f2838xEthCalcCrc	(	const void *	data,
		size_t	length
	)

CRC calculation.

Parameters

[in]	data	Pointer to the data over which to calculate the CRC
[in]	length	Number of bytes to process

Returns: Resulting CRC value

Definition at line 929 of file f2838x_eth_driver.c.

◆ f2838xEthDisableIrq()

void f2838xEthDisableIrq ( NetInterface * interface )

Disable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 395 of file f2838x_eth_driver.c.

◆ f2838xEthEnableIrq()

void f2838xEthEnableIrq ( NetInterface * interface )

Enable interrupts.

Parameters

[in] interface Underlying network interface

Definition at line 362 of file f2838x_eth_driver.c.

◆ f2838xEthEventHandler()

void f2838xEthEventHandler ( NetInterface * interface )

TMS320F2838xD Ethernet MAC event handler.

Parameters

[in] interface Underlying network interface

Definition at line 480 of file f2838x_eth_driver.c.

◆ f2838xEthInit()

error_t f2838xEthInit ( NetInterface * interface )

TMS320F2838xD Ethernet MAC initialization.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 120 of file f2838x_eth_driver.c.

◆ f2838xEthInitDmaDesc()

void f2838xEthInitDmaDesc ( NetInterface * interface )

Initialize DMA descriptor lists.

Parameters

[in] interface Underlying network interface

Definition at line 286 of file f2838x_eth_driver.c.

◆ f2838xEthInitGpio()

void f2838xEthInitGpio ( NetInterface * interface )

GPIO configuration.

Parameters

[in] interface Underlying network interface

Definition at line 273 of file f2838x_eth_driver.c.

◆ f2838xEthIrqHandler()

void f2838xEthIrqHandler ( void )

TMS320F2838xD Ethernet MAC interrupt service routine.

Definition at line 427 of file f2838x_eth_driver.c.

◆ f2838xEthReadPhyReg()

uint16_t f2838xEthReadPhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr
	)

Read PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)

Returns: Register value

Definition at line 877 of file f2838x_eth_driver.c.

◆ f2838xEthReceivePacket()

error_t f2838xEthReceivePacket ( NetInterface * interface )

Receive a packet.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 567 of file f2838x_eth_driver.c.

◆ f2838xEthSendPacket()

error_t f2838xEthSendPacket	(	NetInterface *	interface,
		const NetBuffer *	buffer,
		size_t	offset,
		NetTxAncillary *	ancillary
	)

Send a packet.

Parameters

[in]	interface	Underlying network interface
[in]	buffer	Multi-part buffer containing the data to send
[in]	offset	Offset to the first data byte
[in]	ancillary	Additional options passed to the stack along with the packet

Returns: Error code

Definition at line 505 of file f2838x_eth_driver.c.

◆ f2838xEthTick()

void f2838xEthTick ( NetInterface * interface )

TMS320F2838xD Ethernet MAC timer handler.

This routine is periodically called by the TCP/IP stack to handle periodic operations such as polling the link state

Parameters

[in] interface Underlying network interface

Definition at line 337 of file f2838x_eth_driver.c.

◆ f2838xEthUpdateMacAddrFilter()

error_t f2838xEthUpdateMacAddrFilter ( NetInterface * interface )

Configure MAC address filtering.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 642 of file f2838x_eth_driver.c.

◆ f2838xEthUpdateMacConfig()

error_t f2838xEthUpdateMacConfig ( NetInterface * interface )

Adjust MAC configuration parameters for proper operation.

Parameters

[in] interface Underlying network interface

Returns: Error code

Definition at line 788 of file f2838x_eth_driver.c.

◆ f2838xEthWritePhyReg()

void f2838xEthWritePhyReg	(	uint8_t	opcode,
		uint8_t	phyAddr,
		uint8_t	regAddr,
		uint16_t	data
	)

Write PHY register.

Parameters

[in]	opcode	Access type (2 bits)
[in]	phyAddr	PHY address (5 bits)
[in]	regAddr	Register address (5 bits)
[in]	data	Register value

Definition at line 831 of file f2838x_eth_driver.c.

Variable Documentation

◆ f2838xEthDriver

const NicDriver f2838xEthDriver

extern

TMS320F2838xD Ethernet MAC driver.

Definition at line 93 of file f2838x_eth_driver.c.

Data Structures

Macros

Functions

Variables

Detailed Description

License

Macro Definition Documentation

◆ ETH_RDES0_BUF1AP

◆ ETH_RDES0_IVT

◆ ETH_RDES0_OVT

◆ ETH_RDES0_RTSL

◆ ETH_RDES1_IPCB

◆ ETH_RDES1_IPCE

◆ ETH_RDES1_IPHE

◆ ETH_RDES1_IPV4

◆ ETH_RDES1_IPV6

◆ ETH_RDES1_OPC

◆ ETH_RDES1_PFT

◆ ETH_RDES1_PMT

◆ ETH_RDES1_PT

◆ ETH_RDES1_PV

◆ ETH_RDES1_RTSH

◆ ETH_RDES1_TD

◆ ETH_RDES1_TSA

◆ ETH_RDES2_ARPRN

◆ ETH_RDES2_BUF2AP

◆ ETH_RDES2_DAF

◆ ETH_RDES2_HF

◆ ETH_RDES2_L3FM

◆ ETH_RDES2_L3L4FM

◆ ETH_RDES2_L4FM

◆ ETH_RDES2_MADRM

◆ ETH_RDES2_SAF

◆ ETH_RDES2_VF

◆ ETH_RDES3_BUF1V

◆ ETH_RDES3_BUF2V

◆ ETH_RDES3_CE

◆ ETH_RDES3_CTXT [1/2]

◆ ETH_RDES3_CTXT [2/2]

◆ ETH_RDES3_DE

◆ ETH_RDES3_ES

◆ ETH_RDES3_FD

◆ ETH_RDES3_GP

◆ ETH_RDES3_IOC

◆ ETH_RDES3_LD

◆ ETH_RDES3_LT

◆ ETH_RDES3_OE

◆ ETH_RDES3_OWN [1/3]

◆ ETH_RDES3_OWN [2/3]

◆ ETH_RDES3_OWN [3/3]

◆ ETH_RDES3_PL

◆ ETH_RDES3_RE

◆ ETH_RDES3_RS0V

◆ ETH_RDES3_RS1V

◆ ETH_RDES3_RS2V

◆ ETH_RDES3_RWT

◆ ETH_TDES0_BUF1AP

◆ ETH_TDES0_TTSL [1/2]

◆ ETH_TDES0_TTSL [2/2]

◆ ETH_TDES1_BUF2AP

◆ ETH_TDES1_TTSH [1/2]

◆ ETH_TDES1_TTSH [2/2]

◆ ETH_TDES2_B1L

◆ ETH_TDES2_B2L

◆ ETH_TDES2_IOC

◆ ETH_TDES2_IVT

◆ ETH_TDES2_MSS

◆ ETH_TDES2_TTSE

◆ ETH_TDES2_VTIR

◆ ETH_TDES3_CC

◆ ETH_TDES3_CDE

◆ ETH_TDES3_CIC

◆ ETH_TDES3_CPC

◆ ETH_TDES3_CTXT [1/3]

◆ ETH_TDES3_CTXT [2/3]

◆ ETH_TDES3_CTXT [3/3]

◆ ETH_TDES3_DB

◆ ETH_TDES3_EC

◆ ETH_TDES3_ED

◆ ETH_TDES3_ES