fm3_eth2_driver.h
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1 /**
2  * @file fm3_eth2_driver.h
3  * @brief Cypress FM3 Ethernet MAC driver (ETHER1 instance)
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _FM3_ETH2_DRIVER_H
32 #define _FM3_ETH2_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef FM3_ETH2_TX_BUFFER_COUNT
39  #define FM3_ETH2_TX_BUFFER_COUNT 3
40 #elif (FM3_ETH2_TX_BUFFER_COUNT < 1)
41  #error FM3_ETH2_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef FM3_ETH2_TX_BUFFER_SIZE
46  #define FM3_ETH2_TX_BUFFER_SIZE 1536
47 #elif (FM3_ETH2_TX_BUFFER_SIZE != 1536)
48  #error FM3_ETH2_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef FM3_ETH2_RX_BUFFER_COUNT
53  #define FM3_ETH2_RX_BUFFER_COUNT 6
54 #elif (FM3_ETH2_RX_BUFFER_COUNT < 1)
55  #error FM3_ETH2_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef FM3_ETH2_RX_BUFFER_SIZE
60  #define FM3_ETH2_RX_BUFFER_SIZE 1536
61 #elif (FM3_ETH2_RX_BUFFER_SIZE != 1536)
62  #error FM3_ETH2_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef FM3_ETH2_IRQ_PRIORITY_GROUPING
67  #define FM3_ETH2_IRQ_PRIORITY_GROUPING 3
68 #elif (FM3_ETH2_IRQ_PRIORITY_GROUPING < 0)
69  #error FM3_ETH2_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef FM3_ETH2_IRQ_GROUP_PRIORITY
74  #define FM3_ETH2_IRQ_GROUP_PRIORITY 12
75 #elif (FM3_ETH2_IRQ_GROUP_PRIORITY < 0)
76  #error FM3_ETH2_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef FM3_ETH2_IRQ_SUB_PRIORITY
81  #define FM3_ETH2_IRQ_SUB_PRIORITY 0
82 #elif (FM3_ETH2_IRQ_SUB_PRIORITY < 0)
83  #error FM3_ETH2_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //SR register
87 #define ETH_SR_GLPII 0x40000000
88 #define ETH_SR_TTI 0x20000000
89 #define ETH_SR_GPI 0x10000000
90 #define ETH_SR_GMI 0x08000000
91 #define ETH_SR_GLI 0x04000000
92 #define ETH_SR_EB 0x03800000
93 #define ETH_SR_TS 0x00700000
94 #define ETH_SR_RS 0x000E0000
95 #define ETH_SR_NIS 0x00010000
96 #define ETH_SR_AIS 0x00008000
97 #define ETH_SR_ERI 0x00004000
98 #define ETH_SR_FBI 0x00002000
99 #define ETH_SR_ETI 0x00000400
100 #define ETH_SR_RWT 0x00000200
101 #define ETH_SR_RPS 0x00000100
102 #define ETH_SR_RU 0x00000080
103 #define ETH_SR_RI 0x00000040
104 #define ETH_SR_UNF 0x00000020
105 #define ETH_SR_OVF 0x00000010
106 #define ETH_SR_TJT 0x00000008
107 #define ETH_SR_TU 0x00000004
108 #define ETH_SR_TPS 0x00000002
109 #define ETH_SR_TI 0x00000001
110 
111 //Transmit DMA descriptor flags
112 #define ETH_TDES0_OWN 0x80000000
113 #define ETH_TDES0_IC 0x40000000
114 #define ETH_TDES0_LS 0x20000000
115 #define ETH_TDES0_FS 0x10000000
116 #define ETH_TDES0_DC 0x08000000
117 #define ETH_TDES0_DP 0x04000000
118 #define ETH_TDES0_TTSE 0x02000000
119 #define ETH_TDES0_CIC 0x00C00000
120 #define ETH_TDES0_TER 0x00200000
121 #define ETH_TDES0_TCH 0x00100000
122 #define ETH_TDES0_TTSS 0x00020000
123 #define ETH_TDES0_IHE 0x00010000
124 #define ETH_TDES0_ES 0x00008000
125 #define ETH_TDES0_JT 0x00004000
126 #define ETH_TDES0_FF 0x00002000
127 #define ETH_TDES0_IPE 0x00001000
128 #define ETH_TDES0_LCA 0x00000800
129 #define ETH_TDES0_NC 0x00000400
130 #define ETH_TDES0_LCO 0x00000200
131 #define ETH_TDES0_EC 0x00000100
132 #define ETH_TDES0_VF 0x00000080
133 #define ETH_TDES0_CC 0x00000078
134 #define ETH_TDES0_ED 0x00000004
135 #define ETH_TDES0_UF 0x00000002
136 #define ETH_TDES0_DB 0x00000001
137 #define ETH_TDES1_TBS2 0x1FFF0000
138 #define ETH_TDES1_TBS1 0x00001FFF
139 #define ETH_TDES2_B1AP 0xFFFFFFFF
140 #define ETH_TDES3_B2AP 0xFFFFFFFF
141 #define ETH_TDES6_TTSL 0xFFFFFFFF
142 #define ETH_TDES7_TTSH 0xFFFFFFFF
143 
144 //Receive DMA descriptor flags
145 #define ETH_RDES0_OWN 0x80000000
146 #define ETH_RDES0_AFM 0x40000000
147 #define ETH_RDES0_FL 0x3FFF0000
148 #define ETH_RDES0_ES 0x00008000
149 #define ETH_RDES0_DE 0x00004000
150 #define ETH_RDES0_SAF 0x00002000
151 #define ETH_RDES0_LE 0x00001000
152 #define ETH_RDES0_OE 0x00000800
153 #define ETH_RDES0_VLAN 0x00000400
154 #define ETH_RDES0_FS 0x00000200
155 #define ETH_RDES0_LS 0x00000100
156 #define ETH_RDES0_TS 0x00000080
157 #define ETH_RDES0_LCO 0x00000040
158 #define ETH_RDES0_FT 0x00000020
159 #define ETH_RDES0_RWT 0x00000010
160 #define ETH_RDES0_RE 0x00000008
161 #define ETH_RDES0_DBE 0x00000004
162 #define ETH_RDES0_CE 0x00000002
163 #define ETH_RDES0_ESA 0x00000001
164 #define ETH_RDES1_DIC 0x80000000
165 #define ETH_RDES1_RBS2 0x1FFF0000
166 #define ETH_RDES1_RER 0x00008000
167 #define ETH_RDES1_RCH 0x00004000
168 #define ETH_RDES1_RBS1 0x00001FFF
169 #define ETH_RDES2_B1AP 0xFFFFFFFF
170 #define ETH_RDES3_B2AP 0xFFFFFFFF
171 #define ETH_RDES4_TD 0x00004000
172 #define ETH_RDES4_PV 0x00002000
173 #define ETH_RDES4_PFT 0x00001000
174 #define ETH_RDES4_MT 0x00000F00
175 #define ETH_RDES4_IP6R 0x00000080
176 #define ETH_RDES4_IP4R 0x00000040
177 #define ETH_RDES4_IPCB 0x00000020
178 #define ETH_RDES4_IPE 0x00000010
179 #define ETH_RDES4_IPHE 0x00000008
180 #define ETH_RDES4_IPT 0x00000007
181 #define ETH_RDES6_RTSL 0xFFFFFFFF
182 #define ETH_RDES7_RTSH 0xFFFFFFFF
183 
184 //C++ guard
185 #ifdef __cplusplus
186 extern "C" {
187 #endif
188 
189 
190 /**
191  * @brief Enhanced TX DMA descriptor
192  **/
193 
194 typedef struct
195 {
196  uint32_t tdes0;
197  uint32_t tdes1;
198  uint32_t tdes2;
199  uint32_t tdes3;
200  uint32_t tdes4;
201  uint32_t tdes5;
202  uint32_t tdes6;
203  uint32_t tdes7;
205 
206 
207 /**
208  * @brief Enhanced RX DMA descriptor
209  **/
210 
211 typedef struct
212 {
213  uint32_t rdes0;
214  uint32_t rdes1;
215  uint32_t rdes2;
216  uint32_t rdes3;
217  uint32_t rdes4;
218  uint32_t rdes5;
219  uint32_t rdes6;
220  uint32_t rdes7;
222 
223 
224 //FM3 Ethernet MAC driver (ETHER1 instance)
225 extern const NicDriver fm3Eth2Driver;
226 
227 //FM3 Ethernet MAC related functions
228 error_t fm3Eth2Init(NetInterface *interface);
229 void fm3Eth2InitGpio(NetInterface *interface);
230 void fm3Eth2InitDmaDesc(NetInterface *interface);
231 
232 void fm3Eth2Tick(NetInterface *interface);
233 
234 void fm3Eth2EnableIrq(NetInterface *interface);
235 void fm3Eth2DisableIrq(NetInterface *interface);
236 void fm3Eth2EventHandler(NetInterface *interface);
237 
239  const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary);
240 
242 
245 
246 void fm3Eth2WritePhyReg(uint8_t opcode, uint8_t phyAddr,
247  uint8_t regAddr, uint16_t data);
248 
249 uint16_t fm3Eth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr,
250  uint8_t regAddr);
251 
252 uint32_t fm3Eth2CalcCrc(const void *data, size_t length);
253 
254 //C++ guard
255 #ifdef __cplusplus
256 }
257 #endif
258 
259 #endif
uint8_t opcode
Definition: dns_common.h:188
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
error_t fm3Eth2UpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
void fm3Eth2InitGpio(NetInterface *interface)
GPIO configuration.
const NicDriver fm3Eth2Driver
FM3 Ethernet MAC driver (ETHER1 instance)
error_t fm3Eth2SendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary)
Send a packet.
void fm3Eth2DisableIrq(NetInterface *interface)
Disable interrupts.
error_t fm3Eth2UpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void fm3Eth2EnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t fm3Eth2ReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void fm3Eth2Tick(NetInterface *interface)
FM3 Ethernet MAC timer handler.
error_t fm3Eth2ReceivePacket(NetInterface *interface)
Receive a packet.
void fm3Eth2InitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
void fm3Eth2WritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint32_t fm3Eth2CalcCrc(const void *data, size_t length)
CRC calculation.
void fm3Eth2EventHandler(NetInterface *interface)
FM3 Ethernet MAC event handler.
error_t fm3Eth2Init(NetInterface *interface)
FM3 Ethernet MAC initialization.
uint16_t regAddr
#define NetInterface
Definition: net.h:36
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
Enhanced RX DMA descriptor.
Enhanced TX DMA descriptor.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
NIC driver.
Definition: nic.h:283
uint8_t length
Definition: tcp.h:368