fm4_eth_driver.h
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1 /**
2  * @file fm4_eth_driver.h
3  * @brief Cypress FM4 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _FM4_ETH_DRIVER_H
32 #define _FM4_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef FM4_ETH_TX_BUFFER_COUNT
39  #define FM4_ETH_TX_BUFFER_COUNT 3
40 #elif (FM4_ETH_TX_BUFFER_COUNT < 1)
41  #error FM4_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef FM4_ETH_TX_BUFFER_SIZE
46  #define FM4_ETH_TX_BUFFER_SIZE 1536
47 #elif (FM4_ETH_TX_BUFFER_SIZE != 1536)
48  #error FM4_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef FM4_ETH_RX_BUFFER_COUNT
53  #define FM4_ETH_RX_BUFFER_COUNT 6
54 #elif (FM4_ETH_RX_BUFFER_COUNT < 1)
55  #error FM4_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef FM4_ETH_RX_BUFFER_SIZE
60  #define FM4_ETH_RX_BUFFER_SIZE 1536
61 #elif (FM4_ETH_RX_BUFFER_SIZE != 1536)
62  #error FM4_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef FM4_ETH_IRQ_PRIORITY_GROUPING
67  #define FM4_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (FM4_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error FM4_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef FM4_ETH_IRQ_GROUP_PRIORITY
74  #define FM4_ETH_IRQ_GROUP_PRIORITY 12
75 #elif (FM4_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error FM4_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef FM4_ETH_IRQ_SUB_PRIORITY
81  #define FM4_ETH_IRQ_SUB_PRIORITY 0
82 #elif (FM4_ETH_IRQ_SUB_PRIORITY < 0)
83  #error FM4_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //Transmit DMA descriptor flags
87 #define ETH_TDES0_OWN 0x80000000
88 #define ETH_TDES0_IC 0x40000000
89 #define ETH_TDES0_LS 0x20000000
90 #define ETH_TDES0_FS 0x10000000
91 #define ETH_TDES0_DC 0x08000000
92 #define ETH_TDES0_DP 0x04000000
93 #define ETH_TDES0_TTSE 0x02000000
94 #define ETH_TDES0_CIC 0x00C00000
95 #define ETH_TDES0_TER 0x00200000
96 #define ETH_TDES0_TCH 0x00100000
97 #define ETH_TDES0_TTSS 0x00020000
98 #define ETH_TDES0_IHE 0x00010000
99 #define ETH_TDES0_ES 0x00008000
100 #define ETH_TDES0_JT 0x00004000
101 #define ETH_TDES0_FF 0x00002000
102 #define ETH_TDES0_IPE 0x00001000
103 #define ETH_TDES0_LCA 0x00000800
104 #define ETH_TDES0_NC 0x00000400
105 #define ETH_TDES0_LCO 0x00000200
106 #define ETH_TDES0_EC 0x00000100
107 #define ETH_TDES0_VF 0x00000080
108 #define ETH_TDES0_CC 0x00000078
109 #define ETH_TDES0_ED 0x00000004
110 #define ETH_TDES0_UF 0x00000002
111 #define ETH_TDES0_DB 0x00000001
112 #define ETH_TDES1_TBS2 0x1FFF0000
113 #define ETH_TDES1_TBS1 0x00001FFF
114 #define ETH_TDES2_B1AP 0xFFFFFFFF
115 #define ETH_TDES3_B2AP 0xFFFFFFFF
116 #define ETH_TDES6_TTSL 0xFFFFFFFF
117 #define ETH_TDES7_TTSH 0xFFFFFFFF
118 
119 //Receive DMA descriptor flags
120 #define ETH_RDES0_OWN 0x80000000
121 #define ETH_RDES0_AFM 0x40000000
122 #define ETH_RDES0_FL 0x3FFF0000
123 #define ETH_RDES0_ES 0x00008000
124 #define ETH_RDES0_DE 0x00004000
125 #define ETH_RDES0_SAF 0x00002000
126 #define ETH_RDES0_LE 0x00001000
127 #define ETH_RDES0_OE 0x00000800
128 #define ETH_RDES0_VLAN 0x00000400
129 #define ETH_RDES0_FS 0x00000200
130 #define ETH_RDES0_LS 0x00000100
131 #define ETH_RDES0_TS 0x00000080
132 #define ETH_RDES0_LCO 0x00000040
133 #define ETH_RDES0_FT 0x00000020
134 #define ETH_RDES0_RWT 0x00000010
135 #define ETH_RDES0_RE 0x00000008
136 #define ETH_RDES0_DBE 0x00000004
137 #define ETH_RDES0_CE 0x00000002
138 #define ETH_RDES0_ESA 0x00000001
139 #define ETH_RDES1_DIC 0x80000000
140 #define ETH_RDES1_RBS2 0x1FFF0000
141 #define ETH_RDES1_RER 0x00008000
142 #define ETH_RDES1_RCH 0x00004000
143 #define ETH_RDES1_RBS1 0x00001FFF
144 #define ETH_RDES2_B1AP 0xFFFFFFFF
145 #define ETH_RDES3_B2AP 0xFFFFFFFF
146 #define ETH_RDES4_TD 0x00004000
147 #define ETH_RDES4_PV 0x00002000
148 #define ETH_RDES4_PFT 0x00001000
149 #define ETH_RDES4_MT 0x00000F00
150 #define ETH_RDES4_IP6R 0x00000080
151 #define ETH_RDES4_IP4R 0x00000040
152 #define ETH_RDES4_IPCB 0x00000020
153 #define ETH_RDES4_IPE 0x00000010
154 #define ETH_RDES4_IPHE 0x00000008
155 #define ETH_RDES4_IPT 0x00000007
156 #define ETH_RDES6_RTSL 0xFFFFFFFF
157 #define ETH_RDES7_RTSH 0xFFFFFFFF
158 
159 //C++ guard
160 #ifdef __cplusplus
161 extern "C" {
162 #endif
163 
164 
165 /**
166  * @brief Enhanced TX DMA descriptor
167  **/
168 
169 typedef struct
170 {
171  uint32_t tdes0;
172  uint32_t tdes1;
173  uint32_t tdes2;
174  uint32_t tdes3;
175  uint32_t tdes4;
176  uint32_t tdes5;
177  uint32_t tdes6;
178  uint32_t tdes7;
179 } Fm4TxDmaDesc;
180 
181 
182 /**
183  * @brief Enhanced RX DMA descriptor
184  **/
185 
186 typedef struct
187 {
188  uint32_t rdes0;
189  uint32_t rdes1;
190  uint32_t rdes2;
191  uint32_t rdes3;
192  uint32_t rdes4;
193  uint32_t rdes5;
194  uint32_t rdes6;
195  uint32_t rdes7;
196 } Fm4RxDmaDesc;
197 
198 
199 //FM4 Ethernet MAC driver
200 extern const NicDriver fm4EthDriver;
201 
202 //FM4 Ethernet MAC related functions
203 error_t fm4EthInit(NetInterface *interface);
204 void fm4EthInitGpio(NetInterface *interface);
205 void fm4EthInitDmaDesc(NetInterface *interface);
206 
207 void fm4EthTick(NetInterface *interface);
208 
209 void fm4EthEnableIrq(NetInterface *interface);
210 void fm4EthDisableIrq(NetInterface *interface);
211 void fm4EthEventHandler(NetInterface *interface);
212 
214  const NetBuffer *buffer, size_t offset);
215 
217 
220 
221 void fm4EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
222  uint8_t regAddr, uint16_t data);
223 
224 uint16_t fm4EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
225  uint8_t regAddr);
226 
227 uint32_t fm4EthCalcCrc(const void *data, size_t length);
228 
229 //C++ guard
230 #ifdef __cplusplus
231 }
232 #endif
233 
234 #endif
uint8_t length
Definition: dtls_misc.h:149
uint8_t opcode
Definition: dns_common.h:172
uint32_t rdes4
Enhanced RX DMA descriptor.
void fm4EthDisableIrq(NetInterface *interface)
Disable interrupts.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
uint32_t tdes6
error_t fm4EthInit(NetInterface *interface)
FM4 Ethernet MAC initialization.
void fm4EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
uint32_t tdes7
uint32_t rdes2
uint32_t rdes0
error_t
Error codes.
Definition: error.h:42
uint32_t tdes3
uint32_t tdes5
void fm4EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
#define NetInterface
Definition: net.h:36
uint32_t tdes1
uint32_t rdes1
uint32_t tdes4
uint32_t rdes6
void fm4EthInitGpio(NetInterface *interface)
error_t fm4EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
uint16_t regAddr
void fm4EthTick(NetInterface *interface)
FM4 Ethernet MAC timer handler.
uint32_t fm4EthCalcCrc(const void *data, size_t length)
CRC calculation.
void fm4EthEventHandler(NetInterface *interface)
FM4 Ethernet MAC event handler.
uint16_t fm4EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
Network interface controller abstraction layer.
void fm4EthEnableIrq(NetInterface *interface)
Enable interrupts.
const NicDriver fm4EthDriver
FM4 Ethernet MAC driver.
uint32_t tdes0
uint32_t tdes2
uint32_t rdes7
uint32_t rdes5
error_t fm4EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
uint32_t rdes3
uint8_t data[]
Definition: dtls_misc.h:176
error_t fm4EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
Enhanced TX DMA descriptor.
NIC driver.
Definition: nic.h:179
error_t fm4EthReceivePacket(NetInterface *interface)
Receive a packet.