ics1894_driver.h
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1 /**
2  * @file ics1894_driver.h
3  * @brief ICS1894-32 Ethernet PHY driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.4
29  **/
30 
31 #ifndef _ICS1894_DRIVER_H
32 #define _ICS1894_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //PHY address
38 #ifndef ICS1894_PHY_ADDR
39  #define ICS1894_PHY_ADDR 5
40 #elif (ICS1894_PHY_ADDR < 0 || ICS1894_PHY_ADDR > 31)
41  #error ICS1894_PHY_ADDR parameter is not valid
42 #endif
43 
44 //ICS1894 PHY registers
45 #define ICS1894_BMCR 0x00
46 #define ICS1894_BMSR 0x01
47 #define ICS1894_PHYID1 0x02
48 #define ICS1894_PHYID2 0x03
49 #define ICS1894_ANAR 0x04
50 #define ICS1894_ANLPAR 0x05
51 #define ICS1894_ANER 0x06
52 #define ICS1894_ANNPT 0x07
53 #define ICS1894_ANNPLPAR 0x08
54 #define ICS1894_ECR1 0x10
55 #define ICS1894_QPDSR 0x11
56 #define ICS1894_10BT_OP 0x12
57 #define ICS1894_ECR2 0x13
58 #define ICS1894_ECR3 0x14
59 #define ICS1894_ECR4 0x15
60 #define ICS1894_ECR5 0x16
61 #define ICS1894_ECR6 0x17
62 #define ICS1894_ECR7 0x18
63 
64 //Basic Control register
65 #define ICS1894_BMCR_RESET 0x8000
66 #define ICS1894_BMCR_LOOPBACK 0x4000
67 #define ICS1894_BMCR_SPEED_SEL 0x2000
68 #define ICS1894_BMCR_AN_EN 0x1000
69 #define ICS1894_BMCR_POWER_DOWN 0x0800
70 #define ICS1894_BMCR_ISOLATE 0x0400
71 #define ICS1894_BMCR_RESTART_AN 0x0200
72 #define ICS1894_BMCR_DUPLEX_MODE 0x0100
73 #define ICS1894_BMCR_COL_TEST 0x0080
74 
75 //Basic Status register
76 #define ICS1894_BMSR_100BT4 0x8000
77 #define ICS1894_BMSR_100BTX_FD 0x4000
78 #define ICS1894_BMSR_100BTX_HD 0x2000
79 #define ICS1894_BMSR_10BT_FD 0x1000
80 #define ICS1894_BMSR_10BT_HD 0x0800
81 #define ICS1894_BMSR_MF_PREAMBLE_SUPPR 0x0040
82 #define ICS1894_BMSR_AN_COMPLETE 0x0020
83 #define ICS1894_BMSR_REMOTE_FAULT 0x0010
84 #define ICS1894_BMSR_AN_CAPABLE 0x0008
85 #define ICS1894_BMSR_LINK_STATUS 0x0004
86 #define ICS1894_BMSR_JABBER_DETECT 0x0002
87 #define ICS1894_BMSR_EXTENDED_CAPABLE 0x0001
88 
89 //PHY Identifier 1 register
90 #define ICS1894_PHYID1_OUI_MSB 0xFFFF
91 #define ICS1894_PHYID1_OUI_MSB_DEFAULT 0x0015
92 
93 //PHY Identifier 2 register
94 #define ICS1894_PHYID2_OUI_LSB 0xFC00
95 #define ICS1894_PHYID2_OUI_LSB_DEFAULT 0xF400
96 #define ICS1894_PHYID2_MODEL_NUM 0x03F0
97 #define ICS1894_PHYID2_MODEL_NUM_DEFAULT 0x0050
98 #define ICS1894_PHYID2_REVISION_NUM 0x000F
99 #define ICS1894_PHYID2_REVISION_NUM_DEFAULT 0x0000
100 
101 //Auto-Negotiation Advertisement register
102 #define ICS1894_ANAR_NEXT_PAGE 0x8000
103 #define ICS1894_ANAR_REMOTE_FAULT 0x2000
104 #define ICS1894_ANAR_100BT4 0x0200
105 #define ICS1894_ANAR_100BTX_FD 0x0100
106 #define ICS1894_ANAR_100BTX_HD 0x0080
107 #define ICS1894_ANAR_10BT_FD 0x0040
108 #define ICS1894_ANAR_10BT_HD 0x0020
109 #define ICS1894_ANAR_SELECTOR 0x001F
110 #define ICS1894_ANAR_SELECTOR_DEFAULT 0x0001
111 
112 //Auto-Negotiation Link Partner Ability register
113 #define ICS1894_ANLPAR_NEXT_PAGE 0x8000
114 #define ICS1894_ANLPAR_ACK 0x4000
115 #define ICS1894_ANLPAR_REMOTE_FAULT 0x2000
116 #define ICS1894_ANLPAR_100BT4 0x0200
117 #define ICS1894_ANLPAR_100BTX_FD 0x0100
118 #define ICS1894_ANLPAR_100BTX_HD 0x0080
119 #define ICS1894_ANLPAR_10BT_FD 0x0040
120 #define ICS1894_ANLPAR_10BT_HD 0x0020
121 #define ICS1894_ANLPAR_SELECTOR 0x001F
122 
123 //Auto-Negotiation Expansion register
124 #define ICS1894_ANER_PAR_DETECT_FAULT 0x0010
125 #define ICS1894_ANER_LP_NEXT_PAGE_ABLE 0x0008
126 #define ICS1894_ANER_NEXT_PAGE_ABLE 0x0004
127 #define ICS1894_ANER_PAGE_RECEIVED 0x0002
128 #define ICS1894_ANER_LP_AN_ABLE 0x0001
129 
130 //Auto-Negotiation Next Page Transmit register
131 #define ICS1894_ANNPT_NEXT_PAGE 0x8000
132 #define ICS1894_ANNPT_MSG_PAGE 0x2000
133 #define ICS1894_ANNPT_ACK2 0x1000
134 #define ICS1894_ANNPT_TOGGLE 0x0800
135 #define ICS1894_ANNPT_MESSAGE 0x07FF
136 
137 //Auto-Negotiation Next Page Link Partner Ability register
138 #define ICS1894_ANNPLPAR_NEXT_PAGE 0x8000
139 #define ICS1894_ANNPLPAR_MSG_PAGE 0x2000
140 #define ICS1894_ANNPLPAR_ACK2 0x1000
141 #define ICS1894_ANNPLPAR_TOGGLE 0x0800
142 #define ICS1894_ANNPLPAR_MESSAGE 0x07FF
143 
144 //Extended Control 1 register
145 #define ICS1894_ECR1_CMD_OVERRIDE_WR_EN 0x8000
146 #define ICS1894_ECR1_PHY_ADDR 0x07C0
147 #define ICS1894_ECR1_STREAM_CIPHER_TEST_MODE 0x0020
148 #define ICS1894_ECR1_NRZ_NRZI_ENCODING 0x0008
149 #define ICS1894_ECR1_TRANSMIT_INVALID_CODES 0x0004
150 #define ICS1894_ECR1_STREAM_CIPHER_DIS 0x0001
151 
152 //Quick Poll Detailed Status register
153 #define ICS1894_QPDSR_DATA_RATE 0x8000
154 #define ICS1894_QPDSR_DATA_RATE_10MBPS 0x0000
155 #define ICS1894_QPDSR_DATA_RATE_100MBPS 0x8000
156 #define ICS1894_QPDSR_DUPLEX 0x4000
157 #define ICS1894_QPDSR_DUPLEX_HD 0x0000
158 #define ICS1894_QPDSR_DUPLEX_FD 0x4000
159 #define ICS1894_QPDSR_AN_PROGRESS_MONITOR 0x3800
160 #define ICS1894_QPDSR_100BTX_SIGNAL_LOST 0x0400
161 #define ICS1894_QPDSR_100_PLL_LOCK_ERROR 0x0200
162 #define ICS1894_QPDSR_FALSE_CARRIER_DETECT 0x0100
163 #define ICS1894_QPDSR_INVALID_SYMBOL_DETECT 0x0080
164 #define ICS1894_QPDSR_HALT_SYMBOL_DETECT 0x0040
165 #define ICS1894_QPDSR_PREMATURE_END_DETECT 0x0020
166 #define ICS1894_QPDSR_AN_COMPLETE 0x0010
167 #define ICS1894_QPDSR_100BTX_SIGNAL_DETECT 0x0008
168 #define ICS1894_QPDSR_JABBER_DETECT 0x0004
169 #define ICS1894_QPDSR_REMOTE_FAULT 0x0002
170 #define ICS1894_QPDSR_LINK_STATUS 0x0001
171 
172 //10Base-T Operations register
173 #define ICS1894_10BT_OP_REMOTE_JABBER_DETECT 0x8000
174 #define ICS1894_10BT_OP_POLARITY_REV 0x4000
175 #define ICS1894_10BT_OP_DATA_BUS_MODE 0x3000
176 #define ICS1894_10BT_OP_DATA_BUS_MODE_MII 0x0000
177 #define ICS1894_10BT_OP_DATA_BUS_MODE_SI 0x1000
178 #define ICS1894_10BT_OP_DATA_BUS_MODE_RMII 0x2000
179 #define ICS1894_10BT_OP_AMDIXEN 0x0800
180 #define ICS1894_10BT_OP_RXTRI 0x0400
181 #define ICS1894_10BT_OP_REGEN 0x0200
182 #define ICS1894_10BT_OP_TM_SWITCH 0x0100
183 #define ICS1894_10BT_OP_JABBER_INHIBIT 0x0020
184 #define ICS1894_10BT_OP_AUTO_POLARITY_INHIBIT 0x0008
185 #define ICS1894_10BT_OP_SQE_TEST_INHIBIT 0x0004
186 #define ICS1894_10BT_OP_LINK_LOSS_INHIBIT 0x0002
187 #define ICS1894_10BT_OP_SQUELCH_INHIBIT 0x0001
188 
189 //Extended Control 2 register
190 #define ICS1894_ECR2_NODE_MODE 0x8000
191 #define ICS1894_ECR2_HW_SW_MODE_SPEED_SEL 0x4000
192 #define ICS1894_ECR2_REMOTE_FAULT 0x2000
193 #define ICS1894_ECR2_REGISTER_BANK_SEL 0x1800
194 #define ICS1894_ECR2_AMDIX_EN 0x0200
195 #define ICS1894_ECR2_MDI_MODE 0x0100
196 #define ICS1894_ECR2_TPTRI 0x0080
197 #define ICS1894_ECR2_AUTO_100BTX_PD 0x0001
198 
199 //Extended Control 3 register
200 #define ICS1894_ECR3_STR_ENHANCE 0x8000
201 #define ICS1894_ECR3_FAST_OFF 0x4000
202 #define ICS1894_ECR3_LED4_MODE 0x3000
203 #define ICS1894_ECR3_LED4_MODE_RX 0x0000
204 #define ICS1894_ECR3_LED4_MODE_COL 0x1000
205 #define ICS1894_ECR3_LED4_MODE_FD 0x2000
206 #define ICS1894_ECR3_LED4_MODE_OFF 0x3000
207 #define ICS1894_ECR3_LED3_MODE 0x0E00
208 #define ICS1894_ECR3_LED3_MODE_LINK 0x0000
209 #define ICS1894_ECR3_LED3_MODE_ACT 0x0200
210 #define ICS1894_ECR3_LED3_MODE_TX 0x0400
211 #define ICS1894_ECR3_LED3_MODE_RX 0x0600
212 #define ICS1894_ECR3_LED3_MODE_COL 0x0800
213 #define ICS1894_ECR3_LED3_MODE_100_10 0x0A00
214 #define ICS1894_ECR3_LED3_MODE_FD 0x0C00
215 #define ICS1894_ECR3_LED3_MODE_OFF 0x0E00
216 #define ICS1894_ECR3_LED2_MODE 0x01C0
217 #define ICS1894_ECR3_LED2_MODE_LINK 0x0000
218 #define ICS1894_ECR3_LED2_MODE_ACT 0x0040
219 #define ICS1894_ECR3_LED2_MODE_TX 0x0080
220 #define ICS1894_ECR3_LED2_MODE_RX 0x00C0
221 #define ICS1894_ECR3_LED2_MODE_COL 0x0100
222 #define ICS1894_ECR3_LED2_MODE_100_10 0x0140
223 #define ICS1894_ECR3_LED2_MODE_FD 0x0180
224 #define ICS1894_ECR3_LED2_MODE_OFF 0x01C0
225 #define ICS1894_ECR3_LED1_MODE 0x0038
226 #define ICS1894_ECR3_LED1_MODE_LINK 0x0000
227 #define ICS1894_ECR3_LED1_MODE_ACT 0x0008
228 #define ICS1894_ECR3_LED1_MODE_TX 0x0010
229 #define ICS1894_ECR3_LED1_MODE_RX 0x0018
230 #define ICS1894_ECR3_LED1_MODE_COL 0x0020
231 #define ICS1894_ECR3_LED1_MODE_100_10 0x0028
232 #define ICS1894_ECR3_LED1_MODE_FD 0x0030
233 #define ICS1894_ECR3_LED1_MODE_OFF 0x0038
234 #define ICS1894_ECR3_LED0_MODE 0x0007
235 #define ICS1894_ECR3_LED0_MODE_LINK 0x0000
236 #define ICS1894_ECR3_LED0_MODE_ACT 0x0001
237 #define ICS1894_ECR3_LED0_MODE_TX 0x0002
238 #define ICS1894_ECR3_LED0_MODE_RX 0x0003
239 #define ICS1894_ECR3_LED0_MODE_COL 0x0004
240 #define ICS1894_ECR3_LED0_MODE_100_10 0x0005
241 #define ICS1894_ECR3_LED0_MODE_FD 0x0006
242 #define ICS1894_ECR3_LED0_MODE_LINK_STAT 0x0007
243 
244 //Extended Control 4 register
245 #define ICS1894_ECR4_RXER_CNT 0xFFFF
246 
247 //Extended Control 5 register
248 #define ICS1894_ECR5_INT_OUT_EN 0x8000
249 #define ICS1894_ECR5_INT_FLAG_RD_CLEAR_EN 0x4000
250 #define ICS1894_ECR5_Int_pol 0x2000
251 #define ICS1894_ECR5_INT_FLAG_AUTO_CLEAR_EN 0x1000
252 #define ICS1894_ECR5_INT_FLAG_RE_SETUP_EN 0x0800
253 #define ICS1894_ECR5_DPD_WU_INT_EN 0x0400
254 #define ICS1894_ECR5_DPD_INT_EN 0x0200
255 #define ICS1894_ECR5_AN_COMPLETE_INT_EN 0x0100
256 #define ICS1894_ECR5_JABBER_INT_EN 0x0080
257 #define ICS1894_ECR5_RX_ERROR_INT_EN 0x0040
258 #define ICS1894_ECR5_PAGE_RECEIVED_INT_EN 0x0020
259 #define ICS1894_ECR5_PAR_DETECT_FAULT_INT_EN 0x0010
260 #define ICS1894_ECR5_LP_ACK_INT_EN 0x0008
261 #define ICS1894_ECR5_LINK_DOWN_INT_EN 0x0004
262 #define ICS1894_ECR5_REMOTE_FAULT_INT_EN 0x0002
263 #define ICS1894_ECR5_LINK_UP_INT_EN 0x0001
264 
265 //Extended Control 6 register
266 #define ICS1894_ECR6_DPD_WU_INT 0x0400
267 #define ICS1894_ECR6_DPD_INT 0x0200
268 #define ICS1894_ECR6_AN_COMPLETE_INT 0x0100
269 #define ICS1894_ECR6_JABBER_INT 0x0080
270 #define ICS1894_ECR6_RX_ERROR_INT 0x0040
271 #define ICS1894_ECR6_PAGE_RECEIVED_INT 0x0020
272 #define ICS1894_ECR6_PAR_DETECT_FAULT_INT 0x0010
273 #define ICS1894_ECR6_LP_ACK_INT 0x0008
274 #define ICS1894_ECR6_LINK_DOWN_INT 0x0004
275 #define ICS1894_ECR6_REMOTE_FAULT_INT 0x0002
276 #define ICS1894_ECR6_LINK_UP_INT 0x0001
277 
278 //Extended Control 7 register
279 #define ICS1894_ECR7_FIFO_HALF 0xF000
280 #define ICS1894_ECR7_DPD_EN 0x0100
281 #define ICS1894_ECR7_TPLL_10_100_DPD_EN 0x0080
282 #define ICS1894_ECR7_RX_100_DPD_EN 0x0040
283 #define ICS1894_ECR7_ADMIX_TX_DPD_EN 0x0020
284 #define ICS1894_ECR7_CDR_100_CDR_DPD_EN 0x0010
285 
286 //C++ guard
287 #ifdef __cplusplus
288 extern "C" {
289 #endif
290 
291 //ICS1894 Ethernet PHY driver
292 extern const PhyDriver ics1894PhyDriver;
293 
294 //ICS1894 related functions
295 error_t ics1894Init(NetInterface *interface);
296 void ics1894InitHook(NetInterface *interface);
297 
298 void ics1894Tick(NetInterface *interface);
299 
300 void ics1894EnableIrq(NetInterface *interface);
301 void ics1894DisableIrq(NetInterface *interface);
302 
303 void ics1894EventHandler(NetInterface *interface);
304 
305 void ics1894WritePhyReg(NetInterface *interface, uint8_t address,
306  uint16_t data);
307 
308 uint16_t ics1894ReadPhyReg(NetInterface *interface, uint8_t address);
309 
310 void ics1894DumpPhyReg(NetInterface *interface);
311 
312 //C++ guard
313 #ifdef __cplusplus
314 }
315 #endif
316 
317 #endif
error_t ics1894Init(NetInterface *interface)
ICS1894 PHY transceiver initialization.
void ics1894InitHook(NetInterface *interface)
ICS1894 custom configuration.
Ethernet PHY driver.
Definition: nic.h:311
uint8_t data[]
Definition: ethernet.h:222
void ics1894Tick(NetInterface *interface)
ICS1894 timer handler.
uint16_t ics1894ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
error_t
Error codes.
Definition: error.h:43
void ics1894DisableIrq(NetInterface *interface)
Disable interrupts.
#define NetInterface
Definition: net.h:36
void ics1894EventHandler(NetInterface *interface)
ICS1894 event handler.
void ics1894EnableIrq(NetInterface *interface)
Enable interrupts.
Ipv6Addr address[]
Definition: ipv6.h:325
void ics1894WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
Network interface controller abstraction layer.
void ics1894DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
const PhyDriver ics1894PhyDriver
ICS1894 Ethernet PHY driver.