ksz8081_driver.h
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1 /**
2  * @file ksz8081_driver.h
3  * @brief KSZ8081 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _KSZ8081_DRIVER_H
30 #define _KSZ8081_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef KSZ8081_PHY_ADDR
37  #define KSZ8081_PHY_ADDR 0
38 #elif (KSZ8081_PHY_ADDR < 0 || KSZ8081_PHY_ADDR > 31)
39  #error KSZ8081_PHY_ADDR parameter is not valid
40 #endif
41 
42 //50MHz clock mode support
43 #ifndef KSZ8081_50MHZ_CLOCK_MODE_SUPPORT
44  #define KSZ8081_50MHZ_CLOCK_MODE_SUPPORT DISABLED
45 #elif (KSZ8081_50MHZ_CLOCK_MODE_SUPPORT != ENABLED && KSZ8081_50MHZ_CLOCK_MODE_SUPPORT != DISABLED)
46  #error KSZ8081_50MHZ_CLOCK_MODE_SUPPORT parameter is not valid
47 #endif
48 
49 //KSZ8081 registers
50 #define KSZ8081_PHY_REG_BMCR 0x00
51 #define KSZ8081_PHY_REG_BMSR 0x01
52 #define KSZ8081_PHY_REG_PHYIDR1 0x02
53 #define KSZ8081_PHY_REG_PHYIDR2 0x03
54 #define KSZ8081_PHY_REG_ANAR 0x04
55 #define KSZ8081_PHY_REG_ANLPAR 0x05
56 #define KSZ8081_PHY_REG_ANER 0x06
57 #define KSZ8081_PHY_REG_ANNPTR 0x07
58 #define KSZ8081_PHY_REG_LPNPAR 0x08
59 #define KSZ8081_PHY_REG_DRC 0x10
60 #define KSZ8081_PHY_REG_AFECON1 0x11
61 #define KSZ8081_PHY_REG_RXERCTR 0x15
62 #define KSZ8081_PHY_REG_OMSO 0x16
63 #define KSZ8081_PHY_REG_OMSS 0x17
64 #define KSZ8081_PHY_REG_EXCON 0x18
65 #define KSZ8081_PHY_REG_ICSR 0x1B
66 #define KSZ8081_PHY_REG_LINKMDCS 0x1D
67 #define KSZ8081_PHY_REG_PHYCON1 0x1E
68 #define KSZ8081_PHY_REG_PHYCON2 0x1F
69 
70 //BMCR register
71 #define BMCR_RESET (1 << 15)
72 #define BMCR_LOOPBACK (1 << 14)
73 #define BMCR_SPEED_SEL (1 << 13)
74 #define BMCR_AN_EN (1 << 12)
75 #define BMCR_POWER_DOWN (1 << 11)
76 #define BMCR_ISOLATE (1 << 10)
77 #define BMCR_RESTART_AN (1 << 9)
78 #define BMCR_DUPLEX_MODE (1 << 8)
79 #define BMCR_COL_TEST (1 << 7)
80 
81 //BMSR register
82 #define BMSR_100BT4 (1 << 15)
83 #define BMSR_100BTX_FD (1 << 14)
84 #define BMSR_100BTX (1 << 13)
85 #define BMSR_10BT_FD (1 << 12)
86 #define BMSR_10BT (1 << 11)
87 #define BMSR_NO_PREAMBLE (1 << 6)
88 #define BMSR_AN_COMPLETE (1 << 5)
89 #define BMSR_REMOTE_FAULT (1 << 4)
90 #define BMSR_AN_ABLE (1 << 3)
91 #define BMSR_LINK_STATUS (1 << 2)
92 #define BMSR_JABBER_DETECT (1 << 1)
93 #define BMSR_EXTENDED_CAP (1 << 0)
94 
95 //ANAR register
96 #define ANAR_NEXT_PAGE (1 << 15)
97 #define ANAR_REMOTE_FAULT (1 << 13)
98 #define ANAR_PAUSE1 (1 << 11)
99 #define ANAR_PAUSE0 (1 << 10)
100 #define ANAR_100BT4 (1 << 9)
101 #define ANAR_100BTX_FD (1 << 8)
102 #define ANAR_100BTX (1 << 7)
103 #define ANAR_10BT_FD (1 << 6)
104 #define ANAR_10BT (1 << 5)
105 #define ANAR_SELECTOR4 (1 << 4)
106 #define ANAR_SELECTOR3 (1 << 3)
107 #define ANAR_SELECTOR2 (1 << 2)
108 #define ANAR_SELECTOR1 (1 << 1)
109 #define ANAR_SELECTOR0 (1 << 0)
110 
111 //ANLPAR register
112 #define ANLPAR_NEXT_PAGE (1 << 15)
113 #define ANLPAR_LP_ACK (1 << 14)
114 #define ANLPAR_REMOTE_FAULT (1 << 13)
115 #define ANLPAR_PAUSE1 (1 << 11)
116 #define ANLPAR_PAUSE0 (1 << 10)
117 #define ANLPAR_100BT4 (1 << 9)
118 #define ANLPAR_100BTX_FD (1 << 8)
119 #define ANLPAR_100BTX (1 << 7)
120 #define ANLPAR_10BT_FD (1 << 6)
121 #define ANLPAR_10BT (1 << 5)
122 #define ANLPAR_SELECTOR4 (1 << 4)
123 #define ANLPAR_SELECTOR3 (1 << 3)
124 #define ANLPAR_SELECTOR2 (1 << 2)
125 #define ANLPAR_SELECTOR1 (1 << 1)
126 #define ANLPAR_SELECTOR0 (1 << 0)
127 
128 //ANER register
129 #define ANER_PAR_DET_FAULT (1 << 4)
130 #define ANER_LP_NEXT_PAGE_ABLE (1 << 3)
131 #define ANER_NEXT_PAGE_ABLE (1 << 2)
132 #define ANER_PAGE_RECEIVED (1 << 1)
133 #define ANER_LP_AN_ABLE (1 << 0)
134 
135 //ANNPTR register
136 #define ANNPTR_NEXT_PAGE (1 << 15)
137 #define ANNPTR_MSG_PAGE (1 << 13)
138 #define ANNPTR_ACK2 (1 << 12)
139 #define ANNPTR_TOGGLE (1 << 11)
140 #define ANNPTR_MESSAGE10 (1 << 10)
141 #define ANNPTR_MESSAGE9 (1 << 9)
142 #define ANNPTR_MESSAGE8 (1 << 8)
143 #define ANNPTR_MESSAGE7 (1 << 7)
144 #define ANNPTR_MESSAGE6 (1 << 6)
145 #define ANNPTR_MESSAGE5 (1 << 5)
146 #define ANNPTR_MESSAGE4 (1 << 4)
147 #define ANNPTR_MESSAGE3 (1 << 3)
148 #define ANNPTR_MESSAGE2 (1 << 2)
149 #define ANNPTR_MESSAGE1 (1 << 1)
150 #define ANNPTR_MESSAGE0 (1 << 0)
151 
152 //LPNPAR register
153 #define LPNPAR_NEXT_PAGE (1 << 15)
154 #define LPNPAR_ACK (1 << 14)
155 #define LPNPAR_MSG_PAGE (1 << 13)
156 #define LPNPAR_ACK2 (1 << 12)
157 #define LPNPAR_TOGGLE (1 << 11)
158 #define LPNPAR_MESSAGE10 (1 << 10)
159 #define LPNPAR_MESSAGE9 (1 << 9)
160 #define LPNPAR_MESSAGE8 (1 << 8)
161 #define LPNPAR_MESSAGE7 (1 << 7)
162 #define LPNPAR_MESSAGE6 (1 << 6)
163 #define LPNPAR_MESSAGE5 (1 << 5)
164 #define LPNPAR_MESSAGE4 (1 << 4)
165 #define LPNPAR_MESSAGE3 (1 << 3)
166 #define LPNPAR_MESSAGE2 (1 << 2)
167 #define LPNPAR_MESSAGE1 (1 << 1)
168 #define LPNPAR_MESSAGE0 (1 << 0)
169 
170 //DRC register
171 #define DRC_PLL_OFF (1 << 4)
172 
173 //AFECON1 register
174 #define AFECON1_SLOW_OSC_MODE_EN (1 << 5)
175 
176 //OMSO register
177 #define OMSO_BCAST_OFF_OVERRIDE (1 << 9)
178 #define OMSO_MII_BTB_OVERRIDE (1 << 7)
179 #define OMSO_RMII_BTB_OVERRIDE (1 << 6)
180 #define OMSO_NAND_TREE_OVERRIDE (1 << 5)
181 #define OMSO_RMII_OVERRIDE (1 << 1)
182 #define OMSO_MII_OVERRIDE (1 << 0)
183 
184 //OMSS register
185 #define OMSS_PHYAD2 (1 << 15)
186 #define OMSS_PHYAD1 (1 << 14)
187 #define OMSS_PHYAD0 (1 << 13)
188 #define OMSS_RMII_STATUS (1 << 1)
189 
190 //EXCON register
191 #define EXCON_EDPD_DIS (1 << 11)
192 
193 //ICSR register
194 #define ICSR_JABBER_IE (1 << 15)
195 #define ICSR_RECEIVE_ERROR_IE (1 << 14)
196 #define ICSR_PAGE_RECEIVED_IE (1 << 13)
197 #define ICSR_PAR_DET_FAULT_IE (1 << 12)
198 #define ICSR_LP_ACK_IE (1 << 11)
199 #define ICSR_LINK_DOWN_IE (1 << 10)
200 #define ICSR_REMOTE_FAULT_IE (1 << 9)
201 #define ICSR_LINK_UP_IE (1 << 8)
202 #define ICSR_JABBER_IF (1 << 7)
203 #define ICSR_RECEIVE_ERROR_IF (1 << 6)
204 #define ICSR_PAGE_RECEIVED_IF (1 << 5)
205 #define ICSR_PAR_DET_FAULT_IF (1 << 4)
206 #define ICSR_LP_ACK_IF (1 << 3)
207 #define ICSR_LINK_DOWN_IF (1 << 2)
208 #define ICSR_REMOTE_FAULT_IF (1 << 1)
209 #define ICSR_LINK_UP_IF (1 << 0)
210 
211 //LINKMDCS register
212 #define LINKMDCS_CABLE_DIAG_EN (1 << 15)
213 #define LINKMDCS_CABLE_DIAG_RES1 (1 << 14)
214 #define LINKMDCS_CABLE_DIAG_RES0 (1 << 13)
215 #define LINKMDCS_SHORT_CABLE (1 << 12)
216 #define LINKMDCS_CABLE_FAULT_CNT8 (1 << 8)
217 #define LINKMDCS_CABLE_FAULT_CNT7 (1 << 7)
218 #define LINKMDCS_CABLE_FAULT_CNT6 (1 << 6)
219 #define LINKMDCS_CABLE_FAULT_CNT5 (1 << 5)
220 #define LINKMDCS_CABLE_FAULT_CNT4 (1 << 4)
221 #define LINKMDCS_CABLE_FAULT_CNT3 (1 << 3)
222 #define LINKMDCS_CABLE_FAULT_CNT2 (1 << 2)
223 #define LINKMDCS_CABLE_FAULT_CNT1 (1 << 1)
224 #define LINKMDCS_CABLE_FAULT_CNT0 (1 << 0)
225 
226 //PHYCON1 register
227 #define PHYCON1_PAUSE_EN (1 << 9)
228 #define PHYCON1_LINK_STATUS (1 << 8)
229 #define PHYCON1_POL_STATUS (1 << 7)
230 #define PHYCON1_MDIX_STATE (1 << 5)
231 #define PHYCON1_ENERGY_DETECT (1 << 4)
232 #define PHYCON1_ISOLATE (1 << 3)
233 #define PHYCON1_OP_MODE2 (1 << 2)
234 #define PHYCON1_OP_MODE1 (1 << 1)
235 #define PHYCON1_OP_MODE0 (1 << 0)
236 
237 //Operation mode indication
238 #define PHYCON1_OP_MODE_MASK (7 << 0)
239 #define PHYCON1_OP_MODE_AN (0 << 0)
240 #define PHYCON1_OP_MODE_10BT (1 << 0)
241 #define PHYCON1_OP_MODE_100BTX (2 << 0)
242 #define PHYCON1_OP_MODE_10BT_FD (5 << 0)
243 #define PHYCON1_OP_MODE_100BTX_FD (6 << 0)
244 
245 //PHYCON2 register
246 #define PHYCON2_HP_MDIX (1 << 15)
247 #define PHYCON2_MDIX_SEL (1 << 14)
248 #define PHYCON2_PAIR_SWAP_DIS (1 << 13)
249 #define PHYCON2_FORCE_LINK (1 << 11)
250 #define PHYCON2_POWER_SAVING (1 << 10)
251 #define PHYCON2_INT_LEVEL (1 << 9)
252 #define PHYCON2_JABBER_EN (1 << 8)
253 #define PHYCON2_RMII_REF_CLK_SEL (1 << 7)
254 #define PHYCON2_LED_MODE1 (1 << 5)
255 #define PHYCON2_LED_MODE0 (1 << 4)
256 #define PHYCON2_TX_DIS (1 << 3)
257 #define PHYCON2_REMOTE_LOOPBACK (1 << 2)
258 #define PHYCON2_SCRAMBLER_DIS (1 << 0)
259 
260 //C++ guard
261 #ifdef __cplusplus
262  extern "C" {
263 #endif
264 
265 //KSZ8081 Ethernet PHY driver
266 extern const PhyDriver ksz8081PhyDriver;
267 
268 //KSZ8081 related functions
269 error_t ksz8081Init(NetInterface *interface);
270 
271 void ksz8081Tick(NetInterface *interface);
272 
273 void ksz8081EnableIrq(NetInterface *interface);
274 void ksz8081DisableIrq(NetInterface *interface);
275 
276 void ksz8081EventHandler(NetInterface *interface);
277 
278 void ksz8081WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
279 uint16_t ksz8081ReadPhyReg(NetInterface *interface, uint8_t address);
280 
281 void ksz8081DumpPhyReg(NetInterface *interface);
282 
283 //C++ guard
284 #ifdef __cplusplus
285  }
286 #endif
287 
288 #endif
void ksz8081DisableIrq(NetInterface *interface)
Disable interrupts.
error_t ksz8081Init(NetInterface *interface)
KSZ8081 PHY transceiver initialization.
void ksz8081DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
void ksz8081WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
PHY driver.
Definition: nic.h:196
uint16_t ksz8081ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
void ksz8081EnableIrq(NetInterface *interface)
Enable interrupts.
void ksz8081EventHandler(NetInterface *interface)
KSZ8081 event handler.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
const PhyDriver ksz8081PhyDriver
KSZ8081 Ethernet PHY driver.
Network interface controller abstraction layer.
void ksz8081Tick(NetInterface *interface)
KSZ8081 timer handler.