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1 /**
2  * @file ksz8563_driver.h
3  * @brief KSZ8563 3-port Ethernet switch driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.4
29  **/
30 
31 #ifndef _KSZ8563_DRIVER_H
32 #define _KSZ8563_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Port identifiers
38 #define KSZ8563_PORT1 1
39 #define KSZ8563_PORT2 2
40 #define KSZ8563_PORT3 3
41 
42 //Port masks
43 #define KSZ8563_PORT_MASK 0x07
44 #define KSZ8563_PORT1_MASK 0x01
45 #define KSZ8563_PORT2_MASK 0x02
46 #define KSZ8563_PORT3_MASK 0x04
47 
48 //SPI command byte
49 #define KSZ8563_SPI_CMD_WRITE 0x40000000
50 #define KSZ8563_SPI_CMD_READ 0x60000000
51 #define KSZ8563_SPI_CMD_ADDR 0x001FFFE0
52 
53 //Size of static and dynamic MAC tables
54 #define KSZ8563_STATIC_MAC_TABLE_SIZE 16
55 #define KSZ8563_DYNAMIC_MAC_TABLE_SIZE 4096
56 
57 //Tail tag rules (host to KSZ8563)
58 #define KSZ8563_TAIL_TAG_NORMAL_ADDR_LOOKUP 0x40
59 #define KSZ8563_TAIL_TAG_PORT_BLOCKING_OVERRIDE 0x20
60 #define KSZ8563_TAIL_TAG_PRIORITY 0x18
61 #define KSZ8563_TAIL_TAG_DEST_PORT3 0x04
62 #define KSZ8563_TAIL_TAG_DEST_PORT2 0x02
63 #define KSZ8563_TAIL_TAG_DEST_PORT1 0x01
64 
65 //Tail tag rules (KSZ8563 to host)
66 #define KSZ8563_TAIL_TAG_PTP_MSG 0x80
67 #define KSZ8563_TAIL_TAG_SRC_PORT 0x03
68 
69 //KSZ8563 PHY registers
70 #define KSZ8563_BMCR 0x00
71 #define KSZ8563_BMSR 0x01
72 #define KSZ8563_PHYID1 0x02
73 #define KSZ8563_PHYID2 0x03
74 #define KSZ8563_ANAR 0x04
75 #define KSZ8563_ANLPAR 0x05
76 #define KSZ8563_ANER 0x06
77 #define KSZ8563_ANNPR 0x07
78 #define KSZ8563_ANLPNPR 0x08
79 #define KSZ8563_MMDACR 0x0D
80 #define KSZ8563_MMDAADR 0x0E
81 #define KSZ8563_RLB 0x11
82 #define KSZ8563_LINKMD 0x12
83 #define KSZ8563_DPMAPCSS 0x13
84 #define KSZ8563_RXERCTR 0x15
85 #define KSZ8563_ICSR 0x1B
86 #define KSZ8563_AUTOMDI 0x1C
87 #define KSZ8563_PHYCON 0x1F
88 
89 //KSZ8563 MMD registers
90 #define KSZ8563_MMD_LED_MODE 0x02, 0x00
91 #define KSZ8563_MMD_EEE_ADV 0x07, 0x3C
92 
93 //KSZ8563 Switch registers
94 #define KSZ8563_CHIP_ID0 0x0000
95 #define KSZ8563_CHIP_ID1 0x0001
96 #define KSZ8563_CHIP_ID2 0x0002
97 #define KSZ8563_CHIP_ID3 0x0003
98 #define KSZ8563_PME_PIN_CTRL 0x0006
99 #define KSZ8563_CHIP_ID4 0x000F
100 #define KSZ8563_GLOBAL_INT_STAT 0x0010
101 #define KSZ8563_GLOBAL_INT_MASK 0x0014
102 #define KSZ8563_GLOBAL_PORT_INT_STAT 0x0018
103 #define KSZ8563_GLOBAL_PORT_INT_MASK 0x001C
104 #define KSZ8563_SERIAL_IO_CTRL 0x0100
105 #define KSZ8563_IBA_CTRL 0x0104
106 #define KSZ8563_IO_DRIVE_STRENGTH 0x010D
107 #define KSZ8563_IBA_OP_STAT1 0x0110
108 #define KSZ8563_LED_OVERRIDE 0x0120
109 #define KSZ8563_LED_OUTPUT 0x0124
110 #define KSZ8563_LED2_0_LED2_1_SRC 0x0128
111 #define KSZ8563_PWR_DOWN_CTRL0 0x0201
112 #define KSZ8563_LED_STRAP_IN 0x0210
113 #define KSZ8563_SWITCH_OP 0x0300
114 #define KSZ8563_SWITCH_MAC_ADDR0 0x0302
115 #define KSZ8563_SWITCH_MAC_ADDR1 0x0303
116 #define KSZ8563_SWITCH_MAC_ADDR2 0x0304
117 #define KSZ8563_SWITCH_MAC_ADDR3 0x0305
118 #define KSZ8563_SWITCH_MAC_ADDR4 0x0306
119 #define KSZ8563_SWITCH_MAC_ADDR5 0x0307
120 #define KSZ8563_SWITCH_MTU 0x0308
121 #define KSZ8563_SWITCH_ISP_TPID 0x030A
122 #define KSZ8563_AVB_CBS_STRATEGY 0x030E
123 #define KSZ8563_SWITCH_LUE_CTRL0 0x0310
124 #define KSZ8563_SWITCH_LUE_CTRL1 0x0311
125 #define KSZ8563_SWITCH_LUE_CTRL2 0x0312
126 #define KSZ8563_SWITCH_LUE_CTRL3 0x0313
127 #define KSZ8563_ALU_TABLE_INT 0x0314
128 #define KSZ8563_ALU_TABLE_MASK 0x0315
129 #define KSZ8563_ALU_TABLE_ENTRY_INDEX0 0x0316
130 #define KSZ8563_ALU_TABLE_ENTRY_INDEX1 0x0318
131 #define KSZ8563_ALU_TABLE_ENTRY_INDEX2 0x031A
132 #define KSZ8563_UNKNOWN_UNICAST_CTRL 0x0320
133 #define KSZ8563_UNKONWN_MULTICAST_CTRL 0x0324
134 #define KSZ8563_UNKNOWN_VLAN_ID_CTRL 0x0328
135 #define KSZ8563_SWITCH_MAC_CTRL0 0x0330
136 #define KSZ8563_SWITCH_MAC_CTRL1 0x0331
137 #define KSZ8563_SWITCH_MAC_CTRL2 0x0332
138 #define KSZ8563_SWITCH_MAC_CTRL3 0x0333
139 #define KSZ8563_SWITCH_MAC_CTRL4 0x0334
140 #define KSZ8563_SWITCH_MAC_CTRL5 0x0335
141 #define KSZ8563_SWITCH_MIB_CTRL 0x0336
142 #define KSZ8563_802_1P_PRIO_MAPPING0 0x0338
143 #define KSZ8563_802_1P_PRIO_MAPPING1 0x0339
144 #define KSZ8563_802_1P_PRIO_MAPPING2 0x033A
145 #define KSZ8563_802_1P_PRIO_MAPPING3 0x033B
146 #define KSZ8563_IP_DIFFSERV_PRIO_EN 0x033E
147 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING0 0x0340
148 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING1 0x0341
149 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING2 0x0342
150 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING3 0x0343
151 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING4 0x0344
152 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING5 0x0345
153 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING6 0x0346
154 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING7 0x0347
155 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING8 0x0348
156 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING9 0x0349
157 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING10 0x034A
158 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING11 0x034B
159 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING12 0x034C
160 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING13 0x034D
161 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING14 0x034E
162 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING15 0x034F
163 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING16 0x0350
164 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING17 0x0351
165 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING18 0x0352
166 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING19 0x0353
167 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING20 0x0354
168 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING21 0x0355
169 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING22 0x0356
170 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING23 0x0357
171 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING24 0x0358
172 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING25 0x0359
173 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING26 0x035A
174 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING27 0x035B
175 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING28 0x035C
176 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING29 0x035D
177 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING30 0x035E
178 #define KSZ8563_IP_DIFFSERV_PRIO_MAPPING31 0x035F
179 #define KSZ8563_GLOBAL_PORT_MIRROR_SNOOP_CTRL 0x0370
180 #define KSZ8563_WRED_DIFFSERV_COLOR_MAPPING 0x0378
181 #define KSZ8563_PTP_EVENT_MSG_PRIO 0x037C
182 #define KSZ8563_PTP_NON_EVENT_MSG_PRIO 0x037D
183 #define KSZ8563_QUEUE_MGMT_CTRL0 0x0390
184 #define KSZ8563_VLAN_TABLE_ENTRY0 0x0400
185 #define KSZ8563_VLAN_TABLE_ENTRY1 0x0404
186 #define KSZ8563_VLAN_TABLE_ENTRY2 0x0408
187 #define KSZ8563_VLAN_TABLE_INDEX 0x040C
188 #define KSZ8563_VLAN_TABLE_ACCESS_CTRL 0x040E
189 #define KSZ8563_ALU_TABLE_INDEX0 0x0410
190 #define KSZ8563_ALU_TABLE_INDEX1 0x0414
191 #define KSZ8563_ALU_TABLE_CTRL 0x0418
192 #define KSZ8563_STATIC_MCAST_TABLE_CTRL 0x041C
193 #define KSZ8563_ALU_TABLE_ENTRY1 0x0420
194 #define KSZ8563_STATIC_TABLE_ENTRY1 0x0420
195 #define KSZ8563_ALU_TABLE_ENTRY2 0x0424
196 #define KSZ8563_STATIC_TABLE_ENTRY2 0x0424
197 #define KSZ8563_RES_MCAST_TABLE_ENTRY2 0x0424
198 #define KSZ8563_ALU_TABLE_ENTRY3 0x0428
199 #define KSZ8563_STATIC_TABLE_ENTRY3 0x0428
200 #define KSZ8563_ALU_TABLE_ENTRY4 0x042C
201 #define KSZ8563_STATIC_TABLE_ENTRY4 0x042C
202 #define KSZ8563_GLOBAL_PTP_CLK_CTRL 0x0500
203 #define KSZ8563_GLOBAL_PTP_RTC_CLK_PHASE 0x0502
204 #define KSZ8563_GLOBAL_PTP_RTC_CLK_NS_H 0x0504
205 #define KSZ8563_GLOBAL_PTP_RTC_CLK_NS_L 0x0506
206 #define KSZ8563_GLOBAL_PTP_RTC_CLK_S_H 0x0508
207 #define KSZ8563_GLOBAL_PTP_RTC_CLK_S_L 0x050A
208 #define KSZ8563_GLOBAL_PTP_CLK_SUB_NS_RATE_H 0x050C
209 #define KSZ8563_GLOBAL_PTP_CLK_SUB_NS_RATE_L 0x050E
210 #define KSZ8563_GLOBAL_PTP_CLK_TEMP_ADJ_DURATION_H 0x0510
211 #define KSZ8563_GLOBAL_PTP_CLK_TEMP_ADJ_DURATION_L 0x0512
212 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG1 0x0514
213 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG2 0x0516
214 #define KSZ8563_GLOBAL_PTP_DOMAIN_VERSION 0x0518
215 #define KSZ8563_GLOBAL_PTP_UNIT_INDEX 0x0520
216 #define KSZ8563_GPIO_STATUS_MONITOR0 0x0524
217 #define KSZ8563_GPIO_STATUS_MONITOR1 0x0528
218 #define KSZ8563_TS_CTRL_STAT 0x052C
219 #define KSZ8563_TOU_TARGET_TIME_NS 0x0530
220 #define KSZ8563_TOU_TARGET_TIME_S 0x0534
221 #define KSZ8563_TOU_CTRL1 0x0538
222 #define KSZ8563_TOU_CTRL2 0x053C
223 #define KSZ8563_TOU_CTRL3 0x0540
224 #define KSZ8563_TOU_CTRL4 0x0544
225 #define KSZ8563_TOU_CTRL5 0x0548
226 #define KSZ8563_TS_STAT_CTRL 0x0550
227 #define KSZ8563_TS_SAMPLE1_TIME_NS 0x0554
228 #define KSZ8563_TS_SAMPLE1_TIME_S 0x0558
229 #define KSZ8563_TS_SAMPLE1_TIME_PHASE 0x055C
230 #define KSZ8563_TS_SAMPLE2_TIME_NS 0x0560
231 #define KSZ8563_TS_SAMPLE2_TIME_S 0x0564
232 #define KSZ8563_TS_SAMPLE2_TIME_PHASE 0x0568
233 #define KSZ8563_TS_SAMPLE3_TIME_NS 0x056C
234 #define KSZ8563_TS_SAMPLE3_TIME_S 0x0570
235 #define KSZ8563_TS_SAMPLE3_TIME_PHASE 0x0574
236 #define KSZ8563_TS_SAMPLE4_TIME_NS 0x0578
237 #define KSZ8563_TS_SAMPLE4_TIME_S 0x057C
238 #define KSZ8563_TS_SAMPLE4_TIME_PHASE 0x0580
239 #define KSZ8563_TS_SAMPLE5_TIME_NS 0x0584
240 #define KSZ8563_TS_SAMPLE5_TIME_S 0x0588
241 #define KSZ8563_TS_SAMPLE5_TIME_PHASE 0x058C
242 #define KSZ8563_TS_SAMPLE6_TIME_NS 0x0590
243 #define KSZ8563_TS_SAMPLE6_TIME_S 0x0594
244 #define KSZ8563_TS_SAMPLE6_TIME_PHASE 0x0598
245 #define KSZ8563_TS_SAMPLE7_TIME_NS 0x059C
246 #define KSZ8563_TS_SAMPLE7_TIME_S 0x05A0
247 #define KSZ8563_TS_SAMPLE7_TIME_PHASE 0x05A4
248 #define KSZ8563_TS_SAMPLE8_TIME_NS 0x05A8
249 #define KSZ8563_TS_SAMPLE8_TIME_S 0x05AC
250 #define KSZ8563_TS_SAMPLE8_TIME_PHASE 0x05B0
251 #define KSZ8563_PORT1_DEFAULT_TAG0 0x1000
252 #define KSZ8563_PORT1_DEFAULT_TAG1 0x1001
253 #define KSZ8563_PORT1_AVB_SR_CLASS1_TAG0 0x1004
254 #define KSZ8563_PORT1_AVB_SR_CLASS1_TAG1 0x1005
255 #define KSZ8563_PORT1_AVB_SR_CLASS2_TAG0 0x1006
256 #define KSZ8563_PORT1_AVB_SR_CLASS2_TAG1 0x1007
257 #define KSZ8563_PORT1_AVB_SR_CLASS1_TYPE 0x1008
258 #define KSZ8563_PORT1_AVB_SR_CLASS2_TYPE 0x100A
259 #define KSZ8563_PORT1_PME_WOL_EVENT 0x1013
260 #define KSZ8563_PORT1_PME_WOL_EN 0x1017
261 #define KSZ8563_PORT1_INT_STATUS 0x101B
262 #define KSZ8563_PORT1_INT_MASK 0x101F
263 #define KSZ8563_PORT1_OP_CTRL0 0x1020
264 #define KSZ8563_PORT1_OP_CTRL1 0x1021
265 #define KSZ8563_PORT1_STATUS 0x1030
266 #define KSZ8563_PORT1_MAC_CTRL0 0x1400
267 #define KSZ8563_PORT1_MAC_CTRL1 0x1401
268 #define KSZ8563_PORT1_IG_RATE_LIMIT_CTRL 0x1403
269 #define KSZ8563_PORT1_PRIO0_IG_LIMIT_CTRL 0x1410
270 #define KSZ8563_PORT1_PRIO1_IG_LIMIT_CTRL 0x1411
271 #define KSZ8563_PORT1_PRIO2_IG_LIMIT_CTRL 0x1412
272 #define KSZ8563_PORT1_PRIO3_IG_LIMIT_CTRL 0x1413
273 #define KSZ8563_PORT1_PRIO4_IG_LIMIT_CTRL 0x1414
274 #define KSZ8563_PORT1_PRIO5_IG_LIMIT_CTRL 0x1415
275 #define KSZ8563_PORT1_PRIO6_IG_LIMIT_CTRL 0x1416
276 #define KSZ8563_PORT1_PRIO7_IG_LIMIT_CTRL 0x1417
277 #define KSZ8563_PORT1_QUEUE0_EG_LIMIT_CTRL 0x1420
278 #define KSZ8563_PORT1_QUEUE1_EG_LIMIT_CTRL 0x1421
279 #define KSZ8563_PORT1_QUEUE2_EG_LIMIT_CTRL 0x1422
280 #define KSZ8563_PORT1_QUEUE3_EG_LIMIT_CTRL 0x1423
281 #define KSZ8563_PORT1_MIB_CTRL_STAT 0x1500
282 #define KSZ8563_PORT1_MIB_DATA 0x1504
283 #define KSZ8563_PORT1_ACL_ACCESS0 0x1600
284 #define KSZ8563_PORT1_ACL_ACCESS1 0x1601
285 #define KSZ8563_PORT1_ACL_ACCESS2 0x1602
286 #define KSZ8563_PORT1_ACL_ACCESS3 0x1603
287 #define KSZ8563_PORT1_ACL_ACCESS4 0x1604
288 #define KSZ8563_PORT1_ACL_ACCESS5 0x1605
289 #define KSZ8563_PORT1_ACL_ACCESS6 0x1606
290 #define KSZ8563_PORT1_ACL_ACCESS7 0x1607
291 #define KSZ8563_PORT1_ACL_ACCESS8 0x1608
292 #define KSZ8563_PORT1_ACL_ACCESS9 0x1609
293 #define KSZ8563_PORT1_ACL_ACCESS10 0x160A
294 #define KSZ8563_PORT1_ACL_ACCESS11 0x160B
295 #define KSZ8563_PORT1_ACL_ACCESS12 0x160C
296 #define KSZ8563_PORT1_ACL_ACCESS13 0x160D
297 #define KSZ8563_PORT1_ACL_ACCESS14 0x160E
298 #define KSZ8563_PORT1_ACL_ACCESS15 0x160F
299 #define KSZ8563_PORT1_ACL_BYTE_EN_MSB 0x1610
300 #define KSZ8563_PORT1_ACL_BYTE_EN_LSB 0x1611
301 #define KSZ8563_PORT1_ACL_ACCESS_CTRL0 0x1612
302 #define KSZ8563_PORT1_MIRRORING_CTRL 0x1800
303 #define KSZ8563_PORT1_PRIO_CTRL 0x1801
304 #define KSZ8563_PORT1_IG_MAC_CTRL 0x1802
305 #define KSZ8563_PORT1_AUTH_CTRL 0x1803
306 #define KSZ8563_PORT1_PTR 0x1804
307 #define KSZ8563_PORT1_PRIO_TO_QUEUE_MAPPING 0x1808
308 #define KSZ8563_PORT1_POLICE_CTRL 0x180C
309 #define KSZ8563_PORT1_TX_QUEUE_INDEX 0x1900
310 #define KSZ8563_PORT1_TX_QUEUE_PVID 0x1904
311 #define KSZ8563_PORT1_TX_QUEUE_CTRL0 0x1914
312 #define KSZ8563_PORT1_TX_QUEUE_CTRL1 0x1915
313 #define KSZ8563_PORT1_TX_CREDIT_SHAPER_CTRL0 0x1916
314 #define KSZ8563_PORT1_TX_CREDIT_SHAPER_CTRL1 0x1918
315 #define KSZ8563_PORT1_TX_CREDIT_SHAPER_CTRL2 0x191A
316 #define KSZ8563_PORT1_CTRL0 0x1A00
317 #define KSZ8563_PORT1_CTRL1 0x1A04
318 #define KSZ8563_PORT1_CTRL2 0x1B00
319 #define KSZ8563_PORT1_MSTP_PTR 0x1B01
320 #define KSZ8563_PORT1_MSTP_STATE 0x1B04
321 #define KSZ8563_PORT1_PTP_RX_LATENCY 0x1C00
322 #define KSZ8563_PORT1_PTP_TX_LATENCY 0x1C02
323 #define KSZ8563_PORT1_PTP_ASYM_CORRECTION 0x1C04
324 #define KSZ8563_PORT1_PTP_XDLY_REQ_TS_H 0x1C08
325 #define KSZ8563_PORT1_PTP_XDLY_REQ_TS_L 0x1C0A
326 #define KSZ8563_PORT1_PTP_SYNC_TS_H 0x1C0C
327 #define KSZ8563_PORT1_PTP_SYNC_TS_L 0x1C0E
328 #define KSZ8563_PORT1_PTP_PDLY_RESP_TS_H 0x1C10
329 #define KSZ8563_PORT1_PTP_PDLY_RESP_TS_L 0x1C12
330 #define KSZ8563_PORT1_PTP_TS_INT_STAT 0x1C14
331 #define KSZ8563_PORT1_PTP_TS_INT_EN 0x1C16
332 #define KSZ8563_PORT1_PTP_LINK_DELAY 0x1C18
333 #define KSZ8563_PORT2_DEFAULT_TAG0 0x2000
334 #define KSZ8563_PORT2_DEFAULT_TAG1 0x2001
335 #define KSZ8563_PORT2_AVB_SR_CLASS1_TAG0 0x2004
336 #define KSZ8563_PORT2_AVB_SR_CLASS1_TAG1 0x2005
337 #define KSZ8563_PORT2_AVB_SR_CLASS2_TAG0 0x2006
338 #define KSZ8563_PORT2_AVB_SR_CLASS2_TAG1 0x2007
339 #define KSZ8563_PORT2_AVB_SR_CLASS1_TYPE 0x2008
340 #define KSZ8563_PORT2_AVB_SR_CLASS2_TYPE 0x200A
341 #define KSZ8563_PORT2_PME_WOL_EVENT 0x2013
342 #define KSZ8563_PORT2_PME_WOL_EN 0x2017
343 #define KSZ8563_PORT2_INT_STATUS 0x201B
344 #define KSZ8563_PORT2_INT_MASK 0x201F
345 #define KSZ8563_PORT2_OP_CTRL0 0x2020
346 #define KSZ8563_PORT2_OP_CTRL1 0x2021
347 #define KSZ8563_PORT2_STATUS 0x2030
348 #define KSZ8563_PORT2_MAC_CTRL0 0x2400
349 #define KSZ8563_PORT2_MAC_CTRL1 0x2401
350 #define KSZ8563_PORT2_IG_RATE_LIMIT_CTRL 0x2403
351 #define KSZ8563_PORT2_PRIO0_IG_LIMIT_CTRL 0x2410
352 #define KSZ8563_PORT2_PRIO1_IG_LIMIT_CTRL 0x2411
353 #define KSZ8563_PORT2_PRIO2_IG_LIMIT_CTRL 0x2412
354 #define KSZ8563_PORT2_PRIO3_IG_LIMIT_CTRL 0x2413
355 #define KSZ8563_PORT2_PRIO4_IG_LIMIT_CTRL 0x2414
356 #define KSZ8563_PORT2_PRIO5_IG_LIMIT_CTRL 0x2415
357 #define KSZ8563_PORT2_PRIO6_IG_LIMIT_CTRL 0x2416
358 #define KSZ8563_PORT2_PRIO7_IG_LIMIT_CTRL 0x2417
359 #define KSZ8563_PORT2_QUEUE0_EG_LIMIT_CTRL 0x2420
360 #define KSZ8563_PORT2_QUEUE1_EG_LIMIT_CTRL 0x2421
361 #define KSZ8563_PORT2_QUEUE2_EG_LIMIT_CTRL 0x2422
362 #define KSZ8563_PORT2_QUEUE3_EG_LIMIT_CTRL 0x2423
363 #define KSZ8563_PORT2_MIB_CTRL_STAT 0x2500
364 #define KSZ8563_PORT2_MIB_DATA 0x2504
365 #define KSZ8563_PORT2_ACL_ACCESS0 0x2600
366 #define KSZ8563_PORT2_ACL_ACCESS1 0x2601
367 #define KSZ8563_PORT2_ACL_ACCESS2 0x2602
368 #define KSZ8563_PORT2_ACL_ACCESS3 0x2603
369 #define KSZ8563_PORT2_ACL_ACCESS4 0x2604
370 #define KSZ8563_PORT2_ACL_ACCESS5 0x2605
371 #define KSZ8563_PORT2_ACL_ACCESS6 0x2606
372 #define KSZ8563_PORT2_ACL_ACCESS7 0x2607
373 #define KSZ8563_PORT2_ACL_ACCESS8 0x2608
374 #define KSZ8563_PORT2_ACL_ACCESS9 0x2609
375 #define KSZ8563_PORT2_ACL_ACCESS10 0x260A
376 #define KSZ8563_PORT2_ACL_ACCESS11 0x260B
377 #define KSZ8563_PORT2_ACL_ACCESS12 0x260C
378 #define KSZ8563_PORT2_ACL_ACCESS13 0x260D
379 #define KSZ8563_PORT2_ACL_ACCESS14 0x260E
380 #define KSZ8563_PORT2_ACL_ACCESS15 0x260F
381 #define KSZ8563_PORT2_ACL_BYTE_EN_MSB 0x2610
382 #define KSZ8563_PORT2_ACL_BYTE_EN_LSB 0x2611
383 #define KSZ8563_PORT2_ACL_ACCESS_CTRL0 0x2612
384 #define KSZ8563_PORT2_MIRRORING_CTRL 0x2800
385 #define KSZ8563_PORT2_PRIO_CTRL 0x2801
386 #define KSZ8563_PORT2_IG_MAC_CTRL 0x2802
387 #define KSZ8563_PORT2_AUTH_CTRL 0x2803
388 #define KSZ8563_PORT2_PTR 0x2804
389 #define KSZ8563_PORT2_PRIO_TO_QUEUE_MAPPING 0x2808
390 #define KSZ8563_PORT2_POLICE_CTRL 0x280C
391 #define KSZ8563_PORT2_TX_QUEUE_INDEX 0x2900
392 #define KSZ8563_PORT2_TX_QUEUE_PVID 0x2904
393 #define KSZ8563_PORT2_TX_QUEUE_CTRL0 0x2914
394 #define KSZ8563_PORT2_TX_QUEUE_CTRL1 0x2915
395 #define KSZ8563_PORT2_TX_CREDIT_SHAPER_CTRL0 0x2916
396 #define KSZ8563_PORT2_TX_CREDIT_SHAPER_CTRL1 0x2918
397 #define KSZ8563_PORT2_TX_CREDIT_SHAPER_CTRL2 0x291A
398 #define KSZ8563_PORT2_CTRL0 0x2A00
399 #define KSZ8563_PORT2_CTRL1 0x2A04
400 #define KSZ8563_PORT2_CTRL2 0x2B00
401 #define KSZ8563_PORT2_MSTP_PTR 0x2B01
402 #define KSZ8563_PORT2_MSTP_STATE 0x2B04
403 #define KSZ8563_PORT2_PTP_RX_LATENCY 0x2C00
404 #define KSZ8563_PORT2_PTP_TX_LATENCY 0x2C02
405 #define KSZ8563_PORT2_PTP_ASYM_CORRECTION 0x2C04
406 #define KSZ8563_PORT2_PTP_XDLY_REQ_TS_H 0x2C08
407 #define KSZ8563_PORT2_PTP_XDLY_REQ_TS_L 0x2C0A
408 #define KSZ8563_PORT2_PTP_SYNC_TS_H 0x2C0C
409 #define KSZ8563_PORT2_PTP_SYNC_TS_L 0x2C0E
410 #define KSZ8563_PORT2_PTP_PDLY_RESP_TS_H 0x2C10
411 #define KSZ8563_PORT2_PTP_PDLY_RESP_TS_L 0x2C12
412 #define KSZ8563_PORT2_PTP_TS_INT_STAT 0x2C14
413 #define KSZ8563_PORT2_PTP_TS_INT_EN 0x2C16
414 #define KSZ8563_PORT2_PTP_LINK_DELAY 0x2C18
415 #define KSZ8563_PORT3_DEFAULT_TAG0 0x3000
416 #define KSZ8563_PORT3_DEFAULT_TAG1 0x3001
417 #define KSZ8563_PORT3_AVB_SR_CLASS1_TAG0 0x3004
418 #define KSZ8563_PORT3_AVB_SR_CLASS1_TAG1 0x3005
419 #define KSZ8563_PORT3_AVB_SR_CLASS2_TAG0 0x3006
420 #define KSZ8563_PORT3_AVB_SR_CLASS2_TAG1 0x3007
421 #define KSZ8563_PORT3_AVB_SR_CLASS1_TYPE 0x3008
422 #define KSZ8563_PORT3_AVB_SR_CLASS2_TYPE 0x300A
423 #define KSZ8563_PORT3_PME_WOL_EVENT 0x3013
424 #define KSZ8563_PORT3_PME_WOL_EN 0x3017
425 #define KSZ8563_PORT3_INT_STATUS 0x301B
426 #define KSZ8563_PORT3_INT_MASK 0x301F
427 #define KSZ8563_PORT3_OP_CTRL0 0x3020
428 #define KSZ8563_PORT3_OP_CTRL1 0x3021
429 #define KSZ8563_PORT3_STATUS 0x3030
430 #define KSZ8563_PORT3_XMII_CTRL0 0x3300
431 #define KSZ8563_PORT3_XMII_CTRL1 0x3301
432 #define KSZ8563_PORT3_XMII_CTRL3 0x3303
433 #define KSZ8563_PORT3_MAC_CTRL0 0x3400
434 #define KSZ8563_PORT3_MAC_CTRL1 0x3401
435 #define KSZ8563_PORT3_IG_RATE_LIMIT_CTRL 0x3403
436 #define KSZ8563_PORT3_PRIO0_IG_LIMIT_CTRL 0x3410
437 #define KSZ8563_PORT3_PRIO1_IG_LIMIT_CTRL 0x3411
438 #define KSZ8563_PORT3_PRIO2_IG_LIMIT_CTRL 0x3412
439 #define KSZ8563_PORT3_PRIO3_IG_LIMIT_CTRL 0x3413
440 #define KSZ8563_PORT3_PRIO4_IG_LIMIT_CTRL 0x3414
441 #define KSZ8563_PORT3_PRIO5_IG_LIMIT_CTRL 0x3415
442 #define KSZ8563_PORT3_PRIO6_IG_LIMIT_CTRL 0x3416
443 #define KSZ8563_PORT3_PRIO7_IG_LIMIT_CTRL 0x3417
444 #define KSZ8563_PORT3_QUEUE0_EG_LIMIT_CTRL 0x3420
445 #define KSZ8563_PORT3_QUEUE1_EG_LIMIT_CTRL 0x3421
446 #define KSZ8563_PORT3_QUEUE2_EG_LIMIT_CTRL 0x3422
447 #define KSZ8563_PORT3_QUEUE3_EG_LIMIT_CTRL 0x3423
448 #define KSZ8563_PORT3_MIB_CTRL_STAT 0x3500
449 #define KSZ8563_PORT3_MIB_DATA 0x3504
450 #define KSZ8563_PORT3_ACL_ACCESS0 0x3600
451 #define KSZ8563_PORT3_ACL_ACCESS1 0x3601
452 #define KSZ8563_PORT3_ACL_ACCESS2 0x3602
453 #define KSZ8563_PORT3_ACL_ACCESS3 0x3603
454 #define KSZ8563_PORT3_ACL_ACCESS4 0x3604
455 #define KSZ8563_PORT3_ACL_ACCESS5 0x3605
456 #define KSZ8563_PORT3_ACL_ACCESS6 0x3606
457 #define KSZ8563_PORT3_ACL_ACCESS7 0x3607
458 #define KSZ8563_PORT3_ACL_ACCESS8 0x3608
459 #define KSZ8563_PORT3_ACL_ACCESS9 0x3609
460 #define KSZ8563_PORT3_ACL_ACCESS10 0x360A
461 #define KSZ8563_PORT3_ACL_ACCESS11 0x360B
462 #define KSZ8563_PORT3_ACL_ACCESS12 0x360C
463 #define KSZ8563_PORT3_ACL_ACCESS13 0x360D
464 #define KSZ8563_PORT3_ACL_ACCESS14 0x360E
465 #define KSZ8563_PORT3_ACL_ACCESS15 0x360F
466 #define KSZ8563_PORT3_ACL_BYTE_EN_MSB 0x3610
467 #define KSZ8563_PORT3_ACL_BYTE_EN_LSB 0x3611
468 #define KSZ8563_PORT3_ACL_ACCESS_CTRL0 0x3612
469 #define KSZ8563_PORT3_MIRRORING_CTRL 0x3800
470 #define KSZ8563_PORT3_PRIO_CTRL 0x3801
471 #define KSZ8563_PORT3_IG_MAC_CTRL 0x3802
472 #define KSZ8563_PORT3_AUTH_CTRL 0x3803
473 #define KSZ8563_PORT3_PTR 0x3804
474 #define KSZ8563_PORT3_PRIO_TO_QUEUE_MAPPING 0x3808
475 #define KSZ8563_PORT3_POLICE_CTRL 0x380C
476 #define KSZ8563_PORT3_TX_QUEUE_INDEX 0x3900
477 #define KSZ8563_PORT3_TX_QUEUE_PVID 0x3904
478 #define KSZ8563_PORT3_TX_QUEUE_CTRL0 0x3914
479 #define KSZ8563_PORT3_TX_QUEUE_CTRL1 0x3915
480 #define KSZ8563_PORT3_TX_CREDIT_SHAPER_CTRL0 0x3916
481 #define KSZ8563_PORT3_TX_CREDIT_SHAPER_CTRL1 0x3918
482 #define KSZ8563_PORT3_TX_CREDIT_SHAPER_CTRL2 0x391A
483 #define KSZ8563_PORT3_CTRL0 0x3A00
484 #define KSZ8563_PORT3_CTRL1 0x3A04
485 #define KSZ8563_PORT3_CTRL2 0x3B00
486 #define KSZ8563_PORT3_MSTP_PTR 0x3B01
487 #define KSZ8563_PORT3_MSTP_STATE 0x3B04
488 #define KSZ8563_PORT3_PTP_RX_LATENCY 0x3C00
489 #define KSZ8563_PORT3_PTP_TX_LATENCY 0x3C02
490 #define KSZ8563_PORT3_PTP_ASYM_CORRECTION 0x3C04
491 #define KSZ8563_PORT3_PTP_XDLY_REQ_TS_H 0x3C08
492 #define KSZ8563_PORT3_PTP_XDLY_REQ_TS_L 0x3C0A
493 #define KSZ8563_PORT3_PTP_SYNC_TS_H 0x3C0C
494 #define KSZ8563_PORT3_PTP_SYNC_TS_L 0x3C0E
495 #define KSZ8563_PORT3_PTP_PDLY_RESP_TS_H 0x3C10
496 #define KSZ8563_PORT3_PTP_PDLY_RESP_TS_L 0x3C12
497 #define KSZ8563_PORT3_PTP_TS_INT_STAT 0x3C14
498 #define KSZ8563_PORT3_PTP_TS_INT_EN 0x3C16
499 #define KSZ8563_PORT3_PTP_LINK_DELAY 0x3C18
500 
501 //KSZ8563 Switch register access macros
502 #define KSZ8563_PORTn_DEFAULT_TAG0(port) (0x0000 + ((port) * 0x1000))
503 #define KSZ8563_PORTn_DEFAULT_TAG1(port) (0x0001 + ((port) * 0x1000))
504 #define KSZ8563_PORTn_AVB_SR_CLASS1_TAG0(port) (0x0004 + ((port) * 0x1000))
505 #define KSZ8563_PORTn_AVB_SR_CLASS1_TAG1(port) (0x0005 + ((port) * 0x1000))
506 #define KSZ8563_PORTn_AVB_SR_CLASS2_TAG0(port) (0x0006 + ((port) * 0x1000))
507 #define KSZ8563_PORTn_AVB_SR_CLASS2_TAG1(port) (0x0007 + ((port) * 0x1000))
508 #define KSZ8563_PORTn_AVB_SR_CLASS1_TYPE(port) (0x0008 + ((port) * 0x1000))
509 #define KSZ8563_PORTn_AVB_SR_CLASS2_TYPE(port) (0x000A + ((port) * 0x1000))
510 #define KSZ8563_PORTn_PME_WOL_EVENT(port) (0x0013 + ((port) * 0x1000))
511 #define KSZ8563_PORTn_PME_WOL_EN(port) (0x0017 + ((port) * 0x1000))
512 #define KSZ8563_PORTn_INT_STATUS(port) (0x001B + ((port) * 0x1000))
513 #define KSZ8563_PORTn_INT_MASK(port) (0x001F + ((port) * 0x1000))
514 #define KSZ8563_PORTn_OP_CTRL0(port) (0x0020 + ((port) * 0x1000))
515 #define KSZ8563_PORTn_OP_CTRL1(port) (0x0021 + ((port) * 0x1000))
516 #define KSZ8563_PORTn_STATUS(port) (0x0030 + ((port) * 0x1000))
517 #define KSZ8563_PORTn_XMII_CTRL0(port) (0x0300 + ((port) * 0x1000))
518 #define KSZ8563_PORTn_XMII_CTRL1(port) (0x0301 + ((port) * 0x1000))
519 #define KSZ8563_PORTn_XMII_CTRL3(port) (0x0303 + ((port) * 0x1000))
520 #define KSZ8563_PORTn_MAC_CTRL0(port) (0x0400 + ((port) * 0x1000))
521 #define KSZ8563_PORTn_MAC_CTRL1(port) (0x0401 + ((port) * 0x1000))
522 #define KSZ8563_PORTn_IG_RATE_LIMIT_CTRL(port) (0x0403 + ((port) * 0x1000))
523 #define KSZ8563_PORTn_PRIO0_IG_LIMIT_CTRL(port) (0x0410 + ((port) * 0x1000))
524 #define KSZ8563_PORTn_PRIO1_IG_LIMIT_CTRL(port) (0x0411 + ((port) * 0x1000))
525 #define KSZ8563_PORTn_PRIO2_IG_LIMIT_CTRL(port) (0x0412 + ((port) * 0x1000))
526 #define KSZ8563_PORTn_PRIO3_IG_LIMIT_CTRL(port) (0x0413 + ((port) * 0x1000))
527 #define KSZ8563_PORTn_PRIO4_IG_LIMIT_CTRL(port) (0x0414 + ((port) * 0x1000))
528 #define KSZ8563_PORTn_PRIO5_IG_LIMIT_CTRL(port) (0x0415 + ((port) * 0x1000))
529 #define KSZ8563_PORTn_PRIO6_IG_LIMIT_CTRL(port) (0x0416 + ((port) * 0x1000))
530 #define KSZ8563_PORTn_PRIO7_IG_LIMIT_CTRL(port) (0x0417 + ((port) * 0x1000))
531 #define KSZ8563_PORTn_QUEUE0_EG_LIMIT_CTRL(port) (0x0420 + ((port) * 0x1000))
532 #define KSZ8563_PORTn_QUEUE1_EG_LIMIT_CTRL(port) (0x0421 + ((port) * 0x1000))
533 #define KSZ8563_PORTn_QUEUE2_EG_LIMIT_CTRL(port) (0x0422 + ((port) * 0x1000))
534 #define KSZ8563_PORTn_QUEUE3_EG_LIMIT_CTRL(port) (0x0423 + ((port) * 0x1000))
535 #define KSZ8563_PORTn_MIB_CTRL_STAT(port) (0x0500 + ((port) * 0x1000))
536 #define KSZ8563_PORTn_MIB_DATA(port) (0x0504 + ((port) * 0x1000))
537 #define KSZ8563_PORTn_ACL_ACCESS0(port) (0x0600 + ((port) * 0x1000))
538 #define KSZ8563_PORTn_ACL_ACCESS1(port) (0x0601 + ((port) * 0x1000))
539 #define KSZ8563_PORTn_ACL_ACCESS2(port) (0x0602 + ((port) * 0x1000))
540 #define KSZ8563_PORTn_ACL_ACCESS3(port) (0x0603 + ((port) * 0x1000))
541 #define KSZ8563_PORTn_ACL_ACCESS4(port) (0x0604 + ((port) * 0x1000))
542 #define KSZ8563_PORTn_ACL_ACCESS5(port) (0x0605 + ((port) * 0x1000))
543 #define KSZ8563_PORTn_ACL_ACCESS6(port) (0x0606 + ((port) * 0x1000))
544 #define KSZ8563_PORTn_ACL_ACCESS7(port) (0x0607 + ((port) * 0x1000))
545 #define KSZ8563_PORTn_ACL_ACCESS8(port) (0x0608 + ((port) * 0x1000))
546 #define KSZ8563_PORTn_ACL_ACCESS9(port) (0x0609 + ((port) * 0x1000))
547 #define KSZ8563_PORTn_ACL_ACCESS10(port) (0x060A + ((port) * 0x1000))
548 #define KSZ8563_PORTn_ACL_ACCESS11(port) (0x060B + ((port) * 0x1000))
549 #define KSZ8563_PORTn_ACL_ACCESS12(port) (0x060C + ((port) * 0x1000))
550 #define KSZ8563_PORTn_ACL_ACCESS13(port) (0x060D + ((port) * 0x1000))
551 #define KSZ8563_PORTn_ACL_ACCESS14(port) (0x060E + ((port) * 0x1000))
552 #define KSZ8563_PORTn_ACL_ACCESS15(port) (0x060F + ((port) * 0x1000))
553 #define KSZ8563_PORTn_ACL_BYTE_EN_MSB(port) (0x0610 + ((port) * 0x1000))
554 #define KSZ8563_PORTn_ACL_BYTE_EN_LSB(port) (0x0611 + ((port) * 0x1000))
555 #define KSZ8563_PORTn_ACL_ACCESS_CTRL0(port) (0x0612 + ((port) * 0x1000))
556 #define KSZ8563_PORTn_MIRRORING_CTRL(port) (0x0800 + ((port) * 0x1000))
557 #define KSZ8563_PORTn_PRIO_CTRL(port) (0x0801 + ((port) * 0x1000))
558 #define KSZ8563_PORTn_IG_MAC_CTRL(port) (0x0802 + ((port) * 0x1000))
559 #define KSZ8563_PORTn_AUTH_CTRL(port) (0x0803 + ((port) * 0x1000))
560 #define KSZ8563_PORTn_PTR(port) (0x0804 + ((port) * 0x1000))
561 #define KSZ8563_PORTn_PRIO_TO_QUEUE_MAPPING(port) (0x0808 + ((port) * 0x1000))
562 #define KSZ8563_PORTn_POLICE_CTRL(port) (0x080C + ((port) * 0x1000))
563 #define KSZ8563_PORTn_TX_QUEUE_INDEX(port) (0x0900 + ((port) * 0x1000))
564 #define KSZ8563_PORTn_TX_QUEUE_PVID(port) (0x0904 + ((port) * 0x1000))
565 #define KSZ8563_PORTn_TX_QUEUE_CTRL0(port) (0x0914 + ((port) * 0x1000))
566 #define KSZ8563_PORTn_TX_QUEUE_CTRL1(port) (0x0915 + ((port) * 0x1000))
567 #define KSZ8563_PORTn_TX_CREDIT_SHAPER_CTRL0(port) (0x0916 + ((port) * 0x1000))
568 #define KSZ8563_PORTn_TX_CREDIT_SHAPER_CTRL1(port) (0x0918 + ((port) * 0x1000))
569 #define KSZ8563_PORTn_TX_CREDIT_SHAPER_CTRL2(port) (0x091A + ((port) * 0x1000))
570 #define KSZ8563_PORTn_CTRL0(port) (0x0A00 + ((port) * 0x1000))
571 #define KSZ8563_PORTn_CTRL1(port) (0x0A04 + ((port) * 0x1000))
572 #define KSZ8563_PORTn_CTRL2(port) (0x0B00 + ((port) * 0x1000))
573 #define KSZ8563_PORTn_MSTP_PTR(port) (0x0B01 + ((port) * 0x1000))
574 #define KSZ8563_PORTn_MSTP_STATE(port) (0x0B04 + ((port) * 0x1000))
575 #define KSZ8563_PORTn_PTP_RX_LATENCY(port) (0x0C00 + ((port) * 0x1000))
576 #define KSZ8563_PORTn_PTP_TX_LATENCY(port) (0x0C02 + ((port) * 0x1000))
577 #define KSZ8563_PORTn_PTP_ASYM_CORRECTION(port) (0x0C04 + ((port) * 0x1000))
578 #define KSZ8563_PORTn_PTP_XDLY_REQ_TS_H(port) (0x0C08 + ((port) * 0x1000))
579 #define KSZ8563_PORTn_PTP_XDLY_REQ_TS_L(port) (0x0C0A + ((port) * 0x1000))
580 #define KSZ8563_PORTn_PTP_SYNC_TS_H(port) (0x0C0C + ((port) * 0x1000))
581 #define KSZ8563_PORTn_PTP_SYNC_TS_L(port) (0x0C0E + ((port) * 0x1000))
582 #define KSZ8563_PORTn_PTP_PDLY_RESP_TS_H(port) (0x0C10 + ((port) * 0x1000))
583 #define KSZ8563_PORTn_PTP_PDLY_RESP_TS_L(port) (0x0C12 + ((port) * 0x1000))
584 #define KSZ8563_PORTn_PTP_TS_INT_STAT(port) (0x0C14 + ((port) * 0x1000))
585 #define KSZ8563_PORTn_PTP_TS_INT_EN(port) (0x0C16 + ((port) * 0x1000))
586 #define KSZ8563_PORTn_PTP_LINK_DELAY(port) (0x0C18 + ((port) * 0x1000))
587 #define KSZ8563_PORTn_ETH_PHY_REG(port, addr) (0x0100 + ((port) * 0x1000) + ((addr) * 2))
588 
589 //PHY Basic Control register
590 #define KSZ8563_BMCR_RESET 0x8000
591 #define KSZ8563_BMCR_LOOPBACK 0x4000
592 #define KSZ8563_BMCR_SPEED_SEL 0x2000
593 #define KSZ8563_BMCR_AN_EN 0x1000
594 #define KSZ8563_BMCR_POWER_DOWN 0x0800
595 #define KSZ8563_BMCR_ISOLATE 0x0400
596 #define KSZ8563_BMCR_RESTART_AN 0x0200
597 #define KSZ8563_BMCR_DUPLEX_MODE 0x0100
598 #define KSZ8563_BMCR_COL_TEST 0x0080
599 
600 //PHY Basic Status register
601 #define KSZ8563_BMSR_100BT4 0x8000
602 #define KSZ8563_BMSR_100BTX_FD 0x4000
603 #define KSZ8563_BMSR_100BTX_HD 0x2000
604 #define KSZ8563_BMSR_10BT_FD 0x1000
605 #define KSZ8563_BMSR_10BT_HD 0x0800
606 #define KSZ8563_BMSR_EXTENDED_STATUS 0x0100
607 #define KSZ8563_BMSR_MF_PREAMBLE_SUPPR 0x0040
608 #define KSZ8563_BMSR_AN_COMPLETE 0x0020
609 #define KSZ8563_BMSR_REMOTE_FAULT 0x0010
610 #define KSZ8563_BMSR_AN_CAPABLE 0x0008
611 #define KSZ8563_BMSR_LINK_STATUS 0x0004
612 #define KSZ8563_BMSR_JABBER_DETECT 0x0002
613 #define KSZ8563_BMSR_EXTENDED_CAPABLE 0x0001
614 
615 //PHY ID High register
616 #define KSZ8563_PHYID1_DEFAULT 0x0022
617 
618 //PHY ID Low register
619 #define KSZ8563_PHYID2_DEFAULT 0x1631
620 
621 //PHY Auto-Negotiation Advertisement register
622 #define KSZ8563_ANAR_NEXT_PAGE 0x8000
623 #define KSZ8563_ANAR_REMOTE_FAULT 0x2000
624 #define KSZ8563_ANAR_PAUSE 0x0C00
625 #define KSZ8563_ANAR_100BT4 0x0200
626 #define KSZ8563_ANAR_100BTX_FD 0x0100
627 #define KSZ8563_ANAR_100BTX_HD 0x0080
628 #define KSZ8563_ANAR_10BT_FD 0x0040
629 #define KSZ8563_ANAR_10BT_HD 0x0020
630 #define KSZ8563_ANAR_SELECTOR 0x001F
631 #define KSZ8563_ANAR_SELECTOR_DEFAULT 0x0001
632 
633 //PHY Auto-Negotiation Link Partner Ability register
634 #define KSZ8563_ANLPAR_NEXT_PAGE 0x8000
635 #define KSZ8563_ANLPAR_ACK 0x4000
636 #define KSZ8563_ANLPAR_REMOTE_FAULT 0x2000
637 #define KSZ8563_ANLPAR_PAUSE 0x0C00
638 #define KSZ8563_ANLPAR_100BT4 0x0200
639 #define KSZ8563_ANLPAR_100BTX_FD 0x0100
640 #define KSZ8563_ANLPAR_100BTX_HD 0x0080
641 #define KSZ8563_ANLPAR_10BT_FD 0x0040
642 #define KSZ8563_ANLPAR_10BT_HD 0x0020
643 #define KSZ8563_ANLPAR_SELECTOR 0x001F
644 #define KSZ8563_ANLPAR_SELECTOR_DEFAULT 0x0001
645 
646 //PHY Auto-Negotiation Expansion Status register
647 #define KSZ8563_ANER_PAR_DETECT_FAULT 0x0010
648 #define KSZ8563_ANER_LP_NEXT_PAGE_ABLE 0x0008
649 #define KSZ8563_ANER_NEXT_PAGE_ABLE 0x0004
650 #define KSZ8563_ANER_PAGE_RECEIVED 0x0002
651 #define KSZ8563_ANER_LP_AN_ABLE 0x0001
652 
653 //PHY Auto-Negotiation Next Page register
654 #define KSZ8563_ANNPR_NEXT_PAGE 0x8000
655 #define KSZ8563_ANNPR_MSG_PAGE 0x2000
656 #define KSZ8563_ANNPR_ACK2 0x1000
657 #define KSZ8563_ANNPR_TOGGLE 0x0800
658 #define KSZ8563_ANNPR_MESSAGE 0x07FF
659 
660 //PHY Auto-Negotiation Link Partner Next Page Ability register
661 #define KSZ8563_ANLPNPR_NEXT_PAGE 0x8000
662 #define KSZ8563_ANLPNPR_ACK 0x4000
663 #define KSZ8563_ANLPNPR_MSG_PAGE 0x2000
664 #define KSZ8563_ANLPNPR_ACK2 0x1000
665 #define KSZ8563_ANLPNPR_TOGGLE 0x0800
666 #define KSZ8563_ANLPNPR_MESSAGE 0x07FF
667 
668 //PHY MMD Setup register
669 #define KSZ8563_MMDACR_FUNC 0xC000
670 #define KSZ8563_MMDACR_FUNC_ADDR 0x0000
671 #define KSZ8563_MMDACR_FUNC_DATA_NO_POST_INC 0x4000
672 #define KSZ8563_MMDACR_FUNC_DATA_POST_INC_RW 0x8000
673 #define KSZ8563_MMDACR_FUNC_DATA_POST_INC_W 0xC000
674 #define KSZ8563_MMDACR_DEVAD 0x001F
675 
676 //PHY Remote Loopback register
677 #define KSZ8563_RLB_REMOTE_LOOPBACK 0x0100
678 
679 //PHY LinkMD register
680 #define KSZ8563_LINKMD_TEST_EN 0x8000
681 #define KSZ8563_LINKMD_PAIR 0x1000
682 #define KSZ8563_LINKMD_PAIR_TXP_TXM 0x0000
683 #define KSZ8563_LINKMD_PAIR_RXP_RXM 0x1000
684 #define KSZ8563_LINKMD_STATUS 0x0300
685 #define KSZ8563_LINKMD_STATUS_NORMAL 0x0000
686 #define KSZ8563_LINKMD_STATUS_OPEN 0x0100
687 #define KSZ8563_LINKMD_STATUS_SHORT 0x0200
688 
689 //PHY Digital PMA/PCS Status register
690 #define KSZ8563_DPMAPCSS_1000BT_LINK_STATUS 0x0002
691 #define KSZ8563_DPMAPCSS_100BTX_LINK_STATUS 0x0001
692 
693 //Port Interrupt Control/Status register
694 #define KSZ8563_ICSR_JABBER_IE 0x8000
695 #define KSZ8563_ICSR_RECEIVE_ERROR_IE 0x4000
696 #define KSZ8563_ICSR_PAGE_RECEIVED_IE 0x2000
697 #define KSZ8563_ICSR_PAR_DETECT_FAULT_IE 0x1000
698 #define KSZ8563_ICSR_LP_ACK_IE 0x0800
699 #define KSZ8563_ICSR_LINK_DOWN_IE 0x0400
700 #define KSZ8563_ICSR_REMOTE_FAULT_IE 0x0200
701 #define KSZ8563_ICSR_LINK_UP_IE 0x0100
702 #define KSZ8563_ICSR_JABBER_IF 0x0080
703 #define KSZ8563_ICSR_RECEIVE_ERROR_IF 0x0040
704 #define KSZ8563_ICSR_PAGE_RECEIVED_IF 0x0020
705 #define KSZ8563_ICSR_PAR_DETECT_FAULT_IF 0x0010
706 #define KSZ8563_ICSR_LP_ACK_IF 0x0008
707 #define KSZ8563_ICSR_LINK_DOWN_IF 0x0004
708 #define KSZ8563_ICSR_REMOTE_FAULT_IF 0x0002
709 #define KSZ8563_ICSR_LINK_UP_IF 0x0001
710 
711 //PHY Auto MDI/MDI-X register
712 #define KSZ8563_AUTOMDI_MDI_SET 0x0080
713 #define KSZ8563_AUTOMDI_SWAP_OFF 0x0040
714 
715 //PHY Control register
716 #define KSZ8563_PHYCON_JABBER_EN 0x0200
717 #define KSZ8563_PHYCON_SPEED_100BTX 0x0020
718 #define KSZ8563_PHYCON_SPEED_10BT 0x0010
719 #define KSZ8563_PHYCON_DUPLEX_STATUS 0x0008
720 
721 //MMD LED Mode register
722 #define KSZ8563_MMD_LED_MODE_LED_MODE 0x0010
723 #define KSZ8563_MMD_LED_MODE_LED_MODE_TRI_COLOR_DUAL 0x0000
724 #define KSZ8563_MMD_LED_MODE_LED_MODE_SINGLE 0x0010
725 #define KSZ8563_MMD_LED_MODE_RESERVED 0x000F
726 #define KSZ8563_MMD_LED_MODE_RESERVED_DEFAULT 0x0001
727 
728 //MMD EEE Advertisement register
729 #define KSZ8563_MMD_EEE_ADV_1000BT_EEE_EN 0x0004
730 #define KSZ8563_MMD_EEE_ADV_100BT_EEE_EN 0x0002
731 
732 //Global Chip ID 0 register
733 #define KSZ8563_CHIP_ID0_DEFAULT 0x00
734 
735 //Global Chip ID 1 register
736 #define KSZ8563_CHIP_ID1_DEFAULT 0x98
737 
738 //Global Chip ID 2 register
739 #define KSZ8563_CHIP_ID2_DEFAULT 0x93
740 
741 //Global Chip ID 3 register
742 #define KSZ8563_CHIP_ID3_REVISION_ID 0xF0
743 #define KSZ8563_CHIP_ID3_GLOBAL_SOFT_RESET 0x01
744 
745 //PME Pin Control register
746 #define KSZ8563_PME_PIN_CTRL_PME_PIN_OUT_EN 0x02
747 #define KSZ8563_PME_PIN_CTRL_PME_PIN_OUT_POL 0x01
748 
749 //Global Chip ID 4 register
750 #define KSZ8563_CHIP_ID4_SKU_ID 0xFF
751 
752 //Global Interrupt Status register
753 #define KSZ8563_GLOBAL_INT_STAT_LUE 0x80000000
754 #define KSZ8563_GLOBAL_INT_STAT_GPIO_TRIG_TS_UNIT 0x40000000
755 
756 //Global Interrupt Mask register
757 #define KSZ8563_GLOBAL_INT_MASK_LUE 0x80000000
758 #define KSZ8563_GLOBAL_INT_MASK_GPIO_TRIG_TS_UNIT 0x40000000
759 
760 //Global Port Interrupt Status register
761 #define KSZ8563_GLOBAL_PORT_INT_STAT_PORT3 0x00000004
762 #define KSZ8563_GLOBAL_PORT_INT_STAT_PORT2 0x00000002
763 #define KSZ8563_GLOBAL_PORT_INT_STAT_PORT1 0x00000001
764 
765 //Global Port Interrupt Mask register
766 #define KSZ8563_GLOBAL_PORT_INT_MASK_PORT3 0x00000004
767 #define KSZ8563_GLOBAL_PORT_INT_MASK_PORT2 0x00000002
768 #define KSZ8563_GLOBAL_PORT_INT_MASK_PORT1 0x00000001
769 
770 //Serial I/O Control register
771 #define KSZ8563_SERIAL_IO_CTRL_MIIM_PREAMBLE_SUPPR 0x04
772 #define KSZ8563_SERIAL_IO_CTRL_AUTO_SPI_DATA_OUT_EDGE_SEL 0x02
773 #define KSZ8563_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL 0x01
774 #define KSZ8563_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL_FALLING 0x00
775 #define KSZ8563_SERIAL_IO_CTRL_SPI_DATA_OUT_EDGE_SEL_RISING 0x01
776 
777 //In-Band Management Control register
778 #define KSZ8563_IBA_CTRL_IBA_EN 0x80000000
779 #define KSZ8563_IBA_CTRL_DEST_MAC_ADDR_MATCH_EN 0x40000000
780 #define KSZ8563_IBA_CTRL_IBA_RESET 0x20000000
781 #define KSZ8563_IBA_CTRL_RESP_PRIO_QUEUE 0x00C00000
782 #define KSZ8563_IBA_CTRL_RESP_PRIO_QUEUE_DEFAULT 0x00400000
783 #define KSZ8563_IBA_CTRL_IBA_COMM 0x00070000
784 #define KSZ8563_IBA_CTRL_IBA_COMM_PORT1 0x00000000
785 #define KSZ8563_IBA_CTRL_IBA_COMM_PORT2 0x00010000
786 #define KSZ8563_IBA_CTRL_IBA_COMM_PORT3 0x00020000
787 #define KSZ8563_IBA_CTRL_TPID 0x0000FFFF
788 #define KSZ8563_IBA_CTRL_TPID_DEFAULT 0x000040FE
789 
790 //I/O Drive Strength register
791 #define KSZ8563_IO_DRIVE_STRENGTH_HIGH_SPEED_DRIVE_STRENGTH 0x70
792 #define KSZ8563_IO_DRIVE_STRENGTH_LOW_SPEED_DRIVE_STRENGTH 0x07
793 
794 //In-Band Management Operation Status 1 register
795 #define KSZ8563_IBA_OP_STAT1_GOOD_PKT_DETECT 0x80000000
796 #define KSZ8563_IBA_OP_STAT1_RESP_PKT_TX_DONE 0x40000000
797 #define KSZ8563_IBA_OP_STAT1_EXEC_DONE 0x20000000
798 #define KSZ8563_IBA_OP_STAT1_MAC_ADDR_MISMATCH_ERR 0x00004000
799 #define KSZ8563_IBA_OP_STAT1_ACCESS_FORMAT_ERR 0x00002000
800 #define KSZ8563_IBA_OP_STAT1_ACCESS_CODE_ERR 0x00001000
801 #define KSZ8563_IBA_OP_STAT1_ACCESS_CMD_ERR 0x00000800
802 #define KSZ8563_IBA_OP_STAT1_OVERSIZE_PKT_ERR 0x00000400
803 #define KSZ8563_IBA_OP_STAT1_ACCESS_CODE_ERR_LOC 0x0000007F
804 
805 //LED Override register
806 #define KSZ8563_LED_OVERRIDE_OVERRIDE 0x0000000F
807 #define KSZ8563_LED_OVERRIDE_OVERRIDE_LED1_0 0x00000001
808 #define KSZ8563_LED_OVERRIDE_OVERRIDE_LED1_1 0x00000002
809 #define KSZ8563_LED_OVERRIDE_OVERRIDE_LED2_0 0x00000004
810 #define KSZ8563_LED_OVERRIDE_OVERRIDE_LED2_1 0x00000008
811 
812 //LED Output register
813 #define KSZ8563_LED_OUTPUT_GPIO_OUT_CTRL 0x0000000F
814 #define KSZ8563_LED_OUTPUT_GPIO_OUT_CTRL_LED1_0 0x00000001
815 #define KSZ8563_LED_OUTPUT_GPIO_OUT_CTRL_LED1_1 0x00000002
816 #define KSZ8563_LED_OUTPUT_GPIO_OUT_CTRL_LED2_0 0x00000004
817 #define KSZ8563_LED_OUTPUT_GPIO_OUT_CTRL_LED2_1 0x00000008
818 
819 //LED2_0/LED2_1 Source register
820 #define KSZ8563_LED2_0_LED2_1_SRC_LED2_1_SRC 0x00000008
821 #define KSZ8563_LED2_0_LED2_1_SRC_LED2_0_SRC 0x00000004
822 
823 //Power Down Control 0 register
824 #define KSZ8563_PWR_DOWN_CTRL0_PLL_PWR_DOWN 0x20
825 #define KSZ8563_PWR_DOWN_CTRL0_PWR_MGMT_MODE 0x18
826 #define KSZ8563_PWR_DOWN_CTRL0_PWR_MGMT_MODE_NORMAL 0x00
827 #define KSZ8563_PWR_DOWN_CTRL0_PWR_MGMT_MODE_EDPD 0x08
828 #define KSZ8563_PWR_DOWN_CTRL0_PWR_MGMT_MODE_SOFT_PWR_DOWN 0x10
829 
830 //LED Strap-In register
831 #define KSZ8563_LED_STRAP_IN_STRAP_IN 0x0000000F
832 #define KSZ8563_LED_STRAP_IN_STRAP_IN_LED1_0 0x00000001
833 #define KSZ8563_LED_STRAP_IN_STRAP_IN_LED1_1 0x00000002
834 #define KSZ8563_LED_STRAP_IN_STRAP_IN_RXD2_0 0x00000004
835 #define KSZ8563_LED_STRAP_IN_STRAP_IN_RXD2_1 0x00000008
836 
837 //Switch Operation register
838 #define KSZ8563_SWITCH_OP_DOUBLE_TAG_EN 0x80
839 #define KSZ8563_SWITCH_OP_SOFT_HARD_RESET 0x02
840 #define KSZ8563_SWITCH_OP_START_SWITCH 0x01
841 
842 //Switch Maximum Transmit Unit register
843 #define KSZ8563_SWITCH_MTU_MTU 0x3FFF
844 #define KSZ8563_SWITCH_MTU_MTU_DEFAULT 0x07D0
845 
846 //Switch ISP TPID register
847 #define KSZ8563_SWITCH_ISP_TPID_ISP_TAG_TPID 0xFFFF
848 
849 //AVB Credit Based Shaper Strategy register
850 #define KSZ8563_AVB_CBS_STRATEGY_SHAPING_CREDIT_ACCOUNTING 0x0002
851 #define KSZ8563_AVB_CBS_STRATEGY_POLICING_CREDIT_ACCOUNTING 0x0001
852 
853 //Switch Lookup Engine Control 0 register
854 #define KSZ8563_SWITCH_LUE_CTRL0_VLAN_EN 0x80
855 #define KSZ8563_SWITCH_LUE_CTRL0_DROP_INVALID_VID 0x40
856 #define KSZ8563_SWITCH_LUE_CTRL0_AGE_COUNT 0x38
857 #define KSZ8563_SWITCH_LUE_CTRL0_AGE_COUNT_DEFAULT 0x20
858 #define KSZ8563_SWITCH_LUE_CTRL0_RESERVED_MCAST_LOOKUP_EN 0x04
859 #define KSZ8563_SWITCH_LUE_CTRL0_HASH_OPTION 0x03
860 #define KSZ8563_SWITCH_LUE_CTRL0_HASH_OPTION_NONE 0x00
861 #define KSZ8563_SWITCH_LUE_CTRL0_HASH_OPTION_CRC 0x01
862 #define KSZ8563_SWITCH_LUE_CTRL0_HASH_OPTION_XOR 0x02
863 
864 //Switch Lookup Engine Control 1 register
865 #define KSZ8563_SWITCH_LUE_CTRL1_UNICAST_LEARNING_DIS 0x80
866 #define KSZ8563_SWITCH_LUE_CTRL1_SELF_ADDR_FILT 0x40
867 #define KSZ8563_SWITCH_LUE_CTRL1_FLUSH_ALU_TABLE 0x20
868 #define KSZ8563_SWITCH_LUE_CTRL1_FLUSH_MSTP_ENTRIES 0x10
869 #define KSZ8563_SWITCH_LUE_CTRL1_MCAST_SRC_ADDR_FILT 0x08
870 #define KSZ8563_SWITCH_LUE_CTRL1_AGING_EN 0x04
871 #define KSZ8563_SWITCH_LUE_CTRL1_FAST_AGING 0x02
872 #define KSZ8563_SWITCH_LUE_CTRL1_LINK_DOWN_FLUSH 0x01
873 
874 //Switch Lookup Engine Control 2 register
875 #define KSZ8563_SWITCH_LUE_CTRL2_DOUBLE_TAG_MCAST_TRAP 0x40
876 #define KSZ8563_SWITCH_LUE_CTRL2_DYNAMIC_ENTRY_EG_VLAN_FILT 0x20
877 #define KSZ8563_SWITCH_LUE_CTRL2_STATIC_ENTRY_EG_VLAN_FILT 0x10
878 #define KSZ8563_SWITCH_LUE_CTRL2_FLUSH_OPTION 0x0C
879 #define KSZ8563_SWITCH_LUE_CTRL2_FLUSH_OPTION_NONE 0x00
880 #define KSZ8563_SWITCH_LUE_CTRL2_FLUSH_OPTION_DYNAMIC 0x04
881 #define KSZ8563_SWITCH_LUE_CTRL2_FLUSH_OPTION_STATIC 0x08
882 #define KSZ8563_SWITCH_LUE_CTRL2_FLUSH_OPTION_BOTH 0x0C
883 #define KSZ8563_SWITCH_LUE_CTRL2_MAC_ADDR_PRIORITY 0x03
884 
885 //Switch Lookup Engine Control 3 register
886 #define KSZ8563_SWITCH_LUE_CTRL3_AGE_PERIOD 0xFF
887 #define KSZ8563_SWITCH_LUE_CTRL3_AGE_PERIOD_DEFAULT 0x4B
888 
889 //Address Lookup Table Interrupt register
890 #define KSZ8563_ALU_TABLE_INT_LEARN_FAIL 0x04
891 #define KSZ8563_ALU_TABLE_INT_ALMOST_FULL 0x02
892 #define KSZ8563_ALU_TABLE_INT_WRITE_FAIL 0x01
893 
894 //Address Lookup Table Mask register
895 #define KSZ8563_ALU_TABLE_MASK_LEARN_FAIL 0x04
896 #define KSZ8563_ALU_TABLE_MASK_ALMOST_FULL 0x02
897 #define KSZ8563_ALU_TABLE_MASK_WRITE_FAIL 0x01
898 
899 //Address Lookup Table Entry Index 0 register
900 #define KSZ8563_ALU_TABLE_ENTRY_INDEX0_ALMOST_FULL_ENTRY_INDEX 0x0FFF
901 #define KSZ8563_ALU_TABLE_ENTRY_INDEX0_FAIL_WRITE_INDEX 0x03FF
902 
903 //Address Lookup Table Entry Index 1 register
904 #define KSZ8563_ALU_TABLE_ENTRY_INDEX1_FAIL_LEARN_INDEX 0x03FF
905 
906 //Address Lookup Table Entry Index 2 register
907 #define KSZ8563_ALU_TABLE_ENTRY_INDEX2_CPU_ACCESS_INDEX 0x03FF
908 
909 //Unknown Unicast Control register
910 #define KSZ8563_UNKNOWN_UNICAST_CTRL_FWD 0x80000000
911 #define KSZ8563_UNKNOWN_UNICAST_CTRL_FWD_MAP 0x00000007
912 #define KSZ8563_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT1 0x00000001
913 #define KSZ8563_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT2 0x00000002
914 #define KSZ8563_UNKNOWN_UNICAST_CTRL_FWD_MAP_PORT3 0x00000004
915 #define KSZ8563_UNKNOWN_UNICAST_CTRL_FWD_MAP_ALL 0x00000007
916 
917 //Unknown Multicast Control register
918 #define KSZ8563_UNKONWN_MULTICAST_CTRL_FWD 0x80000000
919 #define KSZ8563_UNKONWN_MULTICAST_CTRL_FWD_MAP 0x00000007
920 #define KSZ8563_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT1 0x00000001
921 #define KSZ8563_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT2 0x00000002
922 #define KSZ8563_UNKONWN_MULTICAST_CTRL_FWD_MAP_PORT3 0x00000004
923 #define KSZ8563_UNKONWN_MULTICAST_CTRL_FWD_MAP_ALL 0x00000007
924 
925 //Unknown VLAN ID Control register
926 #define KSZ8563_UNKNOWN_VLAN_ID_CTRL_FWD 0x80000000
927 #define KSZ8563_UNKNOWN_VLAN_ID_CTRL_FWD_MAP 0x00000007
928 #define KSZ8563_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT1 0x00000001
929 #define KSZ8563_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT2 0x00000002
930 #define KSZ8563_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_PORT3 0x00000004
931 #define KSZ8563_UNKNOWN_VLAN_ID_CTRL_FWD_MAP_ALL 0x00000007
932 
933 //Switch MAC Control 0 register
934 #define KSZ8563_SWITCH_MAC_CTRL0_ALT_BACK_OFF_MODE 0x80
935 #define KSZ8563_SWITCH_MAC_CTRL0_FRAME_LEN_CHECK_EN 0x08
936 #define KSZ8563_SWITCH_MAC_CTRL0_FLOW_CTRL_PKT_DROP_MODE 0x02
937 #define KSZ8563_SWITCH_MAC_CTRL0_AGGRESSIVE_BACK_OFF_EN 0x01
938 
939 //Switch MAC Control 1 register
940 #define KSZ8563_SWITCH_MAC_CTRL1_MCAST_STORM_PROTECT_DIS 0x40
941 #define KSZ8563_SWITCH_MAC_CTRL1_BACK_PRESSURE_MODE 0x20
942 #define KSZ8563_SWITCH_MAC_CTRL1_FLOW_CTRL_FAIR_MODE 0x10
943 #define KSZ8563_SWITCH_MAC_CTRL1_NO_EXCESSIVE_COL_DROP 0x08
944 #define KSZ8563_SWITCH_MAC_CTRL1_JUMBO_PKT_SUPPORT 0x04
945 #define KSZ8563_SWITCH_MAC_CTRL1_MAX_PKT_SIZE_CHECK_DIS 0x02
946 #define KSZ8563_SWITCH_MAC_CTRL1_PASS_SHORT_PKT 0x01
947 
948 //Switch MAC Control 2 register
949 #define KSZ8563_SWITCH_MAC_CTRL2_NULL_VID_REPLACEMENT 0x08
950 #define KSZ8563_SWITCH_MAC_CTRL2_BCAST_STORM_PROTECT_RATE_MSB 0x07
951 
952 //Switch MAC Control 3 register
953 #define KSZ8563_SWITCH_MAC_CTRL3_BCAST_STORM_PROTECT_RATE_LSB 0xFF
954 
955 //Switch MAC Control 4 register
956 #define KSZ8563_SWITCH_MAC_CTRL4_PASS_FLOW_CTRL_PKT 0x01
957 
958 //Switch MAC Control 5 register
959 #define KSZ8563_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD 0x30
960 #define KSZ8563_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_16MS 0x00
961 #define KSZ8563_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_64MS 0x10
962 #define KSZ8563_SWITCH_MAC_CTRL5_IG_RATE_LIMIT_PERIOD_256MS 0x20
963 #define KSZ8563_SWITCH_MAC_CTRL5_QUEUE_BASED_EG_RATE_LIMITE_EN 0x08
964 
965 //Switch MIB Control register
966 #define KSZ8563_SWITCH_MIB_CTRL_FLUSH 0x80
967 #define KSZ8563_SWITCH_MIB_CTRL_FREEZE 0x40
968 
969 //Global Port Mirroring and Snooping Control register
970 #define KSZ8563_GLOBAL_PORT_MIRROR_SNOOP_CTRL_IGMP_SNOOP_EN 0x40
971 #define KSZ8563_GLOBAL_PORT_MIRROR_SNOOP_CTRL_MLD_SNOOP_OPT 0x08
972 #define KSZ8563_GLOBAL_PORT_MIRROR_SNOOP_CTRL_MLD_SNOOP_EN 0x04
973 #define KSZ8563_GLOBAL_PORT_MIRROR_SNOOP_CTRL_SNIFF_MODE_SEL 0x01
974 
975 //WRED DiffServ Color Mapping register
976 #define KSZ8563_WRED_DIFFSERV_COLOR_MAPPING_RED 0x30
977 #define KSZ8563_WRED_DIFFSERV_COLOR_MAPPING_YELLOW 0x0C
978 #define KSZ8563_WRED_DIFFSERV_COLOR_MAPPING_GREEN 0x03
979 
980 //PTP Event Message Priority register
981 #define KSZ8563_PTP_EVENT_MSG_PRIO_OVERRIDE 0x80
982 #define KSZ8563_PTP_EVENT_MSG_PRIO_PRIORITY 0x0F
983 
984 //PTP Non-Event Message Priority register
985 #define KSZ8563_PTP_NON_EVENT_MSG_PRIO_OVERRIDE 0x80
986 #define KSZ8563_PTP_NON_EVENT_MSG_PRIO_PRIORITY 0x0F
987 
988 //Queue Management Control 0 register
989 #define KSZ8563_QUEUE_MGMT_CTRL0_PRIORITY_2Q 0x000000C0
990 #define KSZ8563_QUEUE_MGMT_CTRL0_UNICAST_PORT_VLAN_DISCARD 0x00000002
991 
992 //VLAN Table Entry 0 register
993 #define KSZ8563_VLAN_TABLE_ENTRY0_VALID 0x80000000
994 #define KSZ8563_VLAN_TABLE_ENTRY0_FORWARD_OPTION 0x08000000
995 #define KSZ8563_VLAN_TABLE_ENTRY0_PRIORITY 0x07000000
996 #define KSZ8563_VLAN_TABLE_ENTRY0_MSTP_INDEX 0x00007000
997 #define KSZ8563_VLAN_TABLE_ENTRY0_FID 0x0000007F
998 
999 //VLAN Table Entry 1 register
1000 #define KSZ8563_VLAN_TABLE_ENTRY1_PORT_UNTAG 0x00000007
1001 #define KSZ8563_VLAN_TABLE_ENTRY1_PORT3_UNTAG 0x00000004
1002 #define KSZ8563_VLAN_TABLE_ENTRY1_PORT2_UNTAG 0x00000002
1003 #define KSZ8563_VLAN_TABLE_ENTRY1_PORT1_UNTAG 0x00000001
1004 
1005 //VLAN Table Entry 2 register
1006 #define KSZ8563_VLAN_TABLE_ENTRY2_PORT_FORWARD 0x00000007
1007 #define KSZ8563_VLAN_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1008 #define KSZ8563_VLAN_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1009 #define KSZ8563_VLAN_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1010 
1011 //VLAN Table Index register
1012 #define KSZ8563_VLAN_TABLE_INDEX_VLAN_INDEX 0x0FFF
1013 
1014 //VLAN Table Access Control register
1015 #define KSZ8563_VLAN_TABLE_ACCESS_CTRL_START_FINISH 0x80
1016 #define KSZ8563_VLAN_TABLE_ACCESS_CTRL_ACTION 0x03
1017 #define KSZ8563_VLAN_TABLE_ACCESS_CTRL_ACTION_NOP 0x00
1018 #define KSZ8563_VLAN_TABLE_ACCESS_CTRL_ACTION_WRITE 0x01
1019 #define KSZ8563_VLAN_TABLE_ACCESS_CTRL_ACTION_READ 0x02
1020 #define KSZ8563_VLAN_TABLE_ACCESS_CTRL_ACTION_CLEAR 0x03
1021 
1022 //ALU Table Index 0 register
1023 #define KSZ8563_ALU_TABLE_INDEX0_FID_INDEX 0x007F0000
1024 #define KSZ8563_ALU_TABLE_INDEX0_MAC_INDEX_MSB 0x0000FFFF
1025 
1026 //ALU Table Index 1 register
1027 #define KSZ8563_ALU_TABLE_INDEX1_MAC_INDEX_LSB 0xFFFFFFFF
1028 
1029 //ALU Table Access Control register
1030 #define KSZ8563_ALU_TABLE_CTRL_VALID_COUNT 0x3FFF0000
1031 #define KSZ8563_ALU_TABLE_CTRL_START_FINISH 0x00000080
1032 #define KSZ8563_ALU_TABLE_CTRL_VALID 0x00000040
1033 #define KSZ8563_ALU_TABLE_CTRL_VALID_ENTRY_OR_SEARCH_END 0x00000020
1034 #define KSZ8563_ALU_TABLE_CTRL_DIRECT 0x00000004
1035 #define KSZ8563_ALU_TABLE_CTRL_ACTION 0x00000003
1036 #define KSZ8563_ALU_TABLE_CTRL_ACTION_NOP 0x00000000
1037 #define KSZ8563_ALU_TABLE_CTRL_ACTION_WRITE 0x00000001
1038 #define KSZ8563_ALU_TABLE_CTRL_ACTION_READ 0x00000002
1039 #define KSZ8563_ALU_TABLE_CTRL_ACTION_SEARCH 0x00000003
1040 
1041 //Static Address and Reserved Multicast Table Control register
1042 #define KSZ8563_STATIC_MCAST_TABLE_CTRL_TABLE_INDEX 0x003F0000
1043 #define KSZ8563_STATIC_MCAST_TABLE_CTRL_START_FINISH 0x00000080
1044 #define KSZ8563_STATIC_MCAST_TABLE_CTRL_TABLE_SELECT 0x00000002
1045 #define KSZ8563_STATIC_MCAST_TABLE_CTRL_ACTION 0x00000001
1046 #define KSZ8563_STATIC_MCAST_TABLE_CTRL_ACTION_READ 0x00000000
1047 #define KSZ8563_STATIC_MCAST_TABLE_CTRL_ACTION_WRITE 0x00000001
1048 
1049 //ALU Table Entry 1 register
1050 #define KSZ8563_ALU_TABLE_ENTRY1_STATIC 0x80000000
1051 #define KSZ8563_ALU_TABLE_ENTRY1_SRC_FILTER 0x40000000
1052 #define KSZ8563_ALU_TABLE_ENTRY1_DES_FILTER 0x20000000
1053 #define KSZ8563_ALU_TABLE_ENTRY1_PRIORITY 0x1C000000
1054 #define KSZ8563_ALU_TABLE_ENTRY1_AGE_COUNT 0x1C000000
1055 #define KSZ8563_ALU_TABLE_ENTRY1_MSTP 0x00000007
1056 
1057 //ALU Table Entry 2 register
1058 #define KSZ8563_ALU_TABLE_ENTRY2_OVERRIDE 0x80000000
1059 #define KSZ8563_ALU_TABLE_ENTRY2_PORT_FORWARD 0x00000007
1060 #define KSZ8563_ALU_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1061 #define KSZ8563_ALU_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1062 #define KSZ8563_ALU_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1063 
1064 //ALU Table Entry 3 register
1065 #define KSZ8563_ALU_TABLE_ENTRY3_FID 0x007F0000
1066 #define KSZ8563_ALU_TABLE_ENTRY3_MAC_ADDR_MSB 0x0000FFFF
1067 
1068 //ALU Table Entry 4 register
1069 #define KSZ8563_ALU_TABLE_ENTRY4_MAC_ADDR_LSB 0xFFFFFFFF
1070 
1071 //Static Address Table Entry 1 register
1072 #define KSZ8563_STATIC_TABLE_ENTRY1_VALID 0x80000000
1073 #define KSZ8563_STATIC_TABLE_ENTRY1_SRC_FILTER 0x40000000
1074 #define KSZ8563_STATIC_TABLE_ENTRY1_DES_FILTER 0x20000000
1075 #define KSZ8563_STATIC_TABLE_ENTRY1_PRIORITY 0x1C000000
1076 #define KSZ8563_STATIC_TABLE_ENTRY1_MSTP 0x00000007
1077 
1078 //Static Address Table Entry 2 register
1079 #define KSZ8563_STATIC_TABLE_ENTRY2_OVERRIDE 0x80000000
1080 #define KSZ8563_STATIC_TABLE_ENTRY2_USE_FID 0x40000000
1081 #define KSZ8563_STATIC_TABLE_ENTRY2_PORT_FORWARD 0x00000007
1082 #define KSZ8563_STATIC_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1083 #define KSZ8563_STATIC_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1084 #define KSZ8563_STATIC_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1085 
1086 //Static Address Table Entry 3 register
1087 #define KSZ8563_STATIC_TABLE_ENTRY3_FID 0x007F0000
1088 #define KSZ8563_STATIC_TABLE_ENTRY3_MAC_ADDR_MSB 0x0000FFFF
1089 
1090 //Static Address Table Entry 4 register
1091 #define KSZ8563_STATIC_TABLE_ENTRY4_MAC_ADDR_LSB 0xFFFFFFFF
1092 
1093 //Reserved Multicast Table Entry 2 register
1094 #define KSZ8563_RES_MCAST_TABLE_ENTRY2_PORT_FORWARD 0x00000007
1095 #define KSZ8563_RES_MCAST_TABLE_ENTRY2_PORT3_FORWARD 0x00000004
1096 #define KSZ8563_RES_MCAST_TABLE_ENTRY2_PORT2_FORWARD 0x00000002
1097 #define KSZ8563_RES_MCAST_TABLE_ENTRY2_PORT1_FORWARD 0x00000001
1098 
1099 //Global PTP Clock Control register
1100 #define KSZ8563_GLOBAL_PTP_CLK_CTRL_SW_FREQ_ADJ_DIS 0x8000
1101 #define KSZ8563_GLOBAL_PTP_CLK_CTRL_PTP_CLK_STEP_ADJ 0x0040
1102 #define KSZ8563_GLOBAL_PTP_CLK_CTRL_PTP_STEP_DIR 0x0020
1103 #define KSZ8563_GLOBAL_PTP_CLK_CTRL_PTP_CLK_READ 0x0010
1104 #define KSZ8563_GLOBAL_PTP_CLK_CTRL_PTP_CLK_LOAD 0x0008
1105 #define KSZ8563_GLOBAL_PTP_CLK_CTRL_PTP_CLK_CONTINUOUS_ADJ 0x0004
1106 #define KSZ8563_GLOBAL_PTP_CLK_CTRL_PTP_CLK_EN 0x0002
1107 #define KSZ8563_GLOBAL_PTP_CLK_CTRL_PTP_CLK_RESET 0x0001
1108 
1109 //Global PTP RTC Clock Phase register
1110 #define KSZ8563_GLOBAL_PTP_RTC_CLK_PHASE_PTP_RTC_8NS_PHASE 0x0007
1111 
1112 //Global PTP Clock Sub-Nanosecond Rate High Word register
1113 #define KSZ8563_GLOBAL_PTP_CLK_SUB_NS_RATE_H_PTP_RATE_DIR 0x8000
1114 #define KSZ8563_GLOBAL_PTP_CLK_SUB_NS_RATE_H_PTP_TEMP_ADJ_MODE 0x4000
1115 #define KSZ8563_GLOBAL_PTP_CLK_SUB_NS_RATE_H_PTP_RTC_SUB_NS_29_16 0x3FFF
1116 
1117 //Global PTP Clock Sub-Nanosecond Rate Low Word register
1118 #define KSZ8563_GLOBAL_PTP_CLK_SUB_NS_RATE_L_PTP_RTC_SUB_NS_15_0 0xFFFF
1119 
1120 //Global PTP Message Config 1 register
1121 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG1_IEEE_1588_PTP_MODE 0x0040
1122 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG1_ETH_PTP_DETECT 0x0020
1123 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG1_IPV4_UDP_PTP_DETECT 0x0010
1124 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG1_IPV6_UDP_PTP_DETECT 0x0008
1125 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG1_E2E_CLK_MODE 0x0000
1126 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG1_P2P_CLK_MODE 0x0004
1127 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG1_SLAVE_OC_CLK_MODE 0x0000
1128 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG1_MASTER_OC_CLK_MODE 0x0002
1129 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG1_TWO_STEP_CLK_MODE 0x0000
1130 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG1_ONE_STEP_CLK_MODE 0x0001
1131 
1132 //Global PTP Message Config 2 register
1133 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG2_UNICAST_PTP_EN 0x1000
1134 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG2_ALT_MASTER_EN 0x0800
1135 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG2_PTP_MSG_PRIO_TX_QUEUE 0x0400
1136 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG2_CHECK_SYNC_FOLLOW_UP 0x0200
1137 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG2_CHECK_DELAY_REQ_RESP 0x0100
1138 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG2_CHECK_PDELAY_REQ_RESP 0x0080
1139 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG2_DROP_SYNC_FOLLOW_UP_DELAY_REQ 0x0020
1140 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG2_CHECK_DOMAIN 0x0010
1141 #define KSZ8563_GLOBAL_PTP_MSG_CONFIG2_IPV4_UDP_CHECKSUM_EN 0x0004
1142 
1143 //Global PTP Domain and Version register
1144 #define KSZ8563_GLOBAL_PTP_DOMAIN_VERSION_PTP_VERSION 0x0F00
1145 #define KSZ8563_GLOBAL_PTP_DOMAIN_VERSION_PTP_DOMAIN 0x00FF
1146 
1147 //Global PTP Unit Index register
1148 #define KSZ8563_GLOBAL_PTP_UNIT_INDEX_GPIO_PTR_INDEX 0x00010000
1149 #define KSZ8563_GLOBAL_PTP_UNIT_INDEX_GPIO_PTR_INDEX_GPIO1 0x00000000
1150 #define KSZ8563_GLOBAL_PTP_UNIT_INDEX_GPIO_PTR_INDEX_GPIO2 0x00010000
1151 #define KSZ8563_GLOBAL_PTP_UNIT_INDEX_TS_PTR_INDEX 0x00000100
1152 #define KSZ8563_GLOBAL_PTP_UNIT_INDEX_TS_PTR_INDEX_UNIT0 0x00000000
1153 #define KSZ8563_GLOBAL_PTP_UNIT_INDEX_TS_PTR_INDEX_UNIT1 0x00000100
1154 #define KSZ8563_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX 0x00000003
1155 #define KSZ8563_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX_UNIT0 0x00000000
1156 #define KSZ8563_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX_UNIT1 0x00000001
1157 #define KSZ8563_GLOBAL_PTP_UNIT_INDEX_TRIGGER_PTR_INDEX_UNIT2 0x00000002
1158 
1159 //GPIO Status Monitor 0 register
1160 #define KSZ8563_GPIO_STATUS_MONITOR0_TRIGGER_ERROR 0x00070000
1161 #define KSZ8563_GPIO_STATUS_MONITOR0_TRIGGER_DONE 0x00000007
1162 
1163 //GPIO Status Monitor 1 register
1164 #define KSZ8563_GPIO_STATUS_MONITOR1_TRIGGER_INT_STATUS 0x00070000
1165 #define KSZ8563_GPIO_STATUS_MONITOR1_TS_INT_STATUS 0x00000003
1166 
1167 //Timestamp Control and Status register
1168 #define KSZ8563_TS_CTRL_STAT_GPIO_OUT_SEL 0x00000100
1169 #define KSZ8563_TS_CTRL_STAT_GPIO_IN 0x00000080
1170 #define KSZ8563_TS_CTRL_STAT_GPIO_OEN 0x00000040
1171 #define KSZ8563_TS_CTRL_STAT_TS_INT_ENB 0x00000020
1172 #define KSZ8563_TS_CTRL_STAT_TRIGGER_ACTIVE 0x00000010
1173 #define KSZ8563_TS_CTRL_STAT_TRIGGER_EN 0x00000008
1174 #define KSZ8563_TS_CTRL_STAT_TRIGGER_SW_RESET 0x00000004
1175 #define KSZ8563_TS_CTRL_STAT_TS_ENB 0x00000002
1176 #define KSZ8563_TS_CTRL_STAT_TS_SW_RESET 0x00000001
1177 
1178 //Trigger Output Unit Target Time Nanosecond register
1179 #define KSZ8563_TOU_TARGET_TIME_NS_TRIGGER_TARGET_TIME_NS 0x3FFFFFFF
1180 
1181 //Trigger Output Unit Target Time Second register
1182 #define KSZ8563_TOU_TARGET_TIME_S_TRIGGER_TARGET_TIME_S 0xFFFFFFFF
1183 
1184 //Trigger Output Unit Control 1 register
1185 #define KSZ8563_TOU_CTRL1_CASCADE_MODE_ENB 0x80000000
1186 #define KSZ8563_TOU_CTRL1_CASCADE_MODE_TAIL 0x40000000
1187 #define KSZ8563_TOU_CTRL1_CASCADE_MODE_DONE 0x0C000000
1188 #define KSZ8563_TOU_CTRL1_TRIGGER_NOW 0x02000000
1189 #define KSZ8563_TOU_CTRL1_TRIGGER_NOTIFY 0x01000000
1190 #define KSZ8563_TOU_CTRL1_TRIGGER_EDGE 0x00800000
1191 #define KSZ8563_TOU_CTRL1_TRIGGER_PATTERN 0x00700000
1192 #define KSZ8563_TOU_CTRL1_TRIGGER_PATTERN_NEG_EDGE 0x00000000
1193 #define KSZ8563_TOU_CTRL1_TRIGGER_PATTERN_POS_EDGE 0x00100000
1194 #define KSZ8563_TOU_CTRL1_TRIGGER_PATTERN_NEG_PULSE 0x00200000
1195 #define KSZ8563_TOU_CTRL1_TRIGGER_PATTERN_POS_PULSE 0x00300000
1196 #define KSZ8563_TOU_CTRL1_TRIGGER_PATTERN_NEG_CYCLE 0x00400000
1197 #define KSZ8563_TOU_CTRL1_TRIGGER_PATTERN_POS_CYCLE 0x00500000
1198 #define KSZ8563_TOU_CTRL1_TRIGGER_PATTERN_REG_OUTPUT 0x00600000
1199 #define KSZ8563_TOU_CTRL1_TRIGGER_GPIO 0x00010000
1200 #define KSZ8563_TOU_CTRL1_TRIGGER_GPIO_1 0x00000000
1201 #define KSZ8563_TOU_CTRL1_TRIGGER_GPIO_2 0x00010000
1202 #define KSZ8563_TOU_CTRL1_TRIGGER_PATTERN_ITERATION 0x0000FFFF
1203 
1204 //Trigger Output Unit Control 2 register
1205 #define KSZ8563_TOU_CTRL2_TRIGGER_CYCLE_WIDTH 0xFFFFFFFF
1206 
1207 //Trigger Output Unit Control 3 register
1208 #define KSZ8563_TOU_CTRL3_TRIGGER_CYCLE 0xFFFF0000
1209 #define KSZ8563_TOU_CTRL3_TRIGGER_BIT_PATTERN 0x0000FFFF
1210 
1211 //Trigger Output Unit Control 4 register
1212 #define KSZ8563_TOU_CTRL4_CASCADE_INTERATION_CYCLE_TIME 0xFFFFFFFF
1213 
1214 //Trigger Output Unit Control 5 register
1215 #define KSZ8563_TOU_CTRL5_PPS_PULSE_WIDTH 0x00FF0000
1216 #define KSZ8563_TOU_CTRL5_TRIGGER_PULSE_WIDTH 0x0000FFFF
1217 
1218 //Timestamp Status and Control register
1219 #define KSZ8563_TS_STAT_CTRL_TS_EVENT_DET_CNT 0x001E0000
1220 #define KSZ8563_TS_STAT_CTRL_TS_DET_EVENT_CNT_OVERFLOW 0x00010000
1221 #define KSZ8563_TS_STAT_CTRL_TS_RISING_EDGE_ENB 0x00000080
1222 #define KSZ8563_TS_STAT_CTRL_TS_FALLING_EDGE_ENB 0x00000040
1223 #define KSZ8563_TS_STAT_CTRL_TS_CASCADE_MODE_TAIL 0x00000020
1224 #define KSZ8563_TS_STAT_CTRL_TS_UPSTREAM_CASCADE_MODE_SEL 0x00000002
1225 #define KSZ8563_TS_STAT_CTRL_TS_CASCADE_MODE_ENB 0x00000001
1226 
1227 //Timestamp 1st Sample Time Nanoseconds register
1228 #define KSZ8563_TS_SAMPLE1_TIME_NS_TS_SAMPLE_EDGE_1ST 0x40000000
1229 #define KSZ8563_TS_SAMPLE1_TIME_NS_TS_SAMPLE_TIME_NS_1ST 0x3FFFFFFF
1230 
1231 //Timestamp 1st Sample Time Seconds register
1232 #define KSZ8563_TS_SAMPLE1_TIME_S_TS_SAMPLE_TIME_S_1ST 0xFFFFFFFF
1233 
1234 //Timestamp 1st Sample Time Phase register
1235 #define KSZ8563_TS_SAMPLE1_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_1ST 0x00000007
1236 
1237 //Timestamp 2nd Sample Time Nanoseconds register
1238 #define KSZ8563_TS_SAMPLE2_TIME_NS_TS_SAMPLE_EDGE_2ND 0x40000000
1239 #define KSZ8563_TS_SAMPLE2_TIME_NS_TS_SAMPLE_TIME_NS_2ND 0x3FFFFFFF
1240 
1241 //Timestamp 2nd Sample Time Seconds register
1242 #define KSZ8563_TS_SAMPLE2_TIME_S_TS_SAMPLE_TIME_S_2ND 0xFFFFFFFF
1243 
1244 //Timestamp 2nd Sample Time Phase register
1245 #define KSZ8563_TS_SAMPLE2_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_2ND 0x00000007
1246 
1247 //Timestamp 3rd Sample Time Nanoseconds register
1248 #define KSZ8563_TS_SAMPLE3_TIME_NS_TS_SAMPLE_EDGE_3RD 0x40000000
1249 #define KSZ8563_TS_SAMPLE3_TIME_NS_TS_SAMPLE_TIME_NS_3RD 0x3FFFFFFF
1250 
1251 //Timestamp 3rd Sample Time Seconds register
1252 #define KSZ8563_TS_SAMPLE3_TIME_S_TS_SAMPLE_TIME_S_3RD 0xFFFFFFFF
1253 
1254 //Timestamp 3rd Sample Time Phase register
1255 #define KSZ8563_TS_SAMPLE3_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_3RD 0x00000007
1256 
1257 //Timestamp 4th Sample Time Nanoseconds register
1258 #define KSZ8563_TS_SAMPLE4_TIME_NS_TS_SAMPLE_EDGE_4TH 0x40000000
1259 #define KSZ8563_TS_SAMPLE4_TIME_NS_TS_SAMPLE_TIME_NS_4TH 0x3FFFFFFF
1260 
1261 //Timestamp 4th Sample Time Seconds register
1262 #define KSZ8563_TS_SAMPLE4_TIME_S_TS_SAMPLE_TIME_S_4TH 0xFFFFFFFF
1263 
1264 //Timestamp 4th Sample Time Phase register
1265 #define KSZ8563_TS_SAMPLE4_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_4TH 0x00000007
1266 
1267 //Timestamp 5th Sample Time Nanoseconds register
1268 #define KSZ8563_TS_SAMPLE5_TIME_NS_TS_SAMPLE_EDGE_5TH 0x40000000
1269 #define KSZ8563_TS_SAMPLE5_TIME_NS_TS_SAMPLE_TIME_NS_5TH 0x3FFFFFFF
1270 
1271 //Timestamp 5th Sample Time Seconds register
1272 #define KSZ8563_TS_SAMPLE5_TIME_S_TS_SAMPLE_TIME_S_5TH 0xFFFFFFFF
1273 
1274 //Timestamp 5th Sample Time Phase register
1275 #define KSZ8563_TS_SAMPLE5_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_5TH 0x00000007
1276 
1277 //Timestamp 6th Sample Time Nanoseconds register
1278 #define KSZ8563_TS_SAMPLE6_TIME_NS_TS_SAMPLE_EDGE_6TH 0x40000000
1279 #define KSZ8563_TS_SAMPLE6_TIME_NS_TS_SAMPLE_TIME_NS_6TH 0x3FFFFFFF
1280 
1281 //Timestamp 6th Sample Time Seconds register
1282 #define KSZ8563_TS_SAMPLE6_TIME_S_TS_SAMPLE_TIME_S_6TH 0xFFFFFFFF
1283 
1284 //Timestamp 6th Sample Time Phase register
1285 #define KSZ8563_TS_SAMPLE6_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_6TH 0x00000007
1286 
1287 //Timestamp 7th Sample Time Nanoseconds register
1288 #define KSZ8563_TS_SAMPLE7_TIME_NS_TS_SAMPLE_EDGE_7TH 0x40000000
1289 #define KSZ8563_TS_SAMPLE7_TIME_NS_TS_SAMPLE_TIME_NS_7TH 0x3FFFFFFF
1290 
1291 //Timestamp 7th Sample Time Seconds register
1292 #define KSZ8563_TS_SAMPLE7_TIME_S_TS_SAMPLE_TIME_S_7TH 0xFFFFFFFF
1293 
1294 //Timestamp 7th Sample Time Phase register
1295 #define KSZ8563_TS_SAMPLE7_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_7TH 0x00000007
1296 
1297 //Timestamp 8th Sample Time Nanoseconds register
1298 #define KSZ8563_TS_SAMPLE8_TIME_NS_TS_SAMPLE_EDGE_8TH 0x40000000
1299 #define KSZ8563_TS_SAMPLE8_TIME_NS_TS_SAMPLE_TIME_NS_8TH 0x3FFFFFFF
1300 
1301 //Timestamp 8th Sample Time Seconds register
1302 #define KSZ8563_TS_SAMPLE8_TIME_S_TS_SAMPLE_TIME_S_8TH 0xFFFFFFFF
1303 
1304 //Timestamp 8th Sample Time Phase register
1305 #define KSZ8563_TS_SAMPLE8_TIME_PHASE_TS_SAMPLE_TIME_SUB_8NS_8TH 0x00000007
1306 
1307 //Port N Default Tag 0 register
1308 #define KSZ8563_PORTn_DEFAULT_TAG0_PCP 0xE0
1309 #define KSZ8563_PORTn_DEFAULT_TAG0_DEI 0x10
1310 #define KSZ8563_PORTn_DEFAULT_TAG0_VID_MSB 0x0F
1311 
1312 //Port N Default Tag 1 register
1313 #define KSZ8563_PORTn_DEFAULT_TAG1_VID_LSB 0xFF
1314 
1315 //Port N Interrupt Status register
1316 #define KSZ8563_PORTn_INT_STATUS_PTP 0x04
1317 #define KSZ8563_PORTn_INT_STATUS_PHY 0x02
1318 #define KSZ8563_PORTn_INT_STATUS_ACL 0x01
1319 
1320 //Port N Interrupt Mask register
1321 #define KSZ8563_PORTn_INT_MASK_PTP 0x04
1322 #define KSZ8563_PORTn_INT_MASK_PHY 0x02
1323 #define KSZ8563_PORTn_INT_MASK_ACL 0x01
1324 
1325 //Port N Operation Control 0 register
1326 #define KSZ8563_PORTn_OP_CTRL0_LOCAL_LOOPBACK 0x80
1327 #define KSZ8563_PORTn_OP_CTRL0_REMOTE_LOOPBACK 0x40
1328 #define KSZ8563_PORTn_OP_CTRL0_TAIL_TAG_EN 0x04
1329 #define KSZ8563_PORTn_OP_CTRL0_TX_QUEUE_SPLIT_EN 0x03
1330 
1331 //Port N Status register
1332 #define KSZ8563_PORTn_STATUS_SPEED 0x18
1333 #define KSZ8563_PORTn_STATUS_SPEED_10MBPS 0x00
1334 #define KSZ8563_PORTn_STATUS_SPEED_100MBPS 0x08
1335 #define KSZ8563_PORTn_STATUS_DUPLEX 0x04
1336 #define KSZ8563_PORTn_STATUS_TX_FLOW_CTRL_EN 0x02
1337 #define KSZ8563_PORTn_STATUS_RX_FLOW_CTRL_EN 0x01
1338 
1339 //XMII Port N Control 0 register
1340 #define KSZ8563_PORTn_XMII_CTRL0_DUPLEX 0x40
1341 #define KSZ8563_PORTn_XMII_CTRL0_TX_FLOW_CTRL_EN 0x20
1342 #define KSZ8563_PORTn_XMII_CTRL0_SPEED_10_100 0x10
1343 #define KSZ8563_PORTn_XMII_CTRL0_RX_FLOW_CTRL_EN 0x08
1344 
1345 //XMII Port N Control 1 register
1346 #define KSZ8563_PORTn_XMII_CTRL1_SPEED_1000 0x40
1347 #define KSZ8563_PORTn_XMII_CTRL1_RGMII_ID_IG 0x10
1348 #define KSZ8563_PORTn_XMII_CTRL1_RGMII_ID_EG 0x08
1349 #define KSZ8563_PORTn_XMII_CTRL1_MII_RMII_MODE 0x04
1350 #define KSZ8563_PORTn_XMII_CTRL1_IF_TYPE 0x03
1351 #define KSZ8563_PORTn_XMII_CTRL1_IF_TYPE_MII 0x00
1352 #define KSZ8563_PORTn_XMII_CTRL1_IF_TYPE_RMII 0x01
1353 #define KSZ8563_PORTn_XMII_CTRL1_IF_TYPE_RGMII 0x03
1354 
1355 //XMII Port N Control 3 register
1356 #define KSZ8563_PORTn_XMII_CTRL3_RGMII_IBS_DUPLEX_STATUS 0x08
1357 #define KSZ8563_PORTn_XMII_CTRL3_RGMII_IBS_RX_CLK_SPEED 0x06
1358 #define KSZ8563_PORTn_XMII_CTRL3_RGMII_IBS_LINK_STATUS 0x01
1359 
1360 //Port N MAC Control 0 register
1361 #define KSZ8563_PORTn_MAC_CTRL0_BCAST_STORM_PROTECT_EN 0x02
1362 
1363 //Port N MAC Control 1 register
1364 #define KSZ8563_PORTn_MAC_CTRL1_BACK_PRESSURE_EN 0x08
1365 #define KSZ8563_PORTn_MAC_CTRL1_PASS_ALL_FRAMES 0x01
1366 
1367 //Port N MIB Control and Status register
1368 #define KSZ8563_PORTn_MIB_CTRL_STAT_MIB_COUNTER_OVERFLOW 0x80000000
1369 #define KSZ8563_PORTn_MIB_CTRL_STAT_MIB_READ 0x02000000
1370 #define KSZ8563_PORTn_MIB_CTRL_STAT_MIB_FLUSH_FREEZE 0x01000000
1371 #define KSZ8563_PORTn_MIB_CTRL_STAT_MIB_INDEX 0x00FF0000
1372 #define KSZ8563_PORTn_MIB_CTRL_STAT_MIB_COUNTER_VALUE_35_32 0x0000000F
1373 
1374 //Port N MIB Data register
1375 #define KSZ8563_PORTn_MIB_DATA_MIB_COUNTER_VALUE_31_0 0xFFFFFFFF
1376 
1377 //Port N ACL Access Control 0 register
1378 #define KSZ8563_PORTn_ACL_ACCESS_CTRL0_WRITE_STATUS 0x40
1379 #define KSZ8563_PORTn_ACL_ACCESS_CTRL0_READ_STATUS 0x20
1380 #define KSZ8563_PORTn_ACL_ACCESS_CTRL0_READ 0x00
1381 #define KSZ8563_PORTn_ACL_ACCESS_CTRL0_WRITE 0x10
1382 #define KSZ8563_PORTn_ACL_ACCESS_CTRL0_ACL_INDEX 0x0F
1383 
1384 //Port N Port Mirroring Control register
1385 #define KSZ8563_PORTn_MIRRORING_CTRL_RECEIVE_SNIFF 0x40
1386 #define KSZ8563_PORTn_MIRRORING_CTRL_TRANSMIT_SNIFF 0x20
1387 #define KSZ8563_PORTn_MIRRORING_CTRL_SNIFFER_PORT 0x02
1388 
1389 //Port N Authentication Control register
1390 #define KSZ8563_PORTn_AUTH_CTRL_ACL_EN 0x04
1391 #define KSZ8563_PORTn_AUTH_CTRL_AUTH_MODE 0x03
1392 #define KSZ8563_PORTn_AUTH_CTRL_AUTH_MODE_PASS 0x00
1393 #define KSZ8563_PORTn_AUTH_CTRL_AUTH_MODE_BLOCK 0x01
1394 #define KSZ8563_PORTn_AUTH_CTRL_AUTH_MODE_TRAP 0x02
1395 
1396 //Port N Pointer register
1397 #define KSZ8563_PORTn_PTR_PORT_INDEX 0x00070000
1398 #define KSZ8563_PORTn_PTR_QUEUE_PTR 0x00000003
1399 
1400 //Port N Control 1 register
1401 #define KSZ8563_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x00000007
1402 #define KSZ8563_PORTn_CTRL1_PORT3_VLAN_MEMBERSHIP 0x00000004
1403 #define KSZ8563_PORTn_CTRL1_PORT2_VLAN_MEMBERSHIP 0x00000002
1404 #define KSZ8563_PORTn_CTRL1_PORT1_VLAN_MEMBERSHIP 0x00000001
1405 
1406 //Port N Control 2 register
1407 #define KSZ8563_PORTn_CTRL2_NULL_VID_LOOKUP_EN 0x80
1408 #define KSZ8563_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
1409 #define KSZ8563_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
1410 #define KSZ8563_PORTn_CTRL2_802_1X_EN 0x10
1411 #define KSZ8563_PORTn_CTRL2_SELF_ADDR_FILT 0x08
1412 
1413 //Port N MSTP Pointer register
1414 #define KSZ8563_PORTn_MSTP_PTR_MSTP_PTR 0x07
1415 
1416 //Port N MSTP State register
1417 #define KSZ8563_PORTn_MSTP_STATE_TRANSMIT_EN 0x04
1418 #define KSZ8563_PORTn_MSTP_STATE_RECEIVE_EN 0x02
1419 #define KSZ8563_PORTn_MSTP_STATE_LEARNING_DIS 0x01
1420 
1421 //Port N PTP Asymmetry Correction register
1422 #define KSZ8563_PORTn_PTP_ASYM_CORRECTION_PTP_ASYM_COR_SIGN 0x8000
1423 #define KSZ8563_PORTn_PTP_ASYM_CORRECTION_PTP_ASYM_COR 0x7FFF
1424 
1425 //Port N PTP Timestamp Interrupt Status register
1426 #define KSZ8563_PORTn_PTP_TS_INT_STAT_TS_SYNC_INT_STATUS 0x8000
1427 #define KSZ8563_PORTn_PTP_TS_INT_STAT_TS_PDLY_REQ_INT_STATUS 0x4000
1428 #define KSZ8563_PORTn_PTP_TS_INT_STAT_TS_PDLY_RESP_INT_STATUS 0x2000
1429 
1430 //Port N PTP Timestamp Interrupt Enable register
1431 #define KSZ8563_PORTn_PTP_TS_INT_EN_TS_SYNC_INT_ENB 0x8000
1432 #define KSZ8563_PORTn_PTP_TS_INT_EN_TS_PDLY_REQ_INT_ENB 0x4000
1433 #define KSZ8563_PORTn_PTP_TS_INT_EN_TS_PDLY_RESP_INT_ENB 0x2000
1434 
1435 //C++ guard
1436 #ifdef __cplusplus
1437 extern "C" {
1438 #endif
1439 
1440 //KSZ8563 Ethernet switch driver
1441 extern const SwitchDriver ksz8563SwitchDriver;
1442 
1443 //KSZ8563 related functions
1444 error_t ksz8563Init(NetInterface *interface);
1445 void ksz8563InitHook(NetInterface *interface);
1446 
1447 void ksz8563Tick(NetInterface *interface);
1448 
1449 void ksz8563EnableIrq(NetInterface *interface);
1450 void ksz8563DisableIrq(NetInterface *interface);
1451 
1452 void ksz8563EventHandler(NetInterface *interface);
1453 
1454 error_t ksz8563TagFrame(NetInterface *interface, NetBuffer *buffer,
1455  size_t *offset, NetTxAncillary *ancillary);
1456 
1457 error_t ksz8563UntagFrame(NetInterface *interface, uint8_t **frame,
1458  size_t *length, NetRxAncillary *ancillary);
1459 
1460 bool_t ksz8563GetLinkState(NetInterface *interface, uint8_t port);
1461 uint32_t ksz8563GetLinkSpeed(NetInterface *interface, uint8_t port);
1463 
1464 void ksz8563SetPortState(NetInterface *interface, uint8_t port,
1465  SwitchPortState state);
1466 
1468 
1469 void ksz8563SetAgingTime(NetInterface *interface, uint32_t agingTime);
1470 
1471 void ksz8563EnableIgmpSnooping(NetInterface *interface, bool_t enable);
1472 void ksz8563EnableMldSnooping(NetInterface *interface, bool_t enable);
1473 void ksz8563EnableRsvdMcastTable(NetInterface *interface, bool_t enable);
1474 
1476  const SwitchFdbEntry *entry);
1477 
1479  const SwitchFdbEntry *entry);
1480 
1482  SwitchFdbEntry *entry);
1483 
1484 void ksz8563FlushStaticFdbTable(NetInterface *interface);
1485 
1487  SwitchFdbEntry *entry);
1488 
1489 void ksz8563FlushDynamicFdbTable(NetInterface *interface, uint8_t port);
1490 
1492  bool_t enable, uint32_t forwardPorts);
1493 
1494 void ksz8563WritePhyReg(NetInterface *interface, uint8_t port,
1495  uint8_t address, uint16_t data);
1496 
1497 uint16_t ksz8563ReadPhyReg(NetInterface *interface, uint8_t port,
1498  uint8_t address);
1499 
1500 void ksz8563DumpPhyReg(NetInterface *interface, uint8_t port);
1501 
1502 void ksz8563WriteMmdReg(NetInterface *interface, uint8_t port,
1503  uint8_t devAddr, uint16_t regAddr, uint16_t data);
1504 
1505 uint16_t ksz8563ReadMmdReg(NetInterface *interface, uint8_t port,
1506  uint8_t devAddr, uint16_t regAddr);
1507 
1508 void ksz8563WriteSwitchReg8(NetInterface *interface, uint16_t address,
1509  uint8_t data);
1510 
1511 uint8_t ksz8563ReadSwitchReg8(NetInterface *interface, uint16_t address);
1512 
1513 void ksz8563WriteSwitchReg16(NetInterface *interface, uint16_t address,
1514  uint16_t data);
1515 
1516 uint16_t ksz8563ReadSwitchReg16(NetInterface *interface, uint16_t address);
1517 
1518 void ksz8563WriteSwitchReg32(NetInterface *interface, uint16_t address,
1519  uint32_t data);
1520 
1521 uint32_t ksz8563ReadSwitchReg32(NetInterface *interface, uint16_t address);
1522 
1523 //C++ guard
1524 #ifdef __cplusplus
1525 }
1526 #endif
1527 
1528 #endif
void ksz8563DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
int bool_t
Definition: compiler_port.h:53
void ksz8563SetUnknownMcastFwdPorts(NetInterface *interface, bool_t enable, uint32_t forwardPorts)
Set forward ports for unknown multicast packets.
void ksz8563EnableIgmpSnooping(NetInterface *interface, bool_t enable)
Enable IGMP snooping.
void ksz8563FlushStaticFdbTable(NetInterface *interface)
Flush static MAC table.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
uint8_t data[]
Definition: ethernet.h:222
bool_t ksz8563GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
uint16_t ksz8563ReadMmdReg(NetInterface *interface, uint8_t port, uint8_t devAddr, uint16_t regAddr)
Read MMD register.
void ksz8563EventHandler(NetInterface *interface)
KSZ8563 event handler.
uint32_t ksz8563ReadSwitchReg32(NetInterface *interface, uint16_t address)
Read switch register (32 bits)
void ksz8563WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
void ksz8563WriteSwitchReg32(NetInterface *interface, uint16_t address, uint32_t data)
Write switch register (32 bits)
uint8_t ksz8563ReadSwitchReg8(NetInterface *interface, uint16_t address)
Read switch register (8 bits)
error_t
Error codes.
Definition: error.h:43
error_t ksz8563DeleteStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Remove an entry from the static MAC table.
error_t ksz8563Init(NetInterface *interface)
KSZ8563 Ethernet switch initialization.
void ksz8563InitHook(NetInterface *interface)
KSZ8563 custom configuration.
#define NetRxAncillary
Definition: net_misc.h:40
#define NetInterface
Definition: net.h:36
void ksz8563FlushDynamicFdbTable(NetInterface *interface, uint8_t port)
Flush dynamic MAC table.
void ksz8563DisableIrq(NetInterface *interface)
Disable interrupts.
#define NetTxAncillary
Definition: net_misc.h:36
SwitchPortState
Switch port state.
Definition: nic.h:134
error_t ksz8563AddStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Add a new entry to the static MAC table.
void ksz8563SetPortState(NetInterface *interface, uint8_t port, SwitchPortState state)
Set port state.
uint8_t length
Definition: tcp.h:368
void ksz8563WriteSwitchReg16(NetInterface *interface, uint16_t address, uint16_t data)
Write switch register (16 bits)
void ksz8563WriteSwitchReg8(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register (8 bits)
error_t ksz8563GetDynamicFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the dynamic MAC table.
uint16_t port
Definition: dns_common.h:267
NicDuplexMode ksz8563GetDuplexMode(NetInterface *interface, uint8_t port)
Get duplex mode.
uint16_t ksz8563ReadSwitchReg16(NetInterface *interface, uint16_t address)
Read switch register (16 bits)
uint16_t regAddr
void ksz8563Tick(NetInterface *interface)
KSZ8563 timer handler.
Ethernet switch driver.
Definition: nic.h:325
error_t ksz8563GetStaticFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the static MAC table.
Ipv6Addr address[]
Definition: ipv6.h:325
NicDuplexMode
Duplex mode.
Definition: nic.h:122
Network interface controller abstraction layer.
error_t ksz8563TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, NetTxAncillary *ancillary)
Add tail tag to Ethernet frame.
void ksz8563EnableMldSnooping(NetInterface *interface, bool_t enable)
Enable MLD snooping.
SwitchPortState ksz8563GetPortState(NetInterface *interface, uint8_t port)
Get port state.
const SwitchDriver ksz8563SwitchDriver
KSZ8563 Ethernet switch driver.
void ksz8563EnableRsvdMcastTable(NetInterface *interface, bool_t enable)
Enable reserved multicast table.
unsigned int uint_t
Definition: compiler_port.h:50
void ksz8563SetAgingTime(NetInterface *interface, uint32_t agingTime)
Set aging time for dynamic filtering entries.
uint16_t ksz8563ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
error_t ksz8563UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, NetRxAncillary *ancillary)
Decode tail tag from incoming Ethernet frame.
Forwarding database entry.
Definition: nic.h:149
void ksz8563EnableIrq(NetInterface *interface)
Enable interrupts.
void ksz8563WriteMmdReg(NetInterface *interface, uint8_t port, uint8_t devAddr, uint16_t regAddr, uint16_t data)
Write MMD register.
uint32_t ksz8563GetLinkSpeed(NetInterface *interface, uint8_t port)
Get link speed.