ksz8563_driver.h
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1 /**
2  * @file ksz8563_driver.h
3  * @brief KSZ8563 3-port Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 #ifndef _KSZ8563_DRIVER_H
32 #define _KSZ8563_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //KSZ8563 ports
38 #define KSZ8563_PORT1 1
39 #define KSZ8563_PORT2 2
40 
41 //SPI command byte
42 #define KSZ8563_SPI_CMD_WRITE 0x40000000
43 #define KSZ8563_SPI_CMD_READ 0x60000000
44 #define KSZ8563_SPI_CMD_ADDR 0x001FFFE0
45 
46 //KSZ8563 PHY registers
47 #define KSZ8563_BMCR 0x00
48 #define KSZ8563_BMSR 0x01
49 #define KSZ8563_PHYID1 0x02
50 #define KSZ8563_PHYID2 0x03
51 #define KSZ8563_ANAR 0x04
52 #define KSZ8563_ANLPAR 0x05
53 #define KSZ8563_ANER 0x06
54 #define KSZ8563_ANNPR 0x07
55 #define KSZ8563_ANLPNPR 0x08
56 #define KSZ8563_MMDACR 0x0D
57 #define KSZ8563_MMDAADR 0x0E
58 #define KSZ8563_RLB 0x11
59 #define KSZ8563_LINKMD 0x12
60 #define KSZ8563_DPMAPCSS 0x13
61 #define KSZ8563_RXERCTR 0x15
62 #define KSZ8563_ICSR 0x1B
63 #define KSZ8563_AUTOMDI 0x1C
64 #define KSZ8563_PHYCON 0x1F
65 
66 //KSZ8563 Switch registers
67 #define KSZ8563_CHIP_ID0 0x0000
68 #define KSZ8563_CHIP_ID1 0x0001
69 #define KSZ8563_CHIP_ID2 0x0002
70 #define KSZ8563_CHIP_ID3 0x0003
71 #define KSZ8563_SWITCH_OP 0x0300
72 #define KSZ8563_PORT1_INT_STATUS 0x101B
73 #define KSZ8563_PORT1_INT_MASK 0x101F
74 #define KSZ8563_PORT1_OP_CTRL0 0x1020
75 #define KSZ8563_PORT1_STATUS 0x1030
76 #define KSZ8563_PORT1_MSTP_STATE 0x1B04
77 #define KSZ8563_PORT2_INT_STATUS 0x201B
78 #define KSZ8563_PORT2_INT_MASK 0x201F
79 #define KSZ8563_PORT2_OP_CTRL0 0x2020
80 #define KSZ8563_PORT2_STATUS 0x2030
81 #define KSZ8563_PORT2_MSTP_STATE 0x2B04
82 #define KSZ8563_PORT3_INT_STATUS 0x301B
83 #define KSZ8563_PORT3_INT_MASK 0x301F
84 #define KSZ8563_PORT3_OP_CTRL0 0x3020
85 #define KSZ8563_PORT3_STATUS 0x3030
86 #define KSZ8563_PORT3_XMII_CTRL0 0x3300
87 #define KSZ8563_PORT3_XMII_CTRL1 0x3301
88 #define KSZ8563_PORT3_MSTP_STATE 0x3B04
89 
90 //KSZ8563 Switch register access macros
91 #define KSZ8563_PORTn_INT_STATUS(port) (0x001B + ((port) * 0x1000))
92 #define KSZ8563_PORTn_INT_MASK(port) (0x001F + ((port) * 0x1000))
93 #define KSZ8563_PORTn_OP_CTRL0(port) (0x0020 + ((port) * 0x1000))
94 #define KSZ8563_PORTn_STATUS(port) (0x0030 + ((port) * 0x1000))
95 #define KSZ8563_PORTn_XMII_CTRL0(port) (0x0300 + ((port) * 0x1000))
96 #define KSZ8563_PORTn_XMII_CTRL1(port) (0x0301 + ((port) * 0x1000))
97 #define KSZ8563_PORTn_MSTP_STATE(port) (0x0B04 + ((port) * 0x1000))
98 #define KSZ8563_PORTn_ETH_PHY_REG(port, addr) (0x0100 + ((port) * 0x1000) + ((addr) * 2))
99 
100 //PHY Basic Control register
101 #define KSZ8563_BMCR_RESET 0x8000
102 #define KSZ8563_BMCR_LOOPBACK 0x4000
103 #define KSZ8563_BMCR_SPEED_SEL 0x2000
104 #define KSZ8563_BMCR_AN_EN 0x1000
105 #define KSZ8563_BMCR_POWER_DOWN 0x0800
106 #define KSZ8563_BMCR_ISOLATE 0x0400
107 #define KSZ8563_BMCR_RESTART_AN 0x0200
108 #define KSZ8563_BMCR_DUPLEX_MODE 0x0100
109 #define KSZ8563_BMCR_COL_TEST 0x0080
110 
111 //PHY Basic Status register
112 #define KSZ8563_BMSR_100BT4 0x8000
113 #define KSZ8563_BMSR_100BTX_FD 0x4000
114 #define KSZ8563_BMSR_100BTX_HD 0x2000
115 #define KSZ8563_BMSR_10BT_FD 0x1000
116 #define KSZ8563_BMSR_10BT_HD 0x0800
117 #define KSZ8563_BMSR_EXTENDED_STATUS 0x0100
118 #define KSZ8563_BMSR_MF_PREAMBLE_SUPPR 0x0040
119 #define KSZ8563_BMSR_AN_COMPLETE 0x0020
120 #define KSZ8563_BMSR_REMOTE_FAULT 0x0010
121 #define KSZ8563_BMSR_AN_CAPABLE 0x0008
122 #define KSZ8563_BMSR_LINK_STATUS 0x0004
123 #define KSZ8563_BMSR_JABBER_DETECT 0x0002
124 #define KSZ8563_BMSR_EXTENDED_CAPABLE 0x0001
125 
126 //PHY ID High register
127 #define KSZ8563_PHYID1_DEFAULT 0x0022
128 
129 //PHY ID Low register
130 #define KSZ8563_PHYID2_DEFAULT 0x1631
131 
132 //PHY Auto-Negotiation Advertisement register
133 #define KSZ8563_ANAR_NEXT_PAGE 0x8000
134 #define KSZ8563_ANAR_REMOTE_FAULT 0x2000
135 #define KSZ8563_ANAR_PAUSE 0x0C00
136 #define KSZ8563_ANAR_100BT4 0x0200
137 #define KSZ8563_ANAR_100BTX_FD 0x0100
138 #define KSZ8563_ANAR_100BTX_HD 0x0080
139 #define KSZ8563_ANAR_10BT_FD 0x0040
140 #define KSZ8563_ANAR_10BT_HD 0x0020
141 #define KSZ8563_ANAR_SELECTOR 0x001F
142 #define KSZ8563_ANAR_SELECTOR_DEFAULT 0x0001
143 
144 //PHY Auto-Negotiation Link Partner Ability register
145 #define KSZ8563_ANLPAR_NEXT_PAGE 0x8000
146 #define KSZ8563_ANLPAR_ACK 0x4000
147 #define KSZ8563_ANLPAR_REMOTE_FAULT 0x2000
148 #define KSZ8563_ANLPAR_PAUSE 0x0C00
149 #define KSZ8563_ANLPAR_100BT4 0x0200
150 #define KSZ8563_ANLPAR_100BTX_FD 0x0100
151 #define KSZ8563_ANLPAR_100BTX_HD 0x0080
152 #define KSZ8563_ANLPAR_10BT_FD 0x0040
153 #define KSZ8563_ANLPAR_10BT_HD 0x0020
154 #define KSZ8563_ANLPAR_SELECTOR 0x001F
155 #define KSZ8563_ANLPAR_SELECTOR_DEFAULT 0x0001
156 
157 //PHY Auto-Negotiation Expansion Status register
158 #define KSZ8563_ANER_PAR_DETECT_FAULT 0x0010
159 #define KSZ8563_ANER_LP_NEXT_PAGE_ABLE 0x0008
160 #define KSZ8563_ANER_NEXT_PAGE_ABLE 0x0004
161 #define KSZ8563_ANER_PAGE_RECEIVED 0x0002
162 #define KSZ8563_ANER_LP_AN_ABLE 0x0001
163 
164 //PHY Auto-Negotiation Next Page register
165 #define KSZ8563_ANNPR_NEXT_PAGE 0x8000
166 #define KSZ8563_ANNPR_MSG_PAGE 0x2000
167 #define KSZ8563_ANNPR_ACK2 0x1000
168 #define KSZ8563_ANNPR_TOGGLE 0x0800
169 #define KSZ8563_ANNPR_MESSAGE 0x07FF
170 
171 //PHY Auto-Negotiation Link Partner Next Page Ability register
172 #define KSZ8563_ANLPNPR_NEXT_PAGE 0x8000
173 #define KSZ8563_ANLPNPR_ACK 0x4000
174 #define KSZ8563_ANLPNPR_MSG_PAGE 0x2000
175 #define KSZ8563_ANLPNPR_ACK2 0x1000
176 #define KSZ8563_ANLPNPR_TOGGLE 0x0800
177 #define KSZ8563_ANLPNPR_MESSAGE 0x07FF
178 
179 //PHY MMD Setup register
180 #define KSZ8563_MMDACR_FUNC 0xC000
181 #define KSZ8563_MMDACR_FUNC_ADDR 0x0000
182 #define KSZ8563_MMDACR_FUNC_DATA_NO_POST_INC 0x4000
183 #define KSZ8563_MMDACR_FUNC_DATA_POST_INC_RW 0x8000
184 #define KSZ8563_MMDACR_FUNC_DATA_POST_INC_W 0xC000
185 #define KSZ8563_MMDACR_DEVAD 0x001F
186 
187 //PHY Remote Loopback register
188 #define KSZ8563_RLB_REMOTE_LOOPBACK 0x0100
189 
190 //PHY LinkMD register
191 #define KSZ8563_LINKMD_TEST_EN 0x8000
192 #define KSZ8563_LINKMD_PAIR 0x1000
193 #define KSZ8563_LINKMD_PAIR_TXP_TXM 0x0000
194 #define KSZ8563_LINKMD_PAIR_RXP_RXM 0x1000
195 #define KSZ8563_LINKMD_STATUS 0x0300
196 #define KSZ8563_LINKMD_STATUS_NORMAL 0x0000
197 #define KSZ8563_LINKMD_STATUS_OPEN 0x0100
198 #define KSZ8563_LINKMD_STATUS_SHORT 0x0200
199 
200 //PHY Digital PMA/PCS Status register
201 #define KSZ8563_DPMAPCSS_1000BT_LINK_STATUS 0x0002
202 #define KSZ8563_DPMAPCSS_100BTX_LINK_STATUS 0x0001
203 
204 //Port Interrupt Control/Status register
205 #define KSZ8563_ICSR_JABBER_IE 0x8000
206 #define KSZ8563_ICSR_RECEIVE_ERROR_IE 0x4000
207 #define KSZ8563_ICSR_PAGE_RECEIVED_IE 0x2000
208 #define KSZ8563_ICSR_PAR_DETECT_FAULT_IE 0x1000
209 #define KSZ8563_ICSR_LP_ACK_IE 0x0800
210 #define KSZ8563_ICSR_LINK_DOWN_IE 0x0400
211 #define KSZ8563_ICSR_REMOTE_FAULT_IE 0x0200
212 #define KSZ8563_ICSR_LINK_UP_IE 0x0100
213 #define KSZ8563_ICSR_JABBER_IF 0x0080
214 #define KSZ8563_ICSR_RECEIVE_ERROR_IF 0x0040
215 #define KSZ8563_ICSR_PAGE_RECEIVED_IF 0x0020
216 #define KSZ8563_ICSR_PAR_DETECT_FAULT_IF 0x0010
217 #define KSZ8563_ICSR_LP_ACK_IF 0x0008
218 #define KSZ8563_ICSR_LINK_DOWN_IF 0x0004
219 #define KSZ8563_ICSR_REMOTE_FAULT_IF 0x0002
220 #define KSZ8563_ICSR_LINK_UP_IF 0x0001
221 
222 //PHY Auto MDI/MDI-X register
223 #define KSZ8563_AUTOMDI_MDI_SET 0x0080
224 #define KSZ8563_AUTOMDI_SWAP_OFF 0x0040
225 
226 //PHY Control register
227 #define KSZ8563_PHYCON_JABBER_EN 0x0200
228 #define KSZ8563_PHYCON_SPEED_100BTX 0x0020
229 #define KSZ8563_PHYCON_SPEED_10BT 0x0010
230 #define KSZ8563_PHYCON_DUPLEX_STATUS 0x0008
231 
232 //Global Chip ID 0 register
233 #define KSZ8563_CHIP_ID0_DEFAULT 0x00
234 
235 //Global Chip ID 1 register
236 #define KSZ8563_CHIP_ID1_DEFAULT 0x98
237 
238 //Global Chip ID 2 register
239 #define KSZ8563_CHIP_ID2_DEFAULT 0x93
240 
241 //Global Chip ID 3 register
242 #define KSZ8563_CHIP_ID3_REVISION_ID 0xF0
243 #define KSZ8563_CHIP_ID3_GLOBAL_SOFT_RESET 0x01
244 
245 //Switch Operation register
246 #define KSZ8563_SWITCH_OP_DOUBLE_TAG_EN 0x80
247 #define KSZ8563_SWITCH_OP_SOFT_HARD_RESET 0x02
248 #define KSZ8563_SWITCH_OP_START_SWITCH 0x01
249 
250 //Port N Interrupt Status register
251 #define KSZ8563_PORTn_INT_STATUS_PTP 0x04
252 #define KSZ8563_PORTn_INT_STATUS_PHY 0x02
253 #define KSZ8563_PORTn_INT_STATUS_ACL 0x01
254 
255 //Port N Interrupt Mask register
256 #define KSZ8563_PORTn_INT_MASK_PTP 0x04
257 #define KSZ8563_PORTn_INT_MASK_PHY 0x02
258 #define KSZ8563_PORTn_INT_MASK_ACL 0x01
259 
260 //Port N Operation Control 0 register
261 #define KSZ8563_PORTn_OP_CTRL0_LOCAL_LOOPBACK 0x80
262 #define KSZ8563_PORTn_OP_CTRL0_REMOTE_LOOPBACK 0x40
263 #define KSZ8563_PORTn_OP_CTRL0_TAIL_TAG_EN 0x04
264 #define KSZ8563_PORTn_OP_CTRL0_TX_QUEUE_SPLIT_EN 0x03
265 
266 //Port N Status register
267 #define KSZ8563_PORTn_STATUS_SPEED 0x18
268 #define KSZ8563_PORTn_STATUS_SPEED_10MBPS 0x00
269 #define KSZ8563_PORTn_STATUS_SPEED_100MBPS 0x08
270 #define KSZ8563_PORTn_STATUS_DUPLEX 0x04
271 #define KSZ8563_PORTn_STATUS_TX_FLOW_CTRL_EN 0x02
272 #define KSZ8563_PORTn_STATUS_RX_FLOW_CTRL_EN 0x01
273 
274 //XMII Port N Control 0 register
275 #define KSZ8563_PORTn_XMII_CTRL0_DUPLEX 0x40
276 #define KSZ8563_PORTn_XMII_CTRL0_TX_FLOW_CTRL_EN 0x20
277 #define KSZ8563_PORTn_XMII_CTRL0_SPEED_10_100 0x10
278 #define KSZ8563_PORTn_XMII_CTRL0_RX_FLOW_CTRL_EN 0x08
279 
280 //XMII Port N Control 1 register
281 #define KSZ8563_PORTn_XMII_CTRL1_SPEED_1000 0x40
282 #define KSZ8563_PORTn_XMII_CTRL1_RGMII_ID_IG 0x10
283 #define KSZ8563_PORTn_XMII_CTRL1_RGMII_ID_EG 0x08
284 #define KSZ8563_PORTn_XMII_CTRL1_MII_RMII_MODE 0x04
285 #define KSZ8563_PORTn_XMII_CTRL1_IF_TYPE 0x03
286 #define KSZ8563_PORTn_XMII_CTRL1_IF_TYPE_MII 0x00
287 #define KSZ8563_PORTn_XMII_CTRL1_IF_TYPE_RMII 0x01
288 #define KSZ8563_PORTn_XMII_CTRL1_IF_TYPE_RGMII 0x03
289 
290 //Port N MSTP State register
291 #define KSZ8563_PORTn_MSTP_STATE_TRANSMIT_EN 0x04
292 #define KSZ8563_PORTn_MSTP_STATE_RECEIVE_EN 0x02
293 #define KSZ8563_PORTn_MSTP_STATE_LEARNING_DIS 0x01
294 
295 //Tail tag encoding
296 #define KSZ8563_TAIL_TAG_ENCODE(port) (0x20 | ((port) & 0x03))
297 //Tail tag decoding
298 #define KSZ8563_TAIL_TAG_DECODE(tag) (((tag) & 0x01) + 1)
299 
300 //C++ guard
301 #ifdef __cplusplus
302  extern "C" {
303 #endif
304 
305 //KSZ8563 Ethernet switch driver
306 extern const PhyDriver ksz8563PhyDriver;
307 
308 //KSZ8563 related functions
309 error_t ksz8563Init(NetInterface *interface);
310 
311 bool_t ksz8563GetLinkState(NetInterface *interface, uint8_t port);
312 
313 void ksz8563Tick(NetInterface *interface);
314 
315 void ksz8563EnableIrq(NetInterface *interface);
316 void ksz8563DisableIrq(NetInterface *interface);
317 
318 void ksz8563EventHandler(NetInterface *interface);
319 
320 error_t ksz8563TagFrame(NetInterface *interface, NetBuffer *buffer,
321  size_t *offset, uint8_t port, uint16_t *type);
322 
323 error_t ksz8563UntagFrame(NetInterface *interface, uint8_t **frame,
324  size_t *length, uint8_t *port);
325 
326 void ksz8563WritePhyReg(NetInterface *interface, uint8_t port,
327  uint8_t address, uint16_t data);
328 
329 uint16_t ksz8563ReadPhyReg(NetInterface *interface, uint8_t port,
330  uint8_t address);
331 
332 void ksz8563DumpPhyReg(NetInterface *interface, uint8_t port);
333 
334 void ksz8563WriteSwitchReg(NetInterface *interface, uint16_t address,
335  uint8_t data);
336 
337 uint8_t ksz8563ReadSwitchReg(NetInterface *interface, uint16_t address);
338 
339 void ksz8563DumpSwitchReg(NetInterface *interface);
340 
341 //C++ guard
342 #ifdef __cplusplus
343  }
344 #endif
345 
346 #endif
void ksz8563DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
void ksz8563WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
char_t type
uint8_t ksz8563ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
void ksz8563EventHandler(NetInterface *interface)
KSZ8563 event handler.
PHY driver.
Definition: nic.h:214
error_t ksz8563Init(NetInterface *interface)
KSZ8563 Ethernet switch initialization.
error_t ksz8563TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
void ksz8563EnableIrq(NetInterface *interface)
Enable interrupts.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
bool_t ksz8563GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void ksz8563DisableIrq(NetInterface *interface)
Disable interrupts.
void ksz8563DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:42
error_t ksz8563UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
void ksz8563WriteSwitchReg(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register.
uint16_t port
Definition: dns_common.h:223
void ksz8563Tick(NetInterface *interface)
KSZ8563 timer handler.
uint8_t length
Definition: dtls_misc.h:142
uint16_t ksz8563ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
const PhyDriver ksz8563PhyDriver
KSZ8563 Ethernet switch driver.
int bool_t
Definition: compiler_port.h:49
Network interface controller abstraction layer.