ksz8563_driver.h
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1 /**
2  * @file ksz8563_driver.h
3  * @brief KSZ8563 Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.2
29  **/
30 
31 #ifndef _KSZ8563_DRIVER_H
32 #define _KSZ8563_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //KSZ8563 ports
38 #define KSZ8563_PORT1 1
39 #define KSZ8563_PORT2 2
40 
41 //SPI command byte
42 #define KSZ8563_SPI_CMD_WRITE 0x40000000
43 #define KSZ8563_SPI_CMD_READ 0x60000000
44 #define KSZ8563_SPI_CMD_ADDR 0x001FFFE0
45 
46 //KSZ8563 PHY registers
47 #define KSZ8563_PHY_REG_BMCR 0x00
48 #define KSZ8563_PHY_REG_BMSR 0x01
49 #define KSZ8563_PHY_REG_PHYIDR1 0x02
50 #define KSZ8563_PHY_REG_PHYIDR2 0x03
51 #define KSZ8563_PHY_REG_ANAR 0x04
52 #define KSZ8563_PHY_REG_ANLPAR 0x05
53 #define KSZ8563_PHY_REG_ANER 0x06
54 #define KSZ8563_PHY_REG_ANNPTR 0x07
55 #define KSZ8563_PHY_REG_LPNPAR 0x08
56 #define KSZ8563_PHY_REG_MMD_CTRL 0x0D
57 #define KSZ8563_PHY_REG_MMD_DATA 0x0E
58 #define KSZ8563_PHY_REG_EXT_STATUS 0x0F
59 #define KSZ8563_PHY_REG_RLB 0x11
60 #define KSZ8563_PHY_REG_LINKMDCD 0x12
61 #define KSZ8563_PHY_REG_DPMAPCSS 0x13
62 #define KSZ8563_PHY_REG_RXERCTR 0x15
63 #define KSZ8563_PHY_REG_ICSR 0x1B
64 #define KSZ8563_PHY_REG_AUTOMDI 0x1C
65 #define KSZ8563_PHY_REG_PHYCON 0x1F
66 
67 //BMCR register
68 #define BMCR_SOFT_RESET (1 << 15)
69 #define BMCR_LOOPBACK (1 << 14)
70 #define BMCR_SPEED_SEL_LSB (1 << 13)
71 #define BMCR_AN_EN (1 << 12)
72 #define BMCR_POWER_DOWN (1 << 11)
73 #define BMCR_ISOLATE (1 << 10)
74 #define BMCR_RESTART_AN (1 << 9)
75 #define BMCR_DUPLEX_MODE (1 << 8)
76 #define BMCR_COL_TEST (1 << 7)
77 
78 //BMSR register
79 #define BMSR_100BT4 (1 << 15)
80 #define BMSR_100BTX_FD (1 << 14)
81 #define BMSR_100BTX_HD (1 << 13)
82 #define BMSR_10BT_FD (1 << 12)
83 #define BMSR_10BT_HD (1 << 11)
84 #define BMSR_EXTENDED_STATUS (1 << 8)
85 #define BMSR_MF_PREAMBLE_SUPPR (1 << 6)
86 #define BMSR_AN_COMPLETE (1 << 5)
87 #define BMSR_REMOTE_FAULT (1 << 4)
88 #define BMSR_AN_ABLE (1 << 3)
89 #define BMSR_LINK_STATUS (1 << 2)
90 #define BMSR_JABBER_DETECT (1 << 1)
91 #define BMSR_EXTENDED_CAP (1 << 0)
92 
93 //ANAR register
94 #define ANAR_NEXT_PAGE (1 << 15)
95 #define ANAR_REMOTE_FAULT (1 << 13)
96 #define ANAR_PAUSE1 (1 << 11)
97 #define ANAR_PAUSE0 (1 << 10)
98 #define ANAR_100BT4 (1 << 9)
99 #define ANAR_100BTX_FD (1 << 8)
100 #define ANAR_100BTX_HD (1 << 7)
101 #define ANAR_10BT_FD (1 << 6)
102 #define ANAR_10BT_HD (1 << 5)
103 #define ANAR_SELECTOR4 (1 << 4)
104 #define ANAR_SELECTOR3 (1 << 3)
105 #define ANAR_SELECTOR2 (1 << 2)
106 #define ANAR_SELECTOR1 (1 << 1)
107 #define ANAR_SELECTOR0 (1 << 0)
108 
109 //ANLPAR register
110 #define ANLPAR_NEXT_PAGE (1 << 15)
111 #define ANLPAR_LP_ACK (1 << 14)
112 #define ANLPAR_REMOTE_FAULT (1 << 13)
113 #define ANLPAR_PAUSE1 (1 << 11)
114 #define ANLPAR_PAUSE0 (1 << 10)
115 #define ANLPAR_100BT4 (1 << 9)
116 #define ANLPAR_100BTX_FD (1 << 8)
117 #define ANLPAR_100BTX_HD (1 << 7)
118 #define ANLPAR_10BT_FD (1 << 6)
119 #define ANLPAR_10BT_HD (1 << 5)
120 #define ANLPAR_SELECTOR4 (1 << 4)
121 #define ANLPAR_SELECTOR3 (1 << 3)
122 #define ANLPAR_SELECTOR2 (1 << 2)
123 #define ANLPAR_SELECTOR1 (1 << 1)
124 #define ANLPAR_SELECTOR0 (1 << 0)
125 
126 //ANER register
127 #define ANER_PAR_DET_FAULT (1 << 4)
128 #define ANER_LP_NEXT_PAGE_ABLE (1 << 3)
129 #define ANER_NEXT_PAGE_ABLE (1 << 2)
130 #define ANER_PAGE_RECEIVED (1 << 1)
131 #define ANER_LP_AN_ABLE (1 << 0)
132 
133 //ANNPTR register
134 #define ANNPTR_NEXT_PAGE (1 << 15)
135 #define ANNPTR_MSG_PAGE (1 << 13)
136 #define ANNPTR_ACK2 (1 << 12)
137 #define ANNPTR_TOGGLE (1 << 11)
138 #define ANNPTR_MESSAGE10 (1 << 10)
139 #define ANNPTR_MESSAGE9 (1 << 9)
140 #define ANNPTR_MESSAGE8 (1 << 8)
141 #define ANNPTR_MESSAGE7 (1 << 7)
142 #define ANNPTR_MESSAGE6 (1 << 6)
143 #define ANNPTR_MESSAGE5 (1 << 5)
144 #define ANNPTR_MESSAGE4 (1 << 4)
145 #define ANNPTR_MESSAGE3 (1 << 3)
146 #define ANNPTR_MESSAGE2 (1 << 2)
147 #define ANNPTR_MESSAGE1 (1 << 1)
148 #define ANNPTR_MESSAGE0 (1 << 0)
149 
150 //LPNPAR register
151 #define LPNPAR_NEXT_PAGE (1 << 15)
152 #define LPNPAR_ACK (1 << 14)
153 #define LPNPAR_MSG_PAGE (1 << 13)
154 #define LPNPAR_ACK2 (1 << 12)
155 #define LPNPAR_TOGGLE (1 << 11)
156 #define LPNPAR_MESSAGE10 (1 << 10)
157 #define LPNPAR_MESSAGE9 (1 << 9)
158 #define LPNPAR_MESSAGE8 (1 << 8)
159 #define LPNPAR_MESSAGE7 (1 << 7)
160 #define LPNPAR_MESSAGE6 (1 << 6)
161 #define LPNPAR_MESSAGE5 (1 << 5)
162 #define LPNPAR_MESSAGE4 (1 << 4)
163 #define LPNPAR_MESSAGE3 (1 << 3)
164 #define LPNPAR_MESSAGE2 (1 << 2)
165 #define LPNPAR_MESSAGE1 (1 << 1)
166 #define LPNPAR_MESSAGE0 (1 << 0)
167 
168 //MMD_CTRL register
169 #define MMD_CTRL_DEVICE_OP_MODE1 (1 << 15)
170 #define MMD_CTRL_DEVICE_OP_MODE0 (1 << 14)
171 #define MMD_CTRL_DEVICE_ADDR4 (1 << 4)
172 #define MMD_CTRL_DEVICE_ADDR3 (1 << 3)
173 #define MMD_CTRL_DEVICE_ADDR2 (1 << 2)
174 #define MMD_CTRL_DEVICE_ADDR1 (1 << 1)
175 #define MMD_CTRL_DEVICE_ADDR0 (1 << 0)
176 
177 //EXT_STATUS register
178 #define EXT_STATUS_1000BX_FD (1 << 15)
179 #define EXT_STATUS_1000BX_HD (1 << 14)
180 #define EXT_STATUS_1000BT_FD (1 << 13)
181 #define EXT_STATUS_1000BT_HD (1 << 12)
182 
183 //RLB register
184 #define RLB_REMOTE_LOOPBACK (1 << 8)
185 
186 //LINKMDCD register
187 #define LINKMDCD_CDT_EN (1 << 15)
188 #define LINKMDCD_CDT_PAIR1 (1 << 13)
189 #define LINKMDCD_CDT_PAIR0 (1 << 12)
190 #define LINKMDCD_CDT_STATUS1 (1 << 9)
191 #define LINKMDCD_CDT_STATUS0 (1 << 8)
192 
193 //DPMAPCSS register
194 #define DPMAPCSS_1000BT_LINK_STATUS (1 << 2)
195 #define DPMAPCSS_100BTX_LINK_STATUS (1 << 1)
196 
197 //ICSR register
198 #define ICSR_JABBER_IE (1 << 15)
199 #define ICSR_RECEIVE_ERROR_IE (1 << 14)
200 #define ICSR_PAGE_RECEIVED_IE (1 << 13)
201 #define ICSR_PAR_DET_FAULT_IE (1 << 12)
202 #define ICSR_LP_ACK_IE (1 << 11)
203 #define ICSR_LINK_DOWN_IE (1 << 10)
204 #define ICSR_REMOTE_FAULT_IE (1 << 9)
205 #define ICSR_LINK_UP_IE (1 << 8)
206 #define ICSR_JABBER_IF (1 << 7)
207 #define ICSR_RECEIVE_ERROR_IF (1 << 6)
208 #define ICSR_PAGE_RECEIVED_IF (1 << 5)
209 #define ICSR_PAR_DET_FAULT_IF (1 << 4)
210 #define ICSR_LP_ACK_IF (1 << 3)
211 #define ICSR_LINK_DOWN_IF (1 << 2)
212 #define ICSR_REMOTE_FAULT_IF (1 << 1)
213 #define ICSR_LINK_UP_IF (1 << 0)
214 
215 //AUTOMDI register
216 #define AUTOMDI_MDI_SEL (1 << 7)
217 #define AUTOMDI_SWAP_OFF (1 << 6)
218 
219 //PHYCON register
220 #define PHYCON_JABBER_EN (1 << 9)
221 #define PHYCON_SPEED_1000BT (1 << 6)
222 #define PHYCON_SPEED_100BTX (1 << 5)
223 #define PHYCON_SPEED_10BT (1 << 4)
224 #define PHYCON_DUPLEX_STATUS (1 << 3)
225 #define PHYCON_1000BT_MS_STATUS (1 << 2)
226 
227 //KSZ8563 switch registers
228 #define KSZ8563_SW_REG_CHIP_ID0 0x0000
229 #define KSZ8563_SW_REG_CHIP_ID1 0x0001
230 #define KSZ8563_SW_REG_CHIP_ID2 0x0002
231 #define KSZ8563_SW_REG_CHIP_ID3 0x0003
232 #define KSZ8563_SW_REG_SWITCH_OP 0x0300
233 #define KSZ8563_SW_REG_PORT_OP_CTRL0(n) (0x0020 + ((n) * 0x1000))
234 #define KSZ8563_SW_REG_XMII_PORT_CTRL0(n) (0x0300 + ((n) * 0x1000))
235 #define KSZ8563_SW_REG_XMII_PORT_CTRL1(n) (0x0301 + ((n) * 0x1000))
236 #define KSZ8563_SW_REG_PORT_MSTP_STATE(n) (0x0B04 + ((n) * 0x1000))
237 
238 //Chip ID1 register
239 #define CHIP_ID1_CHIP_ID_MSB 0xFF
240 #define CHIP_ID1_CHIP_ID_MSB_DEFAULT 0x98
241 
242 //Chip ID2 register
243 #define CHIP_ID2_CHIP_ID_LSB 0xFF
244 #define CHIP_ID2_CHIP_ID_LSB_DEFAULT 0x93
245 
246 //Switch operation register
247 #define SWITCH_OP_DOUBLE_TAG_EN (1 << 7)
248 #define SWITCH_OP_SOFT_RESET (1 << 1)
249 #define SWITCH_OP_START_SWITCH (1 << 0)
250 
251 //Port operation control 0 register
252 #define PORT_OP_CTRL0_LOCAL_LOOPBACK (1 << 7)
253 #define PORT_OP_CTRL0_REMOTE_LOOPBACK (1 << 6)
254 #define PORT_OP_CTRL0_TAIL_TAG_EN (1 << 2)
255 #define PORT_OP_CTRL0_TX_QUEUE_SPLIT_EN1 (1 << 1)
256 #define PORT_OP_CTRL0_TX_QUEUE_SPLIT_EN0 (1 << 0)
257 
258 //XMII port control 0 register
259 #define XMII_PORT_CTRL0_PORT_DUPLEX (1 << 6)
260 #define XMII_PORT_CTRL0_PORT_TX_FLOW_CTRL_EN (1 << 5)
261 #define XMII_PORT_CTRL0_PORT_SPEED_10_100 (1 << 4)
262 #define XMII_PORT_CTRL0_PORT_RX_FLOW_CTRL_EN (1 << 3)
263 
264 //XMII port control 1 register
265 #define XMII_PORT_CTRL1_PORT_SPEED_1000 (1 << 6)
266 #define XMII_PORT_CTRL1_RGMII_ID_IG (1 << 4)
267 #define XMII_PORT_CTRL1_RGMII_ID_EG (1 << 3)
268 #define XMII_PORT_CTRL1_MII_RMII_MODE (1 << 2)
269 #define XMII_PORT_CTRL1_PORT_IF_TYPE1 (1 << 1)
270 #define XMII_PORT_CTRL1_PORT_IF_TYPE0 (1 << 0)
271 
272 //Port MSTP state register
273 #define PORT_MSTP_STATE_TRANSMIT_EN (1 << 2)
274 #define PORT_MSTP_STATE_RECEIVE_EN (1 << 1)
275 #define PORT_MSTP_STATE_LEARNING_DIS (1 << 0)
276 
277 //KSZ8563 PHY registers
278 #define KSZ8563_SW_REG_PORT_ETH_PHY(n, a) (0x0100 + ((n) * 0x1000) + ((a) * 2))
279 
280 //Tail tag encoding
281 #define KSZ8563_TAIL_TAG_ENCODE(port) (0x20 | ((port) & 0x03))
282 //Tail tag decoding
283 #define KSZ8563_TAIL_TAG_DECODE(tag) (((tag) & 0x01) + 1)
284 
285 //C++ guard
286 #ifdef __cplusplus
287  extern "C" {
288 #endif
289 
290 //KSZ8563 Ethernet switch driver
291 extern const PhyDriver ksz8563PhyDriver;
292 
293 //KSZ8563 related functions
294 error_t ksz8563Init(NetInterface *interface);
295 
296 bool_t ksz8563GetLinkState(NetInterface *interface, uint8_t port);
297 
298 void ksz8563Tick(NetInterface *interface);
299 
300 void ksz8563EnableIrq(NetInterface *interface);
301 void ksz8563DisableIrq(NetInterface *interface);
302 
303 void ksz8563EventHandler(NetInterface *interface);
304 
305 error_t ksz8563TagFrame(NetInterface *interface, NetBuffer *buffer,
306  size_t *offset, uint8_t port, uint16_t *type);
307 
308 error_t ksz8563UntagFrame(NetInterface *interface, uint8_t **frame,
309  size_t *length, uint8_t *port);
310 
311 void ksz8563WritePhyReg(NetInterface *interface, uint8_t port,
312  uint8_t address, uint16_t data);
313 
314 uint16_t ksz8563ReadPhyReg(NetInterface *interface, uint8_t port,
315  uint8_t address);
316 
317 void ksz8563DumpPhyReg(NetInterface *interface, uint8_t port);
318 
319 void ksz8563WriteSwitchReg(NetInterface *interface, uint16_t address,
320  uint8_t data);
321 
322 uint8_t ksz8563ReadSwitchReg(NetInterface *interface, uint16_t address);
323 
324 void ksz8563DumpSwitchReg(NetInterface *interface);
325 
326 //C++ guard
327 #ifdef __cplusplus
328  }
329 #endif
330 
331 #endif
void ksz8563DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
void ksz8563WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
char_t type
uint8_t ksz8563ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
void ksz8563EventHandler(NetInterface *interface)
KSZ8563 event handler.
PHY driver.
Definition: nic.h:199
error_t ksz8563Init(NetInterface *interface)
KSZ8563 Ethernet switch initialization.
error_t ksz8563TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
void ksz8563EnableIrq(NetInterface *interface)
Enable interrupts.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
bool_t ksz8563GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void ksz8563DisableIrq(NetInterface *interface)
Disable interrupts.
void ksz8563DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:42
error_t ksz8563UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
void ksz8563WriteSwitchReg(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register.
uint16_t port
Definition: dns_common.h:223
void ksz8563Tick(NetInterface *interface)
KSZ8563 timer handler.
uint8_t length
Definition: dtls_misc.h:142
uint16_t ksz8563ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
const PhyDriver ksz8563PhyDriver
KSZ8563 Ethernet switch driver.
int bool_t
Definition: compiler_port.h:49
Network interface controller abstraction layer.