ksz8563_driver.c
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1 /**
2  * @file ksz8563_driver.c
3  * @brief KSZ8563 3-port Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "core/net.h"
36 #include "core/ethernet_misc.h"
38 #include "debug.h"
39 
40 
41 /**
42  * @brief KSZ8563 Ethernet switch driver
43  **/
44 
46 {
54 };
55 
56 
57 /**
58  * @brief Tail tag rules (host to KSZ8563)
59  **/
60 
61 const uint8_t ksz8563IngressTailTag[3] =
62 {
63  0,
66 };
67 
68 
69 /**
70  * @brief KSZ8563 Ethernet switch initialization
71  * @param[in] interface Underlying network interface
72  * @return Error code
73  **/
74 
76 {
77  uint_t port;
78  uint8_t temp;
79 
80  //Debug message
81  TRACE_INFO("Initializing KSZ8563...\r\n");
82 
83  //SPI slave mode?
84  if(interface->spiDriver != NULL)
85  {
86  //Initialize SPI
87  interface->spiDriver->init();
88 
89  //Wait for the serial interface to be ready
90  do
91  {
92  //Read CHIP_ID1 register
93  temp = ksz8563ReadSwitchReg(interface, KSZ8563_CHIP_ID1);
94 
95  //The returned data is invalid until the serial interface is ready
96  } while(temp != KSZ8563_CHIP_ID1_DEFAULT);
97 
98  //Reset switch
101 
102  //Wait for the reset to complete
103  do
104  {
105  //Read switch operation register
106  temp = ksz8563ReadSwitchReg(interface, KSZ8563_SWITCH_OP);
107 
108  //The reset bit is self-clearing
109  } while((temp & KSZ8563_SWITCH_OP_SOFT_HARD_RESET) != 0);
110 
111 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
112  //Tail tagging mode?
113  if(interface->port != 0)
114  {
115  //Enable tail tag feature
116  temp = ksz8563ReadSwitchReg(interface, KSZ8563_PORT3_OP_CTRL0);
119 
120  //Loop through ports
122  {
123  //Disable packet transmission and switch address learning
129  }
130  }
131  else
132 #endif
133  {
134  //Disable tail tag feature
135  temp = ksz8563ReadSwitchReg(interface, KSZ8563_PORT3_OP_CTRL0);
138 
139  //Loop through ports
141  {
142  //Enable transmission, reception and switch address learning
148  }
149  }
150 
151  //Add internal delay to ingress and egress RGMII clocks
156 
157  //Start switch operation
160  }
161 
162  //Loop through ports
164  {
165  //Debug message
166  TRACE_DEBUG("Port %u:\r\n", port);
167  //Dump PHY registers for debugging purpose
168  ksz8563DumpPhyReg(interface, port);
169  }
170 
171  //Force the TCP/IP stack to poll the link state at startup
172  interface->phyEvent = TRUE;
173  //Notify the TCP/IP stack of the event
175 
176  //Successful initialization
177  return NO_ERROR;
178 }
179 
180 
181 /**
182  * @brief Get link state
183  * @param[in] interface Underlying network interface
184  * @param[in] port Port number
185  * @return Link state
186  **/
187 
189 {
190  uint16_t value;
191  bool_t linkState;
192 
193  //Check port number
194  if(port >= KSZ8563_PORT1 && port <= KSZ8563_PORT2)
195  {
196  //Get exclusive access
198 
199  //Any link failure condition is latched in the BMSR register. Reading
200  //the register twice will always return the actual link status
201  value = ksz8563ReadPhyReg(interface, port, KSZ8563_BMSR);
202  value = ksz8563ReadPhyReg(interface, port, KSZ8563_BMSR);
203 
204  //Retrieve current link state
205  linkState = (value & KSZ8563_BMSR_LINK_STATUS) ? TRUE : FALSE;
206 
207  //Release exclusive access
209  }
210  else
211  {
212  //The specified port number is not valid
213  linkState = FALSE;
214  }
215 
216  //Return link status
217  return linkState;
218 }
219 
220 
221 /**
222  * @brief KSZ8563 timer handler
223  * @param[in] interface Underlying network interface
224  **/
225 
226 void ksz8563Tick(NetInterface *interface)
227 {
228  uint_t port;
229  uint16_t value;
230  bool_t linkState;
231 
232 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
233  //Tail tagging mode?
234  if(interface->port != 0)
235  {
236  uint_t i;
237  NetInterface *virtualInterface;
238 
239  //Loop through network interfaces
240  for(i = 0; i < NET_INTERFACE_COUNT; i++)
241  {
242  //Point to the current interface
243  virtualInterface = &netInterface[i];
244 
245  //Check whether the current virtual interface is attached to the
246  //physical interface
247  if(virtualInterface == interface || virtualInterface->parent == interface)
248  {
249  //The tail tag is used to indicate the source/destination port
250  port = virtualInterface->port;
251 
252  //Valid port?
253  if(port >= KSZ8563_PORT1 && port <= KSZ8563_PORT2)
254  {
255  //Read status register
256  value = ksz8563ReadPhyReg(interface, port, KSZ8563_BMSR);
257 
258  //Retrieve current link state
259  linkState = (value & KSZ8563_BMSR_LINK_STATUS) ? TRUE : FALSE;
260 
261  //Link up or link down event?
262  if(linkState != virtualInterface->linkState)
263  {
264  //Set event flag
265  interface->phyEvent = TRUE;
266  //Notify the TCP/IP stack of the event
268  }
269  }
270  }
271  }
272  }
273  else
274 #endif
275  {
276  //Initialize link state
277  linkState = FALSE;
278 
279  //Loop through ports
281  {
282  //Read status register
283  value = ksz8563ReadPhyReg(interface, port, KSZ8563_BMSR);
284 
285  //Retrieve current link state
287  linkState = TRUE;
288  }
289 
290  //Link up or link down event?
291  if(linkState != interface->linkState)
292  {
293  //Set event flag
294  interface->phyEvent = TRUE;
295  //Notify the TCP/IP stack of the event
297  }
298  }
299 }
300 
301 
302 /**
303  * @brief Enable interrupts
304  * @param[in] interface Underlying network interface
305  **/
306 
308 {
309 }
310 
311 
312 /**
313  * @brief Disable interrupts
314  * @param[in] interface Underlying network interface
315  **/
316 
318 {
319 }
320 
321 
322 /**
323  * @brief KSZ8563 event handler
324  * @param[in] interface Underlying network interface
325  **/
326 
328 {
329  uint_t port;
330  uint16_t value;
331  bool_t linkState;
332 
333 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
334  //Tail tagging mode?
335  if(interface->port != 0)
336  {
337  uint_t i;
338  NetInterface *virtualInterface;
339 
340  //Loop through network interfaces
341  for(i = 0; i < NET_INTERFACE_COUNT; i++)
342  {
343  //Point to the current interface
344  virtualInterface = &netInterface[i];
345 
346  //Check whether the current virtual interface is attached to the
347  //physical interface
348  if(virtualInterface == interface ||
349  virtualInterface->parent == interface)
350  {
351  //The tail tag is used to indicate the source/destination port
352  port = virtualInterface->port;
353 
354  //Valid port?
355  if(port >= KSZ8563_PORT1 && port <= KSZ8563_PORT2)
356  {
357  //Any link failure condition is latched in the BMSR register. Reading
358  //the register twice will always return the actual link status
359  value = ksz8563ReadPhyReg(interface, port, KSZ8563_BMSR);
360  value = ksz8563ReadPhyReg(interface, port, KSZ8563_BMSR);
361 
362  //Retrieve current link state
363  linkState = (value & KSZ8563_BMSR_LINK_STATUS) ? TRUE : FALSE;
364 
365  //Link up event?
366  if(linkState && !virtualInterface->linkState)
367  {
368  //Adjust MAC configuration parameters for proper operation
369  interface->linkSpeed = NIC_LINK_SPEED_1GBPS;
370  interface->duplexMode = NIC_FULL_DUPLEX_MODE;
371  interface->nicDriver->updateMacConfig(interface);
372 
373  //Read PHY control register
375 
376  //Check current speed
378  {
379  //100BASE-TX
380  virtualInterface->linkSpeed = NIC_LINK_SPEED_100MBPS;
381  }
383  {
384  //10BASE-T
385  virtualInterface->linkSpeed = NIC_LINK_SPEED_10MBPS;
386  }
387  else
388  {
389  //Debug message
390  TRACE_WARNING("Invalid speed!\r\n");
391  }
392 
393  //Check current duplex mode
395  virtualInterface->duplexMode = NIC_FULL_DUPLEX_MODE;
396  else
397  virtualInterface->duplexMode = NIC_HALF_DUPLEX_MODE;
398 
399  //Update link state
400  virtualInterface->linkState = TRUE;
401 
402  //Process link state change event
403  nicNotifyLinkChange(virtualInterface);
404  }
405  //Link down event
406  else if(!linkState && virtualInterface->linkState)
407  {
408  //Update link state
409  virtualInterface->linkState = FALSE;
410 
411  //Process link state change event
412  nicNotifyLinkChange(virtualInterface);
413  }
414  }
415  }
416  }
417  }
418  else
419 #endif
420  {
421  //Initialize link state
422  linkState = FALSE;
423 
424  //Loop through ports
426  {
427  //Any link failure condition is latched in the BMSR register. Reading
428  //the register twice will always return the actual link status
429  value = ksz8563ReadPhyReg(interface, port, KSZ8563_BMSR);
430  value = ksz8563ReadPhyReg(interface, port, KSZ8563_BMSR);
431 
432  //Retrieve current link state
434  linkState = TRUE;
435  }
436 
437  //Link up event?
438  if(linkState)
439  {
440  //Adjust MAC configuration parameters for proper operation
441  interface->linkSpeed = NIC_LINK_SPEED_1GBPS;
442  interface->duplexMode = NIC_FULL_DUPLEX_MODE;
443  interface->nicDriver->updateMacConfig(interface);
444 
445  //Update link state
446  interface->linkState = TRUE;
447  }
448  else
449  {
450  //Update link state
451  interface->linkState = FALSE;
452  }
453 
454  //Process link state change event
455  nicNotifyLinkChange(interface);
456  }
457 }
458 
459 
460 /**
461  * @brief Add tail tag to Ethernet frame
462  * @param[in] interface Underlying network interface
463  * @param[in] buffer Multi-part buffer containing the payload
464  * @param[in,out] offset Offset to the first payload byte
465  * @param[in] port Switch port identifier
466  * @param[in,out] type Ethernet type
467  * @return Error code
468  **/
469 
471  size_t *offset, uint8_t port, uint16_t *type)
472 {
473 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
474  error_t error;
475  size_t length;
476  const uint8_t *tailTag;
477 
478  //Valid port?
479  if(port >= KSZ8563_PORT1 && port <= KSZ8563_PORT2)
480  {
481  //The one byte tail tagging is used to indicate the destination port
482  tailTag = &ksz8563IngressTailTag[port];
483 
484  //Retrieve the length of the frame
485  length = netBufferGetLength(buffer) - *offset;
486 
487  //The host controller should manually add padding to the packet before
488  //inserting the tail tag
489  error = ethPadFrame(buffer, &length);
490 
491  //Check status code
492  if(!error)
493  {
494  //The tail tag is inserted at the end of the packet, just before the CRC
495  error = netBufferAppend(buffer, tailTag, sizeof(uint8_t));
496  }
497  }
498  else
499  {
500  //Invalid port identifier
501  error = ERROR_WRONG_IDENTIFIER;
502  }
503 
504  //Return status code
505  return error;
506 #else
507  //Tail tagging mode is not implemented
508  return NO_ERROR;
509 #endif
510 }
511 
512 
513 /**
514  * @brief Decode tail tag from incoming Ethernet frame
515  * @param[in] interface Underlying network interface
516  * @param[in,out] frame Pointer to the received Ethernet frame
517  * @param[in,out] length Length of the frame, in bytes
518  * @param[out] port Switch port identifier
519  * @return Error code
520  **/
521 
522 error_t ksz8563UntagFrame(NetInterface *interface, uint8_t **frame,
523  size_t *length, uint8_t *port)
524 {
525 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
526  error_t error;
527  uint8_t *tailTag;
528 
529  //Valid Ethernet frame received?
530  if(*length >= (sizeof(EthHeader) + sizeof(uint8_t)))
531  {
532  //The tail tag is inserted at the end of the packet, just before the CRC
533  tailTag = *frame + *length - sizeof(uint8_t);
534 
535  //The one byte tail tagging is used to indicate the source port
536  *port = KSZ8563_TAIL_TAG_DECODE(*tailTag);
537 
538  //Strip tail tag from Ethernet frame
539  *length -= sizeof(uint8_t);
540 
541  //Successful processing
542  error = NO_ERROR;
543  }
544  else
545  {
546  //Drop the received frame
547  error = ERROR_INVALID_LENGTH;
548  }
549 
550  //Return status code
551  return error;
552 #else
553  //Tail tagging mode is not implemented
554  return NO_ERROR;
555 #endif
556 }
557 
558 
559 /**
560  * @brief Write PHY register
561  * @param[in] interface Underlying network interface
562  * @param[in] port Port number
563  * @param[in] address PHY register address
564  * @param[in] data Register value
565  **/
566 
567 void ksz8563WritePhyReg(NetInterface *interface, uint8_t port,
568  uint8_t address, uint16_t data)
569 {
570  uint32_t command;
571 
572  //SPI slave mode?
573  if(interface->spiDriver != NULL)
574  {
575  //Set up a write operation
576  command = KSZ8563_SPI_CMD_WRITE;
577  //Set register address
578  command |= KSZ8563_PORTn_ETH_PHY_REG(port, address) << 5;
579 
580  //Pull the CS pin low
581  interface->spiDriver->assertCs();
582 
583  //Write 32-bit command
584  interface->spiDriver->transfer((command >> 24) & 0xFF);
585  interface->spiDriver->transfer((command >> 16) & 0xFF);
586  interface->spiDriver->transfer((command >> 8) & 0xFF);
587  interface->spiDriver->transfer(command & 0xFF);
588 
589  //Write 16-bit data
590  interface->spiDriver->transfer(MSB(data));
591  interface->spiDriver->transfer(LSB(data));
592 
593  //Terminate the operation by raising the CS pin
594  interface->spiDriver->deassertCs();
595  }
596  else
597  {
598  //Write the specified PHY register
599  interface->nicDriver->writePhyReg(SMI_OPCODE_WRITE, port, address, data);
600  }
601 }
602 
603 
604 /**
605  * @brief Read PHY register
606  * @param[in] interface Underlying network interface
607  * @param[in] port Port number
608  * @param[in] address PHY register address
609  * @return Register value
610  **/
611 
612 uint16_t ksz8563ReadPhyReg(NetInterface *interface, uint8_t port,
613  uint8_t address)
614 {
615  uint16_t data;
616  uint32_t command;
617 
618  //SPI slave mode?
619  if(interface->spiDriver != NULL)
620  {
621  //Set up a read operation
622  command = KSZ8563_SPI_CMD_READ;
623  //Set register address
624  command |= KSZ8563_PORTn_ETH_PHY_REG(port, address) << 5;
625 
626  //Pull the CS pin low
627  interface->spiDriver->assertCs();
628 
629  //Write 32-bit command
630  interface->spiDriver->transfer((command >> 24) & 0xFF);
631  interface->spiDriver->transfer((command >> 16) & 0xFF);
632  interface->spiDriver->transfer((command >> 8) & 0xFF);
633  interface->spiDriver->transfer(command & 0xFF);
634 
635  //Read 16-bit data
636  data = interface->spiDriver->transfer(0xFF) << 8;
637  data |= interface->spiDriver->transfer(0xFF);
638 
639  //Terminate the operation by raising the CS pin
640  interface->spiDriver->deassertCs();
641  }
642  else
643  {
644  //Read the specified PHY register
645  data = interface->nicDriver->readPhyReg(SMI_OPCODE_READ, port, address);
646  }
647 
648  //Return register value
649  return data;
650 }
651 
652 
653 /**
654  * @brief Dump PHY registers for debugging purpose
655  * @param[in] interface Underlying network interface
656  * @param[in] port Port number
657  **/
658 
659 void ksz8563DumpPhyReg(NetInterface *interface, uint8_t port)
660 {
661  uint8_t i;
662 
663  //Loop through PHY registers
664  for(i = 0; i < 32; i++)
665  {
666  //Display current PHY register
667  TRACE_DEBUG("%02" PRIu8 ": 0x%04" PRIX16 "\r\n", i,
668  ksz8563ReadPhyReg(interface, port, i));
669  }
670 
671  //Terminate with a line feed
672  TRACE_DEBUG("\r\n");
673 }
674 
675 
676 /**
677  * @brief Write switch register
678  * @param[in] interface Underlying network interface
679  * @param[in] address Switch register address
680  * @param[in] data Register value
681  **/
682 
683 void ksz8563WriteSwitchReg(NetInterface *interface, uint16_t address,
684  uint8_t data)
685 {
686  uint32_t command;
687 
688  //SPI slave mode?
689  if(interface->spiDriver != NULL)
690  {
691  //Set up a write operation
692  command = KSZ8563_SPI_CMD_WRITE;
693  //Set register address
694  command |= (address << 5) & KSZ8563_SPI_CMD_ADDR;
695 
696  //Pull the CS pin low
697  interface->spiDriver->assertCs();
698 
699  //Write 32-bit command
700  interface->spiDriver->transfer((command >> 24) & 0xFF);
701  interface->spiDriver->transfer((command >> 16) & 0xFF);
702  interface->spiDriver->transfer((command >> 8) & 0xFF);
703  interface->spiDriver->transfer(command & 0xFF);
704 
705  //Write data
706  interface->spiDriver->transfer(data);
707 
708  //Terminate the operation by raising the CS pin
709  interface->spiDriver->deassertCs();
710  }
711  else
712  {
713  //The MDC/MDIO interface does not have access to all the configuration
714  //registers. It can only access the standard MIIM registers
715  }
716 }
717 
718 
719 /**
720  * @brief Read switch register
721  * @param[in] interface Underlying network interface
722  * @param[in] address Switch register address
723  * @return Register value
724  **/
725 
726 uint8_t ksz8563ReadSwitchReg(NetInterface *interface, uint16_t address)
727 {
728  uint8_t data;
729  uint32_t command;
730 
731  //SPI slave mode?
732  if(interface->spiDriver != NULL)
733  {
734  //Set up a read operation
735  command = KSZ8563_SPI_CMD_READ;
736  //Set register address
737  command |= (address << 5) & KSZ8563_SPI_CMD_ADDR;
738 
739  //Pull the CS pin low
740  interface->spiDriver->assertCs();
741 
742  //Write 32-bit command
743  interface->spiDriver->transfer((command >> 24) & 0xFF);
744  interface->spiDriver->transfer((command >> 16) & 0xFF);
745  interface->spiDriver->transfer((command >> 8) & 0xFF);
746  interface->spiDriver->transfer(command & 0xFF);
747 
748  //Read data
749  data = interface->spiDriver->transfer(0xFF);
750 
751  //Terminate the operation by raising the CS pin
752  interface->spiDriver->deassertCs();
753  }
754  else
755  {
756  //The MDC/MDIO interface does not have access to all the configuration
757  //registers. It can only access the standard MIIM registers
758  data = 0;
759  }
760 
761  //Return register value
762  return data;
763 }
764 
765 
766 /**
767  * @brief Dump switch registers for debugging purpose
768  * @param[in] interface Underlying network interface
769  **/
770 
772 {
773  uint16_t i;
774 
775  //Loop through switch registers
776  for(i = 0; i < 256; i++)
777  {
778  //Display current switch register
779  TRACE_DEBUG("0x%02" PRIX16 " (%02" PRIu16 ") : 0x%02" PRIX8 "\r\n",
780  i, i, ksz8563ReadSwitchReg(interface, i));
781  }
782 
783  //Terminate with a line feed
784  TRACE_DEBUG("\r\n");
785 }
#define KSZ8563_PORTn_XMII_CTRL1_RGMII_ID_IG
#define KSZ8563_BMSR
#define KSZ8563_SWITCH_OP_START_SWITCH
#define KSZ8563_PORTn_MSTP_STATE_TRANSMIT_EN
#define KSZ8563_PORTn_OP_CTRL0_TAIL_TAG_EN
const uint8_t ksz8563IngressTailTag[3]
Tail tag rules (host to KSZ8563)
void nicNotifyLinkChange(NetInterface *interface)
Process link state change notification.
Definition: nic.c:536
void ksz8563Tick(NetInterface *interface)
KSZ8563 timer handler.
#define KSZ8563_BMSR_LINK_STATUS
#define MSB(x)
Definition: os_port.h:58
#define KSZ8563_PORTn_MSTP_STATE_RECEIVE_EN
TCP/IP stack core.
Debugging facilities.
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
#define KSZ8563_PORT3_XMII_CTRL1
#define KSZ8563_SWITCH_OP
void ksz8563EnableIrq(NetInterface *interface)
Enable interrupts.
Helper functions for Ethernet.
void ksz8563DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
KSZ8563 3-port Ethernet switch.
#define KSZ8563_PORT2
char_t type
#define SMI_OPCODE_READ
Definition: nic.h:63
#define LSB(x)
Definition: os_port.h:54
error_t ethPadFrame(NetBuffer *buffer, size_t *length)
Ethernet frame padding.
#define KSZ8563_PHYCON
__start_packed struct @110 EthHeader
Ethernet frame header.
#define KSZ8563_SPI_CMD_WRITE
uint16_t ksz8563ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
#define TRUE
Definition: os_port.h:50
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define KSZ8563_PORTn_MSTP_STATE(port)
PHY driver.
Definition: nic.h:214
#define KSZ8563_PORT3_OP_CTRL0
#define KSZ8563_PORTn_ETH_PHY_REG(port, addr)
#define NET_INTERFACE_COUNT
Definition: net.h:109
void ksz8563DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
#define KSZ8563_SPI_CMD_READ
#define KSZ8563_PORTn_MSTP_STATE_LEARNING_DIS
const PhyDriver ksz8563PhyDriver
KSZ8563 Ethernet switch driver.
#define KSZ8563_TAIL_TAG_ENCODE(port)
void ksz8563WriteSwitchReg(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
NetInterface netInterface[NET_INTERFACE_COUNT]
Definition: net.c:76
#define KSZ8563_SWITCH_OP_SOFT_HARD_RESET
#define TRACE_INFO(...)
Definition: debug.h:94
error_t ksz8563Init(NetInterface *interface)
KSZ8563 Ethernet switch initialization.
Success.
Definition: error.h:44
void ksz8563WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
Ipv6Addr address
OsEvent netEvent
Definition: net.c:74
uint8_t ksz8563ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
#define TRACE_WARNING(...)
Definition: debug.h:84
unsigned int uint_t
Definition: compiler_port.h:45
#define KSZ8563_SPI_CMD_ADDR
error_t netBufferAppend(NetBuffer *dest, const void *src, size_t length)
Append data a multi-part buffer.
Definition: net_mem.c:586
void osReleaseMutex(OsMutex *mutex)
Release ownership of the specified mutex object.
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint8_t value[]
Definition: dtls_misc.h:143
#define KSZ8563_PORT1
#define KSZ8563_CHIP_ID1_DEFAULT
uint16_t port
Definition: dns_common.h:223
error_t ksz8563TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
#define KSZ8563_PHYCON_SPEED_10BT
OsMutex netMutex
Definition: net.c:72
#define KSZ8563_PORTn_XMII_CTRL1_RGMII_ID_EG
#define KSZ8563_TAIL_TAG_DECODE(tag)
#define KSZ8563_PHYCON_SPEED_100BTX
void ksz8563DisableIrq(NetInterface *interface)
Disable interrupts.
#define KSZ8563_CHIP_ID1
uint8_t length
Definition: dtls_misc.h:142
error_t ksz8563UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
#define KSZ8563_PHYCON_DUPLEX_STATUS
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
void osAcquireMutex(OsMutex *mutex)
Acquire ownership of the specified mutex object.
bool_t ksz8563GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void ksz8563EventHandler(NetInterface *interface)
KSZ8563 event handler.
#define TRACE_DEBUG(...)
Definition: debug.h:106