ksz8721_driver.h
Go to the documentation of this file.
1 /**
2  * @file ksz8721_driver.h
3  * @brief KSZ8721 Ethernet PHY transceiver
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _KSZ8721_DRIVER_H
30 #define _KSZ8721_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //PHY address
36 #ifndef KSZ8721_PHY_ADDR
37  #define KSZ8721_PHY_ADDR 1
38 #elif (KSZ8721_PHY_ADDR < 0 || KSZ8721_PHY_ADDR > 31)
39  #error KSZ8721_PHY_ADDR parameter is not valid
40 #endif
41 
42 //KSZ8721 registers
43 #define KSZ8721_PHY_REG_BMCR 0x00
44 #define KSZ8721_PHY_REG_BMSR 0x01
45 #define KSZ8721_PHY_REG_PHYIDR1 0x02
46 #define KSZ8721_PHY_REG_PHYIDR2 0x03
47 #define KSZ8721_PHY_REG_ANAR 0x04
48 #define KSZ8721_PHY_REG_ANLPAR 0x05
49 #define KSZ8721_PHY_REG_ANER 0x06
50 #define KSZ8721_PHY_REG_ANNPTR 0x07
51 #define KSZ8721_PHY_REG_LPNPAR 0x08
52 #define KSZ8721_PHY_REG_RECR 0x15
53 #define KSZ8721_PHY_REG_ICSR 0x1B
54 #define KSZ8721_PHY_REG_PHYCON 0x1F
55 
56 //BMCR register
57 #define BMCR_RESET (1 << 15)
58 #define BMCR_LOOPBACK (1 << 14)
59 #define BMCR_SPEED_SEL (1 << 13)
60 #define BMCR_AN_EN (1 << 12)
61 #define BMCR_POWER_DOWN (1 << 11)
62 #define BMCR_ISOLATE (1 << 10)
63 #define BMCR_RESTART_AN (1 << 9)
64 #define BMCR_DUPLEX_MODE (1 << 8)
65 #define BMCR_COL_TEST (1 << 7)
66 #define BMCR_TX_DIS (1 << 0)
67 
68 //BMSR register
69 #define BMSR_100BT4 (1 << 15)
70 #define BMSR_100BTX_FD (1 << 14)
71 #define BMSR_100BTX (1 << 13)
72 #define BMSR_10BT_FD (1 << 12)
73 #define BMSR_10BT (1 << 11)
74 #define BMSR_NO_PREAMBLE (1 << 6)
75 #define BMSR_AN_COMPLETE (1 << 5)
76 #define BMSR_REMOTE_FAULT (1 << 4)
77 #define BMSR_AN_ABLE (1 << 3)
78 #define BMSR_LINK_STATUS (1 << 2)
79 #define BMSR_JABBER_DETECT (1 << 1)
80 #define BMSR_EXTENDED_CAP (1 << 0)
81 
82 //ANAR register
83 #define ANAR_NEXT_PAGE (1 << 15)
84 #define ANAR_REMOTE_FAULT (1 << 13)
85 #define ANAR_PAUSE (1 << 10)
86 #define ANAR_100BT4 (1 << 9)
87 #define ANAR_100BTX_FD (1 << 8)
88 #define ANAR_100BTX (1 << 7)
89 #define ANAR_10BT_FD (1 << 6)
90 #define ANAR_10BT (1 << 5)
91 #define ANAR_SELECTOR4 (1 << 4)
92 #define ANAR_SELECTOR3 (1 << 3)
93 #define ANAR_SELECTOR2 (1 << 2)
94 #define ANAR_SELECTOR1 (1 << 1)
95 #define ANAR_SELECTOR0 (1 << 0)
96 
97 //ANLPAR register
98 #define ANLPAR_NEXT_PAGE (1 << 15)
99 #define ANLPAR_LP_ACK (1 << 14)
100 #define ANLPAR_REMOTE_FAULT (1 << 13)
101 #define ANLPAR_PAUSE1 (1 << 11)
102 #define ANLPAR_PAUSE0 (1 << 10)
103 #define ANLPAR_100BT4 (1 << 9)
104 #define ANLPAR_100BTX_FD (1 << 8)
105 #define ANLPAR_100BTX (1 << 7)
106 #define ANLPAR_10BT_FD (1 << 6)
107 #define ANLPAR_10BT (1 << 5)
108 #define ANLPAR_SELECTOR4 (1 << 4)
109 #define ANLPAR_SELECTOR3 (1 << 3)
110 #define ANLPAR_SELECTOR2 (1 << 2)
111 #define ANLPAR_SELECTOR1 (1 << 1)
112 #define ANLPAR_SELECTOR0 (1 << 0)
113 
114 //ANER register
115 #define ANER_PAR_DET_FAULT (1 << 4)
116 #define ANER_LP_NEXT_PAGE_ABLE (1 << 3)
117 #define ANER_NEXT_PAGE_ABLE (1 << 2)
118 #define ANER_PAGE_RECEIVED (1 << 1)
119 #define ANER_LP_AN_ABLE (1 << 0)
120 
121 //ANNPTR register
122 #define ANNPTR_NEXT_PAGE (1 << 15)
123 #define ANNPTR_MSG_PAGE (1 << 13)
124 #define ANNPTR_ACK2 (1 << 12)
125 #define ANNPTR_TOGGLE (1 << 11)
126 #define ANNPTR_MESSAGE10 (1 << 10)
127 #define ANNPTR_MESSAGE9 (1 << 9)
128 #define ANNPTR_MESSAGE8 (1 << 8)
129 #define ANNPTR_MESSAGE7 (1 << 7)
130 #define ANNPTR_MESSAGE6 (1 << 6)
131 #define ANNPTR_MESSAGE5 (1 << 5)
132 #define ANNPTR_MESSAGE4 (1 << 4)
133 #define ANNPTR_MESSAGE3 (1 << 3)
134 #define ANNPTR_MESSAGE2 (1 << 2)
135 #define ANNPTR_MESSAGE1 (1 << 1)
136 #define ANNPTR_MESSAGE0 (1 << 0)
137 
138 //ICSR register
139 #define ICSR_JABBER_IE (1 << 15)
140 #define ICSR_RECEIVE_ERROR_IE (1 << 14)
141 #define ICSR_PAGE_RECEIVED_IE (1 << 13)
142 #define ICSR_PAR_DET_FAULT_IE (1 << 12)
143 #define ICSR_LP_ACK_IE (1 << 11)
144 #define ICSR_LINK_DOWN_IE (1 << 10)
145 #define ICSR_REMOTE_FAULT_IE (1 << 9)
146 #define ICSR_LINK_UP_IE (1 << 8)
147 #define ICSR_JABBER_IF (1 << 7)
148 #define ICSR_RECEIVE_ERROR_IF (1 << 6)
149 #define ICSR_PAGE_RECEIVED_IF (1 << 5)
150 #define ICSR_PAR_DET_FAULT_IF (1 << 4)
151 #define ICSR_LP_ACK_IF (1 << 3)
152 #define ICSR_LINK_DOWN_IF (1 << 2)
153 #define ICSR_REMOTE_FAULT_IF (1 << 1)
154 #define ICSR_LINK_UP_IF (1 << 0)
155 
156 //PHYCON register
157 #define PHYCON_PAIR_SWAP_DIS (1 << 13)
158 #define PHYCON_ENERGY_DETECT (1 << 12)
159 #define PHYCON_FORCE_LINK (1 << 11)
160 #define PHYCON_POWER_SAVING (1 << 10)
161 #define PHYCON_INT_LEVEL (1 << 9)
162 #define PHYCON_JABBER_EN (1 << 8)
163 #define PHYCON_AN_COMPLETE (1 << 7)
164 #define PHYCON_PAUSE_EN (1 << 6)
165 #define PHYCON_ISOLATE (1 << 5)
166 #define PHYCON_OP_MODE2 (1 << 4)
167 #define PHYCON_OP_MODE1 (1 << 3)
168 #define PHYCON_OP_MODE0 (1 << 2)
169 #define PHYCON_SQE_TEST_EN (1 << 1)
170 #define PHYCON_SCRAMBLER_DIS (1 << 0)
171 
172 //Operation mode indication
173 #define PHYCON_OP_MODE_MASK (7 << 2)
174 #define PHYCON_OP_MODE_AN (0 << 2)
175 #define PHYCON_OP_MODE_10BT (1 << 2)
176 #define PHYCON_OP_MODE_100BTX (2 << 2)
177 #define PHYCON_OP_MODE_10BT_FD (5 << 2)
178 #define PHYCON_OP_MODE_100BTX_FD (6 << 2)
179 #define PHYCON_OP_MODE_ISOLATE (7 << 2)
180 
181 //C++ guard
182 #ifdef __cplusplus
183  extern "C" {
184 #endif
185 
186 //KSZ8721 Ethernet PHY driver
187 extern const PhyDriver ksz8721PhyDriver;
188 
189 //KSZ8721 related functions
190 error_t ksz8721Init(NetInterface *interface);
191 
192 void ksz8721Tick(NetInterface *interface);
193 
194 void ksz8721EnableIrq(NetInterface *interface);
195 void ksz8721DisableIrq(NetInterface *interface);
196 
197 void ksz8721EventHandler(NetInterface *interface);
198 
199 void ksz8721WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
200 uint16_t ksz8721ReadPhyReg(NetInterface *interface, uint8_t address);
201 
202 void ksz8721DumpPhyReg(NetInterface *interface);
203 
204 //C++ guard
205 #ifdef __cplusplus
206  }
207 #endif
208 
209 #endif
void ksz8721WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data)
Write PHY register.
error_t ksz8721Init(NetInterface *interface)
KSZ8721 PHY transceiver initialization.
void ksz8721EnableIrq(NetInterface *interface)
Enable interrupts.
uint16_t ksz8721ReadPhyReg(NetInterface *interface, uint8_t address)
Read PHY register.
void ksz8721Tick(NetInterface *interface)
KSZ8721 timer handler.
PHY driver.
Definition: nic.h:196
const PhyDriver ksz8721PhyDriver
KSZ8721 Ethernet PHY driver.
Ipv6Addr address
void ksz8721EventHandler(NetInterface *interface)
KSZ8721 event handler.
error_t
Error codes.
Definition: error.h:40
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
void ksz8721DumpPhyReg(NetInterface *interface)
Dump PHY registers for debugging purpose.
void ksz8721DisableIrq(NetInterface *interface)
Disable interrupts.
Network interface controller abstraction layer.