ksz8775_driver.h
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1 /**
2  * @file ksz8775_driver.h
3  * @brief KSZ8775 5-port Ethernet switch driver
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2024 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 2.4.0
29  **/
30 
31 #ifndef _KSZ8775_DRIVER_H
32 #define _KSZ8775_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Port identifiers
38 #define KSZ8775_PORT1 1
39 #define KSZ8775_PORT2 2
40 #define KSZ8775_PORT3 3
41 #define KSZ8775_PORT4 4
42 #define KSZ8775_PORT5 5
43 
44 //Port masks
45 #define KSZ8775_PORT_MASK 0x1F
46 #define KSZ8775_PORT1_MASK 0x01
47 #define KSZ8775_PORT2_MASK 0x02
48 #define KSZ8775_PORT3_MASK 0x04
49 #define KSZ8775_PORT4_MASK 0x08
50 #define KSZ8775_PORT5_MASK 0x10
51 
52 //SPI command byte
53 #define KSZ8775_SPI_CMD_WRITE 0x4000
54 #define KSZ8775_SPI_CMD_READ 0x6000
55 #define KSZ8775_SPI_CMD_ADDR 0x1FFE
56 
57 //Size of static and dynamic MAC tables
58 #define KSZ8775_STATIC_MAC_TABLE_SIZE 32
59 #define KSZ8775_DYNAMIC_MAC_TABLE_SIZE 1024
60 
61 //Tail tag rules (host to KSZ8775)
62 #define KSZ8775_TAIL_TAG_NORMAL_ADDR_LOOKUP 0x80
63 #define KSZ8775_TAIL_TAG_PORT_SEL 0x40
64 #define KSZ8775_TAIL_TAG_DEST_QUEUE 0x30
65 #define KSZ8775_TAIL_TAG_DEST_PORT4 0x08
66 #define KSZ8775_TAIL_TAG_DEST_PORT3 0x04
67 #define KSZ8775_TAIL_TAG_DEST_PORT2 0x02
68 #define KSZ8775_TAIL_TAG_DEST_PORT1 0x01
69 
70 //Tail tag rules (KSZ8775 to host)
71 #define KSZ8775_TAIL_TAG_SRC_PORT 0x03
72 
73 //KSZ8775 PHY registers
74 #define KSZ8775_BMCR 0x00
75 #define KSZ8775_BMSR 0x01
76 #define KSZ8775_PHYID1 0x02
77 #define KSZ8775_PHYID2 0x03
78 #define KSZ8775_ANAR 0x04
79 #define KSZ8775_ANLPAR 0x05
80 #define KSZ8775_LINKMD 0x1D
81 #define KSZ8775_PHYSCS 0x1F
82 
83 //KSZ8775 Switch registers
84 #define KSZ8775_CHIP_ID0 0x00
85 #define KSZ8775_CHIP_ID1 0x01
86 #define KSZ8775_GLOBAL_CTRL0 0x02
87 #define KSZ8775_GLOBAL_CTRL1 0x03
88 #define KSZ8775_GLOBAL_CTRL2 0x04
89 #define KSZ8775_GLOBAL_CTRL3 0x05
90 #define KSZ8775_GLOBAL_CTRL4 0x06
91 #define KSZ8775_GLOBAL_CTRL5 0x07
92 #define KSZ8775_GLOBAL_CTRL6_MIB_CTRL 0x08
93 #define KSZ8775_GLOBAL_CTRL7 0x09
94 #define KSZ8775_GLOBAL_CTRL8 0x0A
95 #define KSZ8775_GLOBAL_CTRL9 0x0B
96 #define KSZ8775_GLOBAL_CTRL10 0x0C
97 #define KSZ8775_GLOBAL_CTRL11 0x0D
98 #define KSZ8775_PD_MGMT_CTRL1 0x0E
99 #define KSZ8775_PD_MGMT_CTRL2 0x0F
100 #define KSZ8775_PORT1_CTRL0 0x10
101 #define KSZ8775_PORT1_CTRL1 0x11
102 #define KSZ8775_PORT1_CTRL2 0x12
103 #define KSZ8775_PORT1_CTRL3 0x13
104 #define KSZ8775_PORT1_CTRL4 0x14
105 #define KSZ8775_PORT1_CTRL5 0x15
106 #define KSZ8775_PORT1_CTRL7 0x17
107 #define KSZ8775_PORT1_STAT0 0x18
108 #define KSZ8775_PORT1_STAT1 0x19
109 #define KSZ8775_PORT1_PHY_CTRL8 0x1A
110 #define KSZ8775_PORT1_LINKMD 0x1B
111 #define KSZ8775_PORT1_CTRL9 0x1C
112 #define KSZ8775_PORT1_CTRL10 0x1D
113 #define KSZ8775_PORT1_STAT2 0x1E
114 #define KSZ8775_PORT1_CTRL11_STAT3 0x1F
115 #define KSZ8775_PORT2_CTRL0 0x20
116 #define KSZ8775_PORT2_CTRL1 0x21
117 #define KSZ8775_PORT2_CTRL2 0x22
118 #define KSZ8775_PORT2_CTRL3 0x23
119 #define KSZ8775_PORT2_CTRL4 0x24
120 #define KSZ8775_PORT2_CTRL5 0x25
121 #define KSZ8775_PORT2_CTRL7 0x27
122 #define KSZ8775_PORT2_STAT0 0x28
123 #define KSZ8775_PORT2_STAT1 0x29
124 #define KSZ8775_PORT2_PHY_CTRL8 0x2A
125 #define KSZ8775_PORT2_LINKMD 0x2B
126 #define KSZ8775_PORT2_CTRL9 0x2C
127 #define KSZ8775_PORT2_CTRL10 0x2D
128 #define KSZ8775_PORT2_STAT2 0x2E
129 #define KSZ8775_PORT2_CTRL11_STAT3 0x2F
130 #define KSZ8775_PORT3_CTRL0 0x30
131 #define KSZ8775_PORT3_CTRL1 0x31
132 #define KSZ8775_PORT3_CTRL2 0x32
133 #define KSZ8775_PORT3_CTRL3 0x33
134 #define KSZ8775_PORT3_CTRL4 0x34
135 #define KSZ8775_PORT3_CTRL5 0x35
136 #define KSZ8775_PORT3_CTRL7 0x37
137 #define KSZ8775_PORT3_STAT0 0x38
138 #define KSZ8775_PORT3_STAT1 0x39
139 #define KSZ8775_PORT3_PHY_CTRL8 0x3A
140 #define KSZ8775_PORT3_LINKMD 0x3B
141 #define KSZ8775_PORT3_CTRL9 0x3C
142 #define KSZ8775_PORT3_CTRL10 0x3D
143 #define KSZ8775_PORT3_STAT2 0x3E
144 #define KSZ8775_PORT3_CTRL11_STAT3 0x3F
145 #define KSZ8775_PORT4_CTRL0 0x40
146 #define KSZ8775_PORT4_CTRL1 0x41
147 #define KSZ8775_PORT4_CTRL2 0x42
148 #define KSZ8775_PORT4_CTRL3 0x43
149 #define KSZ8775_PORT4_CTRL4 0x44
150 #define KSZ8775_PORT4_CTRL5 0x45
151 #define KSZ8775_PORT4_IF_CTRL6 0x46
152 #define KSZ8775_PORT4_CTRL9 0x4C
153 #define KSZ8775_PORT5_CTRL0 0x50
154 #define KSZ8775_PORT5_CTRL1 0x51
155 #define KSZ8775_PORT5_CTRL2 0x52
156 #define KSZ8775_PORT5_CTRL3 0x53
157 #define KSZ8775_PORT5_CTRL4 0x54
158 #define KSZ8775_PORT5_CTRL5 0x55
159 #define KSZ8775_PORT5_IF_CTRL6 0x56
160 #define KSZ8775_MAC_ADDR0 0x68
161 #define KSZ8775_MAC_ADDR1 0x69
162 #define KSZ8775_MAC_ADDR2 0x6A
163 #define KSZ8775_MAC_ADDR3 0x6B
164 #define KSZ8775_MAC_ADDR4 0x6C
165 #define KSZ8775_MAC_ADDR5 0x6D
166 #define KSZ8775_INDIRECT_CTRL0 0x6E
167 #define KSZ8775_INDIRECT_CTRL1 0x6F
168 #define KSZ8775_INDIRECT_DATA8 0x70
169 #define KSZ8775_INDIRECT_DATA7 0x71
170 #define KSZ8775_INDIRECT_DATA6 0x72
171 #define KSZ8775_INDIRECT_DATA5 0x73
172 #define KSZ8775_INDIRECT_DATA4 0x74
173 #define KSZ8775_INDIRECT_DATA3 0x75
174 #define KSZ8775_INDIRECT_DATA2 0x76
175 #define KSZ8775_INDIRECT_DATA1 0x77
176 #define KSZ8775_INDIRECT_DATA0 0x78
177 #define KSZ8775_INT_STAT 0x7C
178 #define KSZ8775_INT_MASK 0x7D
179 #define KSZ8775_ACL_INT_STAT 0x7E
180 #define KSZ8775_ACL_INT_CTRL 0x7F
181 #define KSZ8775_GLOBAL_CTRL12 0x80
182 #define KSZ8775_GLOBAL_CTRL13 0x81
183 #define KSZ8775_GLOBAL_CTRL14 0x82
184 #define KSZ8775_GLOBAL_CTRL15 0x83
185 #define KSZ8775_GLOBAL_CTRL16 0x84
186 #define KSZ8775_GLOBAL_CTRL17 0x85
187 #define KSZ8775_GLOBAL_CTRL18 0x86
188 #define KSZ8775_GLOBAL_CTRL19 0x87
189 #define KSZ8775_TOS_PRIO_CTRL0 0x90
190 #define KSZ8775_TOS_PRIO_CTRL1 0x91
191 #define KSZ8775_TOS_PRIO_CTRL2 0x92
192 #define KSZ8775_TOS_PRIO_CTRL3 0x93
193 #define KSZ8775_TOS_PRIO_CTRL4 0x94
194 #define KSZ8775_TOS_PRIO_CTRL5 0x95
195 #define KSZ8775_TOS_PRIO_CTRL6 0x96
196 #define KSZ8775_TOS_PRIO_CTRL7 0x97
197 #define KSZ8775_TOS_PRIO_CTRL8 0x98
198 #define KSZ8775_TOS_PRIO_CTRL9 0x99
199 #define KSZ8775_TOS_PRIO_CTRL10 0x9A
200 #define KSZ8775_TOS_PRIO_CTRL11 0x9B
201 #define KSZ8775_TOS_PRIO_CTRL12 0x9C
202 #define KSZ8775_TOS_PRIO_CTRL13 0x9D
203 #define KSZ8775_TOS_PRIO_CTRL14 0x9E
204 #define KSZ8775_TOS_PRIO_CTRL15 0x9F
205 #define KSZ8775_INDIRECT_BYTE 0xA0
206 #define KSZ8775_GLOBAL_CTRL20 0xA3
207 #define KSZ8775_GLOBAL_CTRL21 0xA4
208 #define KSZ8775_PORT1_CTRL12 0xB0
209 #define KSZ8775_PORT1_CTRL13 0xB1
210 #define KSZ8775_PORT1_CTRL14 0xB2
211 #define KSZ8775_PORT1_CTRL15 0xB3
212 #define KSZ8775_PORT1_CTRL16 0xB4
213 #define KSZ8775_PORT1_CTRL17 0xB5
214 #define KSZ8775_PORT1_RATE_LIMIT_CTRL 0xB6
215 #define KSZ8775_PORT1_PRIO0_IG_LIMIT_CTRL1 0xB7
216 #define KSZ8775_PORT1_PRIO1_IG_LIMIT_CTRL2 0xB8
217 #define KSZ8775_PORT1_PRIO2_IG_LIMIT_CTRL3 0xB9
218 #define KSZ8775_PORT1_PRIO3_IG_LIMIT_CTRL4 0xBA
219 #define KSZ8775_PORT1_QUEUE0_EG_LIMIT_CTRL1 0xBB
220 #define KSZ8775_PORT1_QUEUE1_EG_LIMIT_CTRL2 0xBC
221 #define KSZ8775_PORT1_QUEUE2_EG_LIMIT_CTRL3 0xBD
222 #define KSZ8775_PORT1_QUEUE3_EG_LIMIT_CTRL4 0xBE
223 #define KSZ8775_TEST 0xBF
224 #define KSZ8775_PORT2_CTRL12 0xC0
225 #define KSZ8775_PORT2_CTRL13 0xC1
226 #define KSZ8775_PORT2_CTRL14 0xC2
227 #define KSZ8775_PORT2_CTRL15 0xC3
228 #define KSZ8775_PORT2_CTRL16 0xC4
229 #define KSZ8775_PORT2_CTRL17 0xC5
230 #define KSZ8775_PORT2_RATE_LIMIT_CTRL 0xC6
231 #define KSZ8775_PORT2_PRIO0_IG_LIMIT_CTRL1 0xC7
232 #define KSZ8775_PORT2_PRIO1_IG_LIMIT_CTRL2 0xC8
233 #define KSZ8775_PORT2_PRIO2_IG_LIMIT_CTRL3 0xC9
234 #define KSZ8775_PORT2_PRIO3_IG_LIMIT_CTRL4 0xCA
235 #define KSZ8775_PORT2_QUEUE0_EG_LIMIT_CTRL1 0xCB
236 #define KSZ8775_PORT2_QUEUE1_EG_LIMIT_CTRL2 0xCC
237 #define KSZ8775_PORT2_QUEUE2_EG_LIMIT_CTRL3 0xCD
238 #define KSZ8775_PORT2_QUEUE3_EG_LIMIT_CTRL4 0xCE
239 #define KSZ8775_PORT3_CTRL12 0xD0
240 #define KSZ8775_PORT3_CTRL13 0xD1
241 #define KSZ8775_PORT3_CTRL14 0xD2
242 #define KSZ8775_PORT3_CTRL15 0xD3
243 #define KSZ8775_PORT3_CTRL16 0xD4
244 #define KSZ8775_PORT3_CTRL17 0xD5
245 #define KSZ8775_PORT3_RATE_LIMIT_CTRL 0xD6
246 #define KSZ8775_PORT3_PRIO0_IG_LIMIT_CTRL1 0xD7
247 #define KSZ8775_PORT3_PRIO1_IG_LIMIT_CTRL2 0xD8
248 #define KSZ8775_PORT3_PRIO2_IG_LIMIT_CTRL3 0xD9
249 #define KSZ8775_PORT3_PRIO3_IG_LIMIT_CTRL4 0xDA
250 #define KSZ8775_PORT3_QUEUE0_EG_LIMIT_CTRL1 0xDB
251 #define KSZ8775_PORT3_QUEUE1_EG_LIMIT_CTRL2 0xDC
252 #define KSZ8775_PORT3_QUEUE2_EG_LIMIT_CTRL3 0xDD
253 #define KSZ8775_PORT3_QUEUE3_EG_LIMIT_CTRL4 0xDE
254 #define KSZ8775_TEST2 0xDF
255 #define KSZ8775_PORT4_CTRL12 0xE0
256 #define KSZ8775_PORT4_CTRL13 0xE1
257 #define KSZ8775_PORT4_CTRL14 0xE2
258 #define KSZ8775_PORT4_CTRL15 0xE3
259 #define KSZ8775_PORT4_CTRL16 0xE4
260 #define KSZ8775_PORT4_CTRL17 0xE5
261 #define KSZ8775_PORT4_RATE_LIMIT_CTRL 0xE6
262 #define KSZ8775_PORT4_PRIO0_IG_LIMIT_CTRL1 0xE7
263 #define KSZ8775_PORT4_PRIO1_IG_LIMIT_CTRL2 0xE8
264 #define KSZ8775_PORT4_PRIO2_IG_LIMIT_CTRL3 0xE9
265 #define KSZ8775_PORT4_PRIO3_IG_LIMIT_CTRL4 0xEA
266 #define KSZ8775_PORT4_QUEUE0_EG_LIMIT_CTRL1 0xEB
267 #define KSZ8775_PORT4_QUEUE1_EG_LIMIT_CTRL2 0xEC
268 #define KSZ8775_PORT4_QUEUE2_EG_LIMIT_CTRL3 0xED
269 #define KSZ8775_PORT4_QUEUE3_EG_LIMIT_CTRL4 0xEE
270 #define KSZ8775_TEST3 0xEF
271 #define KSZ8775_PORT5_CTRL13 0xF1
272 #define KSZ8775_PORT5_CTRL14 0xF2
273 #define KSZ8775_PORT5_CTRL15 0xF3
274 #define KSZ8775_PORT5_CTRL16 0xF4
275 #define KSZ8775_PORT5_CTRL17 0xF5
276 #define KSZ8775_PORT5_RATE_LIMIT_CTRL 0xF6
277 #define KSZ8775_PORT5_PRIO0_IG_LIMIT_CTRL1 0xF7
278 #define KSZ8775_PORT5_PRIO1_IG_LIMIT_CTRL2 0xF8
279 #define KSZ8775_PORT5_PRIO2_IG_LIMIT_CTRL3 0xF9
280 #define KSZ8775_PORT5_PRIO3_IG_LIMIT_CTRL4 0xFA
281 #define KSZ8775_PORT5_QUEUE0_EG_LIMIT_CTRL1 0xFB
282 #define KSZ8775_PORT5_QUEUE1_EG_LIMIT_CTRL2 0xFC
283 #define KSZ8775_PORT5_QUEUE2_EG_LIMIT_CTRL3 0xFD
284 #define KSZ8775_PORT5_QUEUE3_EG_LIMIT_CTRL4 0xFE
285 #define KSZ8775_TEST4 0xFF
286 
287 //KSZ8775 Switch register access macros
288 #define KSZ8775_PORTn_CTRL0(port) (0x00 + ((port) * 0x10))
289 #define KSZ8775_PORTn_CTRL1(port) (0x01 + ((port) * 0x10))
290 #define KSZ8775_PORTn_CTRL2(port) (0x02 + ((port) * 0x10))
291 #define KSZ8775_PORTn_CTRL3(port) (0x03 + ((port) * 0x10))
292 #define KSZ8775_PORTn_CTRL4(port) (0x04 + ((port) * 0x10))
293 #define KSZ8775_PORTn_CTRL5(port) (0x05 + ((port) * 0x10))
294 #define KSZ8775_PORTn_IF_CTRL6(port) (0x06 + ((port) * 0x10))
295 #define KSZ8775_PORTn_CTRL7(port) (0x07 + ((port) * 0x10))
296 #define KSZ8775_PORTn_STAT0(port) (0x08 + ((port) * 0x10))
297 #define KSZ8775_PORTn_STAT1(port) (0x09 + ((port) * 0x10))
298 #define KSZ8775_PORTn_PHY_CTRL8(port) (0x0A + ((port) * 0x10))
299 #define KSZ8775_PORTn_LINKMD(port) (0x0B + ((port) * 0x10))
300 #define KSZ8775_PORTn_CTRL9(port) (0x0C + ((port) * 0x10))
301 #define KSZ8775_PORTn_CTRL10(port) (0x0D + ((port) * 0x10))
302 #define KSZ8775_PORTn_STAT2(port) (0x0E + ((port) * 0x10))
303 #define KSZ8775_PORTn_CTRL11_STAT3(port) (0x0F + ((port) * 0x10))
304 #define KSZ8775_PORTn_CTRL12(port) (0xA0 + ((port) * 0x10))
305 #define KSZ8775_PORTn_CTRL13(port) (0xA1 + ((port) * 0x10))
306 #define KSZ8775_PORTn_CTRL14(port) (0xA2 + ((port) * 0x10))
307 #define KSZ8775_PORTn_CTRL15(port) (0xA3 + ((port) * 0x10))
308 #define KSZ8775_PORTn_CTRL16(port) (0xA4 + ((port) * 0x10))
309 #define KSZ8775_PORTn_CTRL17(port) (0xA5 + ((port) * 0x10))
310 #define KSZ8775_PORTn_RATE_LIMIT_CTRL(port) (0xA6 + ((port) * 0x10))
311 #define KSZ8775_PORTn_PRIO0_IG_LIMIT_CTRL1(port) (0xA7 + ((port) * 0x10))
312 #define KSZ8775_PORTn_PRIO1_IG_LIMIT_CTRL2(port) (0xA8 + ((port) * 0x10))
313 #define KSZ8775_PORTn_PRIO2_IG_LIMIT_CTRL3(port) (0xA9 + ((port) * 0x10))
314 #define KSZ8775_PORTn_PRIO3_IG_LIMIT_CTRL4(port) (0xAA + ((port) * 0x10))
315 #define KSZ8775_PORTn_QUEUE0_EG_LIMIT_CTRL1(port) (0xAB + ((port) * 0x10))
316 #define KSZ8775_PORTn_QUEUE1_EG_LIMIT_CTRL2(port) (0xAC + ((port) * 0x10))
317 #define KSZ8775_PORTn_QUEUE2_EG_LIMIT_CTRL3(port) (0xAD + ((port) * 0x10))
318 #define KSZ8775_PORTn_QUEUE3_EG_LIMIT_CTRL4(port) (0xAE + ((port) * 0x10))
319 
320 //Basic Control register
321 #define KSZ8775_BMCR_RESET 0x8000
322 #define KSZ8775_BMCR_LOOPBACK 0x4000
323 #define KSZ8775_BMCR_FORCE_100 0x2000
324 #define KSZ8775_BMCR_AN_EN 0x1000
325 #define KSZ8775_BMCR_POWER_DOWN 0x0800
326 #define KSZ8775_BMCR_ISOLATE 0x0400
327 #define KSZ8775_BMCR_RESTART_AN 0x0200
328 #define KSZ8775_BMCR_FORCE_FULL_DUPLEX 0x0100
329 #define KSZ8775_BMCR_HP_MDIX 0x0020
330 #define KSZ8775_BMCR_FORCE_MDI 0x0010
331 #define KSZ8775_BMCR_AUTO_MDIX_DIS 0x0008
332 #define KSZ8775_BMCR_FAR_END_FAULT_DIS 0x0004
333 #define KSZ8775_BMCR_TRANSMIT_DIS 0x0002
334 #define KSZ8775_BMCR_LED_DIS 0x0001
335 
336 //Basic Status register
337 #define KSZ8775_BMSR_100BT4 0x8000
338 #define KSZ8775_BMSR_100BTX_FD 0x4000
339 #define KSZ8775_BMSR_100BTX_HD 0x2000
340 #define KSZ8775_BMSR_10BT_FD 0x1000
341 #define KSZ8775_BMSR_10BT_HD 0x0800
342 #define KSZ8775_BMSR_AN_COMPLETE 0x0020
343 #define KSZ8775_BMSR_FAR_END_FAULT 0x0010
344 #define KSZ8775_BMSR_AN_CAPABLE 0x0008
345 #define KSZ8775_BMSR_LINK_STATUS 0x0004
346 #define KSZ8775_BMSR_EXTENDED_CAPABLE 0x0001
347 
348 //PHYID High register
349 #define KSZ8775_PHYID1_DEFAULT 0x0022
350 
351 //PHYID Low register
352 #define KSZ8775_PHYID2_DEFAULT 0x1550
353 
354 //Advertisement Ability register
355 #define KSZ8775_ANAR_PAUSE 0x0400
356 #define KSZ8775_ANAR_100BTX_FD 0x0100
357 #define KSZ8775_ANAR_100BTX_HD 0x0080
358 #define KSZ8775_ANAR_10BT_FD 0x0040
359 #define KSZ8775_ANAR_10BT_HD 0x0020
360 #define KSZ8775_ANAR_SELECTOR 0x001F
361 #define KSZ8775_ANAR_SELECTOR_DEFAULT 0x0001
362 
363 //Link Partner Ability register
364 #define KSZ8775_ANLPAR_PAUSE 0x0400
365 #define KSZ8775_ANLPAR_100BTX_FD 0x0100
366 #define KSZ8775_ANLPAR_100BTX_HD 0x0080
367 #define KSZ8775_ANLPAR_10BT_FD 0x0040
368 #define KSZ8775_ANLPAR_10BT_HD 0x0020
369 
370 //LinkMD Control/Status register
371 #define KSZ8775_LINKMD_TEST_EN 0x8000
372 #define KSZ8775_LINKMD_RESULT 0x6000
373 #define KSZ8775_LINKMD_SHORT 0x1000
374 #define KSZ8775_LINKMD_FAULT_COUNT 0x01FF
375 
376 //PHY Special Control/Status register
377 #define KSZ8775_PHYSCS_OP_MODE 0x0700
378 #define KSZ8775_PHYSCS_OP_MODE_AN 0x0100
379 #define KSZ8775_PHYSCS_OP_MODE_10BT_HD 0x0200
380 #define KSZ8775_PHYSCS_OP_MODE_100BTX_HD 0x0300
381 #define KSZ8775_PHYSCS_OP_MODE_10BT_FD 0x0500
382 #define KSZ8775_PHYSCS_OP_MODE_100BTX_FD 0x0600
383 #define KSZ8775_PHYSCS_OP_MODE_ISOLATE 0x0700
384 #define KSZ8775_PHYSCS_POLRVS 0x0020
385 #define KSZ8775_PHYSCS_MDIX_STATUS 0x0010
386 #define KSZ8775_PHYSCS_FORCE_LINK 0x0008
387 #define KSZ8775_PHYSCS_PWRSAVE 0x0004
388 #define KSZ8775_PHYSCS_REMOTE_LOOPBACK 0x0002
389 
390 //Chip ID0 register
391 #define KSZ8775_CHIP_ID0_FAMILY_ID 0xFF
392 #define KSZ8775_CHIP_ID0_FAMILY_ID_DEFAULT 0x87
393 
394 //Chip ID1 / Start Switch register
395 #define KSZ8775_CHIP_ID1_CHIP_ID 0xF0
396 #define KSZ8775_CHIP_ID1_CHIP_ID_DEFAULT 0x70
397 #define KSZ8775_CHIP_ID1_REVISION_ID 0x0E
398 #define KSZ8775_CHIP_ID1_START_SWITCH 0x01
399 
400 //Global Control 0 register
401 #define KSZ8775_GLOBAL_CTRL0_NEW_BACK_OFF_EN 0x80
402 #define KSZ8775_GLOBAL_CTRL0_GLOBAL_SOFT_RESET_EN 0x40
403 #define KSZ8775_GLOBAL_CTRL0_FLUSH_DYNAMIC_MAC_TABLE 0x20
404 #define KSZ8775_GLOBAL_CTRL0_FLUSH_STATIC_MAC_TABLE 0x10
405 #define KSZ8775_GLOBAL_CTRL0_UNH_MODE 0x02
406 #define KSZ8775_GLOBAL_CTRL0_LINK_CHANGE_AGE 0x01
407 
408 //Global Control 1 register
409 #define KSZ8775_GLOBAL_CTRL1_2KB_PKT_SUPPORT 0x40
410 #define KSZ8775_GLOBAL_CTRL1_TX_FLOW_CTRL_DIS 0x20
411 #define KSZ8775_GLOBAL_CTRL1_RX_FLOW_CTRL_DIS 0x10
412 #define KSZ8775_GLOBAL_CTRL1_FRAME_LEN_CHECK_EN 0x08
413 #define KSZ8775_GLOBAL_CTRL1_AGING_EN 0x04
414 #define KSZ8775_GLOBAL_CTRL1_FAST_AGE_EN 0x02
415 #define KSZ8775_GLOBAL_CTRL1_AGGRESSIVE_BACK_OFF_EN 0x01
416 
417 //Global Control 2 register
418 #define KSZ8775_GLOBAL_CTRL2_UNI_VLAN_MISMATCH_DISCARD 0x80
419 #define KSZ8775_GLOBAL_CTRL2_MCAST_STORM_PROTECT_DIS 0x40
420 #define KSZ8775_GLOBAL_CTRL2_BACK_PRESSURE_MODE 0x20
421 #define KSZ8775_GLOBAL_CTRL2_FLOW_CTRL_FAIR_MODE 0x10
422 #define KSZ8775_GLOBAL_CTRL2_NO_EXCESSIVE_COL_DROP 0x08
423 #define KSZ8775_GLOBAL_CTRL2_MAX_PKT_SIZE_CHECK_DIS 0x02
424 
425 //Global Control 3 register
426 #define KSZ8775_GLOBAL_CTRL3_VLAN_EN 0x80
427 #define KSZ8775_GLOBAL_CTRL3_SW5_IGMP_SNOOP_EN 0x40
428 #define KSZ8775_GLOBAL_CTRL3_SNIFF_MODE_SEL 0x01
429 
430 //Global Control 4 register
431 #define KSZ8775_GLOBAL_CTRL4_SW5_BACK_PRESSURE_EN 0x80
432 #define KSZ8775_GLOBAL_CTRL4_SW5_HALF_DUPLEX_MODE 0x40
433 #define KSZ8775_GLOBAL_CTRL4_SW5_FLOW_CTRL_EN 0x20
434 #define KSZ8775_GLOBAL_CTRL4_SW5_SPEED 0x10
435 #define KSZ8775_GLOBAL_CTRL4_NULL_VID_REPLACEMENT 0x08
436 #define KSZ8775_GLOBAL_CTRL4_BCAST_STORM_PROTECT_RATE_MSB 0x07
437 
438 //Global Control 5 register
439 #define KSZ8775_GLOBAL_CTRL5_BCAST_STORM_PROTECT_RATE_LSB 0xFF
440 
441 //Global Control 6 MIB Control register
442 #define KSZ8775_GLOBAL_CTRL6_MIB_CTRL_FLUSH_COUNTER 0x80
443 #define KSZ8775_GLOBAL_CTRL6_MIB_CTRL_FREEZE_COUNTER 0x40
444 #define KSZ8775_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN 0x1F
445 #define KSZ8775_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN_PORT1 0x01
446 #define KSZ8775_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN_PORT2 0x02
447 #define KSZ8775_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN_PORT3 0x04
448 #define KSZ8775_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN_PORT4 0x08
449 #define KSZ8775_GLOBAL_CTRL6_MIB_CTRL_CONTROL_EN_PORT5 0x10
450 
451 //Global Control 7 register
452 #define KSZ8775_GLOBAL_CTRL7_FACTORY_TESTING 0xFF
453 
454 //Global Control 8 register
455 #define KSZ8775_GLOBAL_CTRL8_FACTORY_TESTING 0xFF
456 
457 //Global Control 9 register
458 #define KSZ8775_GLOBAL_CTRL9_SW5_REFCLK_EDGE_SEL 0x40
459 #define KSZ8775_GLOBAL_CTRL9_SW5_REFCLK_EDGE_SEL_RISING 0x00
460 #define KSZ8775_GLOBAL_CTRL9_SW5_REFCLK_EDGE_SEL_FALLING 0x40
461 #define KSZ8775_GLOBAL_CTRL9_LED_MODE 0x30
462 #define KSZ8775_GLOBAL_CTRL9_LED_MODE_LED0_LNK_ACT_LED1_SPD 0x00
463 #define KSZ8775_GLOBAL_CTRL9_LED_MODE_LED0_LNK_LED1_ACT 0x10
464 #define KSZ8775_GLOBAL_CTRL9_LED_MODE_LED0_LNK_ACT_LED1_DPLX 0x20
465 #define KSZ8775_GLOBAL_CTRL9_LED_MODE_LED0_LNK_LED1_ACT_DPLX 0x30
466 #define KSZ8775_GLOBAL_CTRL9_REFCLKO_ENABLE 0x02
467 #define KSZ8775_GLOBAL_CTRL9_SPI_READ_CLK_EDGE_SEL 0x01
468 #define KSZ8775_GLOBAL_CTRL9_SPI_READ_CLK_EDGE_SEL_FALLING 0x00
469 #define KSZ8775_GLOBAL_CTRL9_SPI_READ_CLK_EDGE_SEL_RISING 0x01
470 
471 //Global Control 10 register
472 #define KSZ8775_GLOBAL_CTRL10_TAIL_TAG_EN 0x02
473 
474 //Global Control 11 register
475 #define KSZ8775_GLOBAL_CTRL11_FACTORY_TESTING 0xFF
476 
477 //Power-Down Management Control 1 register
478 #define KSZ8775_PD_MGMT_CTRL1_PLL_PWR_DOWN 0x20
479 #define KSZ8775_PD_MGMT_CTRL1_PWR_MGMT_MODE 0x18
480 #define KSZ8775_PD_MGMT_CTRL1_PWR_MGMT_MODE_NORMAL 0x00
481 #define KSZ8775_PD_MGMT_CTRL1_PWR_MGMT_MODE_ENERGY_DETECT 0x08
482 #define KSZ8775_PD_MGMT_CTRL1_PWR_MGMT_MODE_SOFT_PWR_DOWN 0x10
483 
484 //Power-Down Management Control 2 register
485 #define KSZ8775_PD_MGMT_CTRL2_GO_SLEEP_TIME 0xFF
486 
487 //Port N Control 0 register
488 #define KSZ8775_PORTn_CTRL0_BCAST_STORM_PROTECT_EN 0x80
489 #define KSZ8775_PORTn_CTRL0_DIFFSERV_PRIO_CLASS_EN 0x40
490 #define KSZ8775_PORTn_CTRL0_802_1P_PRIO_CLASS_EN 0x20
491 #define KSZ8775_PORTn_CTRL0_PORT_PRIO_CLASS_EN 0x18
492 #define KSZ8775_PORTn_CTRL0_TAG_INSERTION 0x04
493 #define KSZ8775_PORTn_CTRL0_TAG_REMOVAL 0x02
494 #define KSZ8775_PORTn_CTRL0_TWO_QUEUE_SPLIT_EN 0x01
495 
496 //Port N Control 1 register
497 #define KSZ8775_PORTn_CTRL1_SNIFFER_PORT 0x80
498 #define KSZ8775_PORTn_CTRL1_RECEIVE_SNIFF 0x40
499 #define KSZ8775_PORTn_CTRL1_TRANSMIT_SNIFF 0x20
500 #define KSZ8775_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x1F
501 
502 //Port N Control 2 register
503 #define KSZ8775_PORTn_CTRL2_USER_PRIO_CEILING 0x80
504 #define KSZ8775_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
505 #define KSZ8775_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
506 #define KSZ8775_PORTn_CTRL2_FORCE_FLOW_CTRL 0x10
507 #define KSZ8775_PORTn_CTRL2_BACK_PRESSURE_EN 0x08
508 #define KSZ8775_PORTn_CTRL2_TRANSMIT_EN 0x04
509 #define KSZ8775_PORTn_CTRL2_RECEIVE_EN 0x02
510 #define KSZ8775_PORTn_CTRL2_LEARNING_DIS 0x01
511 
512 //Port N Control 3 register
513 #define KSZ8775_PORTn_CTRL3_DEFAULT_USER_PRIO 0xE0
514 #define KSZ8775_PORTn_CTRL3_DEFAULT_CFI 0x10
515 #define KSZ8775_PORTn_CTRL3_DEFAULT_VID_MSB 0x0F
516 
517 //Port N Control 4 register
518 #define KSZ8775_PORTn_CTRL4_DEFAULT_VID_LSB 0xFF
519 
520 //Port N Interface Control 6 register
521 #define KSZ8775_PORTn_IF_CTRL6_RMII_CLK_SEL 0x80
522 #define KSZ8775_PORTn_IF_CTRL6_IS_1GBPS 0x40
523 #define KSZ8775_PORTn_IF_CTRL6_RGMII_ID_IG_EN 0x10
524 #define KSZ8775_PORTn_IF_CTRL6_RGMII_ID_EG_EN 0x08
525 #define KSZ8775_PORTn_IF_CTRL6_MII_MODE_SEL 0x04
526 #define KSZ8775_PORTn_IF_CTRL6_MII_MODE_SEL_PHY 0x00
527 #define KSZ8775_PORTn_IF_CTRL6_MII_MODE_SEL_MAC 0x04
528 #define KSZ8775_PORTn_IF_CTRL6_IF_MODE_SEL 0x03
529 #define KSZ8775_PORTn_IF_CTRL6_IF_MODE_SEL_MII 0x00
530 #define KSZ8775_PORTn_IF_CTRL6_IF_MODE_SEL_RMII 0x01
531 #define KSZ8775_PORTn_IF_CTRL6_IF_MODE_SEL_RGMII 0x03
532 
533 //Port N Status 0 register
534 #define KSZ8775_PORTn_STAT0_LP_FLOW_CTRL_CAPABLE 0x30
535 #define KSZ8775_PORTn_STAT0_LP_100BTX_FD_CAPABLE 0x08
536 #define KSZ8775_PORTn_STAT0_LP_100BTX_HF_CAPABLE 0x04
537 #define KSZ8775_PORTn_STAT0_LP_10BT_FD_CAPABLE 0x02
538 #define KSZ8775_PORTn_STAT0_LP_10BT_HD_CAPABLE 0x01
539 
540 //Port N Status 1 register
541 #define KSZ8775_PORTn_STAT1_HP_MDIX 0x80
542 #define KSZ8775_PORTn_STAT1_FACTORY_TESTING 0x40
543 #define KSZ8775_PORTn_STAT1_POLRVS 0x20
544 #define KSZ8775_PORTn_STAT1_TX_FLOW_CTRL_EN 0x10
545 #define KSZ8775_PORTn_STAT1_RX_FLOW_CTRL_EN 0x08
546 #define KSZ8775_PORTn_STAT1_OP_SPEED 0x04
547 #define KSZ8775_PORTn_STAT1_OP_DUPLEX 0x02
548 
549 //Port N Control 9 register
550 #define KSZ8775_PORTn_CTRL9_AN_DIS 0x80
551 #define KSZ8775_PORTn_CTRL9_FORCED_SPEED 0x40
552 #define KSZ8775_PORTn_CTRL9_FORCED_DUPLEX 0x20
553 
554 //Port N Control 10 register
555 #define KSZ8775_PORTn_CTRL10_LED_OFF 0x80
556 #define KSZ8775_PORTn_CTRL10_TX_DIS 0x40
557 #define KSZ8775_PORTn_CTRL10_RESTART_AN 0x20
558 #define KSZ8775_PORTn_CTRL10_POWER_DOWN 0x08
559 #define KSZ8775_PORTn_CTRL10_AUTO_MDIX_DIS 0x04
560 #define KSZ8775_PORTn_CTRL10_FORCED_MDI 0x02
561 #define KSZ8775_PORTn_CTRL10_MAC_LOOPBACK 0x01
562 
563 //Port N Status 2 register
564 #define KSZ8775_PORTn_STAT2_MDIX_STATUS 0x80
565 #define KSZ8775_PORTn_STAT2_AN_DONE 0x40
566 #define KSZ8775_PORTn_STAT2_LINK_GOOD 0x20
567 
568 //Port N Control 11 / Status 3 register
569 #define KSZ8775_PORTn_CTRL11_STAT3_PHY_LOOPBACK 0x80
570 #define KSZ8775_PORTn_CTRL11_STAT3_PHY_ISOLATE 0x20
571 #define KSZ8775_PORTn_CTRL11_STAT3_SOFT_RESET 0x10
572 #define KSZ8775_PORTn_CTRL11_STAT3_FORCE_LINK 0x08
573 #define KSZ8775_PORTn_CTRL11_STAT3_OP_MODE 0x07
574 #define KSZ8775_PORTn_CTRL11_STAT3_OP_MODE_AN 0x01
575 #define KSZ8775_PORTn_CTRL11_STAT3_OP_MODE_10BT_HD 0x02
576 #define KSZ8775_PORTn_CTRL11_STAT3_OP_MODE_100BTX_HD 0x03
577 #define KSZ8775_PORTn_CTRL11_STAT3_OP_MODE_10BT_FD 0x05
578 #define KSZ8775_PORTn_CTRL11_STAT3_OP_MODE_100BTX_FD 0x06
579 
580 //Indirect Access Control 0 register
581 #define KSZ8775_INDIRECT_CTRL0_FUNC_SEL 0xE0
582 #define KSZ8775_INDIRECT_CTRL0_FUNC_SEL_INDIRECT_MODE 0x00
583 #define KSZ8775_INDIRECT_CTRL0_FUNC_SEL_EEE 0x20
584 #define KSZ8775_INDIRECT_CTRL0_FUNC_SEL_ACL 0x40
585 #define KSZ8775_INDIRECT_CTRL0_FUNC_SEL_PME 0x80
586 #define KSZ8775_INDIRECT_CTRL0_FUNC_SEL_LINKMD 0xA0
587 #define KSZ8775_INDIRECT_CTRL0_WRITE 0x00
588 #define KSZ8775_INDIRECT_CTRL0_READ 0x10
589 #define KSZ8775_INDIRECT_CTRL0_TABLE_SEL 0x0C
590 #define KSZ8775_INDIRECT_CTRL0_TABLE_SEL_STATIC_MAC 0x00
591 #define KSZ8775_INDIRECT_CTRL0_TABLE_SEL_VLAN 0x04
592 #define KSZ8775_INDIRECT_CTRL0_TABLE_SEL_DYNAMIC_MAC 0x08
593 #define KSZ8775_INDIRECT_CTRL0_TABLE_SEL_MIB_COUNTER 0x0C
594 #define KSZ8775_INDIRECT_CTRL0_ADDR_11_8 0x0F
595 #define KSZ8775_INDIRECT_CTRL0_ADDR_9_8 0x03
596 
597 //Indirect Access Control 1 register
598 #define KSZ8775_INDIRECT_CTRL1_ADDR_7_0 0xFF
599 
600 //Interrupt Status register
601 #define KSZ8775_INT_STAT_PME 0x10
602 #define KSZ8775_INT_STAT_PORT4 0x08
603 #define KSZ8775_INT_STAT_PORT3 0x04
604 #define KSZ8775_INT_STAT_PORT2 0x02
605 #define KSZ8775_INT_STAT_PORT1 0x01
606 
607 //Interrupt Mask register
608 #define KSZ8775_INT_MASK_PME 0x10
609 #define KSZ8775_INT_MASK_PORT4 0x08
610 #define KSZ8775_INT_MASK_PORT3 0x04
611 #define KSZ8775_INT_MASK_PORT2 0x02
612 #define KSZ8775_INT_MASK_PORT1 0x01
613 
614 //ACL Interrupt Status register
615 #define KSZ8775_ACL_INT_STAT_PORT5 0x10
616 #define KSZ8775_ACL_INT_STAT_PORT4 0x08
617 #define KSZ8775_ACL_INT_STAT_PORT3 0x04
618 #define KSZ8775_ACL_INT_STAT_PORT2 0x02
619 #define KSZ8775_ACL_INT_STAT_PORT1 0x01
620 
621 //ACL Interrupt Control register
622 #define KSZ8775_ACL_INT_CTRL_PORT5 0x10
623 #define KSZ8775_ACL_INT_CTRL_PORT4 0x08
624 #define KSZ8775_ACL_INT_CTRL_PORT3 0x04
625 #define KSZ8775_ACL_INT_CTRL_PORT2 0x02
626 #define KSZ8775_ACL_INT_CTRL_PORT1 0x01
627 
628 //Global Control 12 register
629 #define KSZ8775_GLOBAL_CTRL12_TAG3 0xC0
630 #define KSZ8775_GLOBAL_CTRL12_TAG2 0x30
631 #define KSZ8775_GLOBAL_CTRL12_TAG1 0x0C
632 #define KSZ8775_GLOBAL_CTRL12_TAG0 0x03
633 
634 //Global Control 13 register
635 #define KSZ8775_GLOBAL_CTRL13_TAG7 0xC0
636 #define KSZ8775_GLOBAL_CTRL13_TAG6 0x30
637 #define KSZ8775_GLOBAL_CTRL13_TAG5 0x0C
638 #define KSZ8775_GLOBAL_CTRL13_TAG4 0x03
639 
640 //Global Control 14 register
641 #define KSZ8775_GLOBAL_CTRL14_PRI_2Q 0xC0
642 
643 //Global Control 15 register
644 #define KSZ8775_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD 0x20
645 #define KSZ8775_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP 0x1F
646 #define KSZ8775_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_FILT 0x00
647 #define KSZ8775_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_PORT1 0x01
648 #define KSZ8775_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_PORT2 0x02
649 #define KSZ8775_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_PORT3 0x04
650 #define KSZ8775_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_PORT4 0x08
651 #define KSZ8775_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_PORT5 0x10
652 #define KSZ8775_GLOBAL_CTRL15_UNKNOWN_UNICAST_FWD_MAP_ALL 0x1F
653 
654 //Global Control 16 register
655 #define KSZ8775_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD 0x20
656 #define KSZ8775_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP 0x1F
657 #define KSZ8775_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_FILT 0x00
658 #define KSZ8775_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_PORT1 0x01
659 #define KSZ8775_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_PORT2 0x02
660 #define KSZ8775_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_PORT3 0x04
661 #define KSZ8775_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_PORT4 0x08
662 #define KSZ8775_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_PORT5 0x10
663 #define KSZ8775_GLOBAL_CTRL16_UNKNOWN_MCAST_FWD_MAP_ALL 0x1F
664 
665 //Global Control 17 register
666 #define KSZ8775_GLOBAL_CTRL17_UNKNOWN_VID_FWD 0x20
667 #define KSZ8775_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP 0x1F
668 #define KSZ8775_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_FILT 0x00
669 #define KSZ8775_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_PORT1 0x01
670 #define KSZ8775_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_PORT2 0x02
671 #define KSZ8775_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_PORT3 0x04
672 #define KSZ8775_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_PORT4 0x08
673 #define KSZ8775_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_PORT5 0x10
674 #define KSZ8775_GLOBAL_CTRL17_UNKNOWN_VID_FWD_MAP_ALL 0x1F
675 
676 //Global Control 18 register
677 #define KSZ8775_GLOBAL_CTRL18_SELF_ADDR_FILTER_EN 0x40
678 #define KSZ8775_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD 0x20
679 #define KSZ8775_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP 0x1F
680 #define KSZ8775_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_FILT 0x00
681 #define KSZ8775_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_PORT1 0x01
682 #define KSZ8775_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_PORT2 0x02
683 #define KSZ8775_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_PORT3 0x04
684 #define KSZ8775_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_PORT4 0x08
685 #define KSZ8775_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_PORT5 0x10
686 #define KSZ8775_GLOBAL_CTRL18_UNKNOWN_IP_MCAST_FWD_MAP_ALL 0x1F
687 
688 //Global Control 19 register
689 #define KSZ8775_GLOBAL_CTRL19_IG_RATE_LIMIT_PERIOD 0x30
690 #define KSZ8775_GLOBAL_CTRL19_IG_RATE_LIMIT_PERIOD_16MS 0x00
691 #define KSZ8775_GLOBAL_CTRL19_IG_RATE_LIMIT_PERIOD_64MS 0x10
692 #define KSZ8775_GLOBAL_CTRL19_IG_RATE_LIMIT_PERIOD_256MS 0x20
693 #define KSZ8775_GLOBAL_CTRL19_QUEUE_BASED_EG_RATE_LIMITE_EN 0x08
694 #define KSZ8775_GLOBAL_CTRL19_INSERT_SRC_PORT_PVID_TAG_EN 0x04
695 
696 //Global Control 20 register
697 #define KSZ8775_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH 0x70
698 #define KSZ8775_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_2MA 0x00
699 #define KSZ8775_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_4MA 0x10
700 #define KSZ8775_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_8MA 0x20
701 #define KSZ8775_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_12MA 0x30
702 #define KSZ8775_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_16MA 0x40
703 #define KSZ8775_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_20MA 0x50
704 #define KSZ8775_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_24MA 0x60
705 #define KSZ8775_GLOBAL_CTRL20_HIGH_SPEED_DRIVE_STRENGTH_28MA 0x70
706 #define KSZ8775_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH 0x07
707 #define KSZ8775_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_2MA 0x00
708 #define KSZ8775_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_4MA 0x01
709 #define KSZ8775_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_8MA 0x02
710 #define KSZ8775_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_12MA 0x03
711 #define KSZ8775_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_16MA 0x04
712 #define KSZ8775_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_20MA 0x05
713 #define KSZ8775_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_24MA 0x06
714 #define KSZ8775_GLOBAL_CTRL20_LOW_SPEED_DRIVE_STRENGTH_28MA 0x07
715 
716 //Global Control 21 register
717 #define KSZ8775_GLOBAL_CTRL21_MLD_SNOOP_OPT 0x08
718 #define KSZ8775_GLOBAL_CTRL21_MLD_SNOOP_EN 0x04
719 
720 //C++ guard
721 #ifdef __cplusplus
722 extern "C" {
723 #endif
724 
725 //CC-RX, CodeWarrior or Win32 compiler?
726 #if defined(__CCRX__)
727  #pragma pack
728 #elif defined(__CWCC__) || defined(_WIN32)
729  #pragma pack(push, 1)
730 #endif
731 
732 
733 /**
734  * @brief Static MAC table entry (read operation)
735  **/
736 
737 typedef struct
738 {
739 #if defined(_CPU_BIG_ENDIAN) && !defined(__ICCRX__)
740  uint8_t fid : 7; //0
741  uint8_t useFid : 1;
742  uint8_t reserved : 1; //1
743  uint8_t override : 1;
744  uint8_t valid : 1;
745  uint8_t forwardPorts : 5;
746 #else
747  uint8_t useFid : 1; //0
748  uint8_t fid : 7;
749  uint8_t forwardPorts : 5; //1
750  uint8_t valid : 1;
751  uint8_t override : 1;
752  uint8_t reserved : 1;
753 #endif
756 
757 
758 /**
759  * @brief Static MAC table entry (write operation)
760  **/
761 
762 typedef struct
763 {
764  uint8_t fid; //0
765 #if defined(_CPU_BIG_ENDIAN) && !defined(__ICCRX__)
766  uint8_t useFid : 1; //1
767  uint8_t override : 1;
768  uint8_t valid : 1;
769  uint8_t forwardPorts : 5;
770 #else
771  uint8_t forwardPorts : 5; //1
772  uint8_t valid : 1;
773  uint8_t override : 1;
774  uint8_t useFid : 1;
775 #endif
778 
779 
780 /**
781  * @brief Dynamic MAC table entry
782  **/
783 
784 typedef struct
785 {
786 #if defined(_CPU_BIG_ENDIAN) && !defined(__ICCRX__)
787  uint8_t macEmpty : 1; //0
788  uint8_t numValidEntriesH : 7;
789  uint8_t numValidEntriesL : 3; //1
790  uint8_t timestamp : 2;
791  uint8_t sourcePort : 3;
792  uint8_t dataNotReady : 1; //2
793  uint8_t fid : 7;
794 #else
795  uint8_t numValidEntriesH : 7; //0
796  uint8_t macEmpty : 1;
797  uint8_t sourcePort : 3; //1
798  uint8_t timestamp : 2;
799  uint8_t numValidEntriesL : 3;
800  uint8_t fid : 7; //2
801  uint8_t dataNotReady : 1;
802 #endif
805 
806 
807 //CC-RX, CodeWarrior or Win32 compiler?
808 #if defined(__CCRX__)
809  #pragma unpack
810 #elif defined(__CWCC__) || defined(_WIN32)
811  #pragma pack(pop)
812 #endif
813 
814 //KSZ8775 Ethernet switch driver
815 extern const SwitchDriver ksz8775SwitchDriver;
816 
817 //KSZ8775 related functions
818 error_t ksz8775Init(NetInterface *interface);
819 void ksz8775InitHook(NetInterface *interface);
820 
821 void ksz8775Tick(NetInterface *interface);
822 
823 void ksz8775EnableIrq(NetInterface *interface);
824 void ksz8775DisableIrq(NetInterface *interface);
825 
826 void ksz8775EventHandler(NetInterface *interface);
827 
828 error_t ksz8775TagFrame(NetInterface *interface, NetBuffer *buffer,
829  size_t *offset, NetTxAncillary *ancillary);
830 
831 error_t ksz8775UntagFrame(NetInterface *interface, uint8_t **frame,
832  size_t *length, NetRxAncillary *ancillary);
833 
834 bool_t ksz8775GetLinkState(NetInterface *interface, uint8_t port);
835 uint32_t ksz8775GetLinkSpeed(NetInterface *interface, uint8_t port);
837 
838 void ksz8775SetPortState(NetInterface *interface, uint8_t port,
839  SwitchPortState state);
840 
842 
843 void ksz8775SetAgingTime(NetInterface *interface, uint32_t agingTime);
844 
845 void ksz8775EnableIgmpSnooping(NetInterface *interface, bool_t enable);
846 void ksz8775EnableMldSnooping(NetInterface *interface, bool_t enable);
847 void ksz8775EnableRsvdMcastTable(NetInterface *interface, bool_t enable);
848 
850  const SwitchFdbEntry *entry);
851 
853  const SwitchFdbEntry *entry);
854 
856  SwitchFdbEntry *entry);
857 
859 
861  SwitchFdbEntry *entry);
862 
863 void ksz8775FlushDynamicFdbTable(NetInterface *interface, uint8_t port);
864 
866  bool_t enable, uint32_t forwardPorts);
867 
868 void ksz8775WritePhyReg(NetInterface *interface, uint8_t port,
869  uint8_t address, uint16_t data);
870 
871 uint16_t ksz8775ReadPhyReg(NetInterface *interface, uint8_t port,
872  uint8_t address);
873 
874 void ksz8775DumpPhyReg(NetInterface *interface, uint8_t port);
875 
876 void ksz8775WriteSwitchReg(NetInterface *interface, uint16_t address,
877  uint8_t data);
878 
879 uint8_t ksz8775ReadSwitchReg(NetInterface *interface, uint16_t address);
880 
881 void ksz8775DumpSwitchReg(NetInterface *interface);
882 
883 //C++ guard
884 #ifdef __cplusplus
885 }
886 #endif
887 
888 #endif
unsigned int uint_t
Definition: compiler_port.h:50
int bool_t
Definition: compiler_port.h:53
uint16_t port
Definition: dns_common.h:267
error_t
Error codes.
Definition: error.h:43
uint8_t data[]
Definition: ethernet.h:222
MacAddr
Definition: ethernet.h:195
uint8_t reserved
Definition: ipv4.h:312
Ipv6Addr address[]
Definition: ipv6.h:316
void ksz8775EnableIgmpSnooping(NetInterface *interface, bool_t enable)
Enable IGMP snooping.
void ksz8775SetPortState(NetInterface *interface, uint8_t port, SwitchPortState state)
Set port state.
void ksz8775SetAgingTime(NetInterface *interface, uint32_t agingTime)
Set aging time for dynamic filtering entries.
void ksz8775WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
error_t ksz8775GetDynamicFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the dynamic MAC table.
void ksz8775DisableIrq(NetInterface *interface)
Disable interrupts.
error_t ksz8775UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, NetRxAncillary *ancillary)
Decode tail tag from incoming Ethernet frame.
void ksz8775EventHandler(NetInterface *interface)
KSZ8775 event handler.
uint32_t ksz8775GetLinkSpeed(NetInterface *interface, uint8_t port)
Get link speed.
error_t ksz8775DeleteStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Remove an entry from the static MAC table.
void ksz8775InitHook(NetInterface *interface)
KSZ8775 custom configuration.
void ksz8775DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
error_t ksz8775AddStaticFdbEntry(NetInterface *interface, const SwitchFdbEntry *entry)
Add a new entry to the static MAC table.
error_t ksz8775Init(NetInterface *interface)
KSZ8775 Ethernet switch initialization.
error_t ksz8775TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, NetTxAncillary *ancillary)
Add tail tag to Ethernet frame.
void ksz8775WriteSwitchReg(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register.
void ksz8775EnableIrq(NetInterface *interface)
Enable interrupts.
void ksz8775FlushDynamicFdbTable(NetInterface *interface, uint8_t port)
Flush dynamic MAC table.
SwitchPortState ksz8775GetPortState(NetInterface *interface, uint8_t port)
Get port state.
void ksz8775SetUnknownMcastFwdPorts(NetInterface *interface, bool_t enable, uint32_t forwardPorts)
Set forward ports for unknown multicast packets.
bool_t ksz8775GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
NicDuplexMode ksz8775GetDuplexMode(NetInterface *interface, uint8_t port)
Get duplex mode.
const SwitchDriver ksz8775SwitchDriver
KSZ8775 Ethernet switch driver.
uint16_t ksz8775ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
uint8_t ksz8775ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
void ksz8775DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
void ksz8775EnableMldSnooping(NetInterface *interface, bool_t enable)
Enable MLD snooping.
void ksz8775Tick(NetInterface *interface)
KSZ8775 timer handler.
void ksz8775FlushStaticFdbTable(NetInterface *interface)
Flush static MAC table.
void ksz8775EnableRsvdMcastTable(NetInterface *interface, bool_t enable)
Enable reserved multicast table.
error_t ksz8775GetStaticFdbEntry(NetInterface *interface, uint_t index, SwitchFdbEntry *entry)
Read an entry from the static MAC table.
#define NetInterface
Definition: net.h:36
#define NetRxAncillary
Definition: net_misc.h:40
#define NetTxAncillary
Definition: net_misc.h:36
Network interface controller abstraction layer.
NicDuplexMode
Duplex mode.
Definition: nic.h:122
SwitchPortState
Switch port state.
Definition: nic.h:134
Dynamic MAC table entry.
uint8_t numValidEntriesH
uint8_t sourcePort
MacAddr macAddr
uint8_t fid
uint8_t macEmpty
uint8_t numValidEntriesL
uint8_t timestamp
uint8_t dataNotReady
Static MAC table entry (read operation)
uint8_t forwardPorts
MacAddr macAddr
uint8_t valid
uint8_t useFid
uint8_t override
uint8_t fid
uint8_t reserved
Static MAC table entry (write operation)
uint8_t forwardPorts
MacAddr macAddr
uint8_t valid
uint8_t useFid
uint8_t override
uint8_t fid
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:89
Ethernet switch driver.
Definition: nic.h:322
Forwarding database entry.
Definition: nic.h:149
uint8_t length
Definition: tcp.h:368