ksz8864_driver.h
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1 /**
2  * @file ksz8864_driver.h
3  * @brief KSZ8864 5-port Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _KSZ8864_DRIVER_H
32 #define _KSZ8864_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //KSZ8864 ports
38 #define KSZ8864_PORT1 1
39 #define KSZ8864_PORT2 2
40 #define KSZ8864_PORT3 3
41 
42 //SPI command byte
43 #define KSZ8864_SPI_CMD_WRITE 0x02
44 #define KSZ8864_SPI_CMD_READ 0x03
45 
46 //KSZ8864 PHY registers
47 #define KSZ8864_BMCR 0x00
48 #define KSZ8864_BMSR 0x01
49 #define KSZ8864_PHYID1 0x02
50 #define KSZ8864_PHYID2 0x03
51 #define KSZ8864_ANAR 0x04
52 #define KSZ8864_ANLPAR 0x05
53 #define KSZ8864_LINKMD 0x1D
54 #define KSZ8864_PHYSCS 0x1F
55 
56 //KSZ8864 Switch registers
57 #define KSZ8864_CHIP_ID0 0x00
58 #define KSZ8864_CHIP_ID1 0x01
59 #define KSZ8864_GLOBAL_CTRL0 0x02
60 #define KSZ8864_GLOBAL_CTRL1 0x03
61 #define KSZ8864_GLOBAL_CTRL2 0x04
62 #define KSZ8864_GLOBAL_CTRL3 0x05
63 #define KSZ8864_GLOBAL_CTRL4 0x06
64 #define KSZ8864_GLOBAL_CTRL5 0x07
65 #define KSZ8864_GLOBAL_CTRL6 0x08
66 #define KSZ8864_GLOBAL_CTRL7 0x09
67 #define KSZ8864_GLOBAL_CTRL8 0x0A
68 #define KSZ8864_GLOBAL_CTRL9 0x0B
69 #define KSZ8864_GLOBAL_CTRL10 0x0C
70 #define KSZ8864_GLOBAL_CTRL11 0x0D
71 #define KSZ8864_PD_MGMT_CTRL1 0x0E
72 #define KSZ8864_PD_MGMT_CTRL2 0x0F
73 #define KSZ8864_PORT1_CTRL0 0x20
74 #define KSZ8864_PORT1_CTRL1 0x21
75 #define KSZ8864_PORT1_CTRL2 0x22
76 #define KSZ8864_PORT1_CTRL3 0x23
77 #define KSZ8864_PORT1_CTRL4 0x24
78 #define KSZ8864_PORT1_STAT0 0x29
79 #define KSZ8864_PORT1_PSCS 0x2A
80 #define KSZ8864_PORT1_LINKMD 0x2B
81 #define KSZ8864_PORT1_CTRL5 0x2C
82 #define KSZ8864_PORT1_CTRL6 0x2D
83 #define KSZ8864_PORT1_STAT1 0x2E
84 #define KSZ8864_PORT1_CTRL7_STAT2 0x2F
85 #define KSZ8864_PORT2_CTRL0 0x30
86 #define KSZ8864_PORT2_CTRL1 0x31
87 #define KSZ8864_PORT2_CTRL2 0x32
88 #define KSZ8864_PORT2_CTRL3 0x33
89 #define KSZ8864_PORT2_CTRL4 0x34
90 #define KSZ8864_PORT2_STAT0 0x39
91 #define KSZ8864_PORT2_PSCS 0x3A
92 #define KSZ8864_PORT2_LINKMD 0x3B
93 #define KSZ8864_PORT2_CTRL5 0x3C
94 #define KSZ8864_PORT2_CTRL6 0x3D
95 #define KSZ8864_PORT2_STAT1 0x3E
96 #define KSZ8864_PORT2_CTRL7_STAT2 0x3F
97 #define KSZ8864_PORT3_CTRL0 0x40
98 #define KSZ8864_PORT3_CTRL1 0x41
99 #define KSZ8864_PORT3_CTRL2 0x42
100 #define KSZ8864_PORT3_CTRL3 0x43
101 #define KSZ8864_PORT3_CTRL4 0x44
102 #define KSZ8864_PORT3_CTRL6 0x4D
103 #define KSZ8864_PORT4_CTRL0 0x50
104 #define KSZ8864_PORT4_CTRL1 0x51
105 #define KSZ8864_PORT4_CTRL2 0x52
106 #define KSZ8864_PORT4_CTRL3 0x53
107 #define KSZ8864_PORT4_CTRL4 0x54
108 #define KSZ8864_RMII_MGMT_CTRL 0x57
109 #define KSZ8864_PORT4_CTRL6 0x5D
110 #define KSZ8864_MAC_ADDR0 0x68
111 #define KSZ8864_MAC_ADDR1 0x69
112 #define KSZ8864_MAC_ADDR2 0x6A
113 #define KSZ8864_MAC_ADDR3 0x6B
114 #define KSZ8864_MAC_ADDR4 0x6C
115 #define KSZ8864_MAC_ADDR5 0x6D
116 #define KSZ8864_IND_ACCESS_CTRL0 0x6E
117 #define KSZ8864_IND_ACCESS_CTRL1 0x6F
118 #define KSZ8864_IND_DATA8 0x70
119 #define KSZ8864_IND_DATA7 0x71
120 #define KSZ8864_IND_DATA6 0x72
121 #define KSZ8864_IND_DATA5 0x73
122 #define KSZ8864_IND_DATA4 0x74
123 #define KSZ8864_IND_DATA3 0x75
124 #define KSZ8864_IND_DATA2 0x76
125 #define KSZ8864_IND_DATA1 0x77
126 #define KSZ8864_IND_DATA0 0x78
127 #define KSZ8864_INT_STAT 0x7C
128 #define KSZ8864_INT_MASK 0x7D
129 #define KSZ8864_GLOBAL_CTRL12 0x80
130 #define KSZ8864_GLOBAL_CTRL13 0x81
131 #define KSZ8864_GLOBAL_CTRL14 0x82
132 #define KSZ8864_GLOBAL_CTRL15 0x83
133 #define KSZ8864_GLOBAL_CTRL16 0x84
134 #define KSZ8864_GLOBAL_CTRL17 0x85
135 #define KSZ8864_GLOBAL_CTRL18 0x86
136 #define KSZ8864_GLOBAL_CTRL19 0x87
137 #define KSZ8864_ID 0x89
138 #define KSZ8864_TOS_PRIO_CTRL0 0x90
139 #define KSZ8864_TOS_PRIO_CTRL1 0x91
140 #define KSZ8864_TOS_PRIO_CTRL2 0x92
141 #define KSZ8864_TOS_PRIO_CTRL3 0x93
142 #define KSZ8864_TOS_PRIO_CTRL4 0x94
143 #define KSZ8864_TOS_PRIO_CTRL5 0x95
144 #define KSZ8864_TOS_PRIO_CTRL6 0x96
145 #define KSZ8864_TOS_PRIO_CTRL7 0x97
146 #define KSZ8864_TOS_PRIO_CTRL8 0x98
147 #define KSZ8864_TOS_PRIO_CTRL9 0x99
148 #define KSZ8864_TOS_PRIO_CTRL10 0x9A
149 #define KSZ8864_TOS_PRIO_CTRL11 0x9B
150 #define KSZ8864_TOS_PRIO_CTRL12 0x9C
151 #define KSZ8864_TOS_PRIO_CTRL13 0x9D
152 #define KSZ8864_TOS_PRIO_CTRL14 0x9E
153 #define KSZ8864_TOS_PRIO_CTRL15 0x9F
154 #define KSZ8864_TEST 0xBF
155 #define KSZ8864_PORT1_CTRL8 0xC0
156 #define KSZ8864_PORT1_CTRL9 0xC1
157 #define KSZ8864_PORT1_CTRL10 0xC2
158 #define KSZ8864_PORT1_CTRL11 0xC3
159 #define KSZ8864_PORT1_CTRL12 0xC4
160 #define KSZ8864_PORT1_CTRL13 0xC5
161 #define KSZ8864_PORT1_RATE_LIMIT_CTRL 0xC6
162 #define KSZ8864_PORT1_PRIO0_IG_LIMIT_CTRL1 0xC7
163 #define KSZ8864_PORT1_PRIO1_IG_LIMIT_CTRL2 0xC8
164 #define KSZ8864_PORT1_PRIO2_IG_LIMIT_CTRL3 0xC9
165 #define KSZ8864_PORT1_PRIO3_IG_LIMIT_CTRL4 0xCA
166 #define KSZ8864_PORT1_QUEUE0_EG_LIMIT_CTRL1 0xCB
167 #define KSZ8864_PORT1_QUEUE1_EG_LIMIT_CTRL2 0xCC
168 #define KSZ8864_PORT1_QUEUE2_EG_LIMIT_CTRL3 0xCD
169 #define KSZ8864_PORT1_QUEUE3_EG_LIMIT_CTRL4 0xCE
170 #define KSZ8864_TEST_PORT3_CTRL1 0xCF
171 #define KSZ8864_PORT2_CTRL8 0xD0
172 #define KSZ8864_PORT2_CTRL9 0xD1
173 #define KSZ8864_PORT2_CTRL10 0xD2
174 #define KSZ8864_PORT2_CTRL11 0xD3
175 #define KSZ8864_PORT2_CTRL12 0xD4
176 #define KSZ8864_PORT2_CTRL13 0xD5
177 #define KSZ8864_PORT2_RATE_LIMIT_CTRL 0xD6
178 #define KSZ8864_PORT2_PRIO0_IG_LIMIT_CTRL1 0xD7
179 #define KSZ8864_PORT2_PRIO1_IG_LIMIT_CTRL2 0xD8
180 #define KSZ8864_PORT2_PRIO2_IG_LIMIT_CTRL3 0xD9
181 #define KSZ8864_PORT2_PRIO3_IG_LIMIT_CTRL4 0xDA
182 #define KSZ8864_PORT2_QUEUE0_EG_LIMIT_CTRL1 0xDB
183 #define KSZ8864_PORT2_QUEUE1_EG_LIMIT_CTRL2 0xDC
184 #define KSZ8864_PORT2_QUEUE2_EG_LIMIT_CTRL3 0xDD
185 #define KSZ8864_PORT2_QUEUE3_EG_LIMIT_CTRL4 0xDE
186 #define KSZ8864_TEST_PORT3_CTRL2 0xDF
187 #define KSZ8864_PORT3_CTRL8 0xE0
188 #define KSZ8864_PORT3_CTRL9 0xE1
189 #define KSZ8864_PORT3_CTRL10 0xE2
190 #define KSZ8864_PORT3_CTRL11 0xE3
191 #define KSZ8864_PORT3_CTRL12 0xE4
192 #define KSZ8864_PORT3_CTRL13 0xE5
193 #define KSZ8864_PORT3_RATE_LIMIT_CTRL 0xE6
194 #define KSZ8864_PORT3_PRIO0_IG_LIMIT_CTRL1 0xE7
195 #define KSZ8864_PORT3_PRIO1_IG_LIMIT_CTRL2 0xE8
196 #define KSZ8864_PORT3_PRIO2_IG_LIMIT_CTRL3 0xE9
197 #define KSZ8864_PORT3_PRIO3_IG_LIMIT_CTRL4 0xEA
198 #define KSZ8864_PORT3_QUEUE0_EG_LIMIT_CTRL1 0xEB
199 #define KSZ8864_PORT3_QUEUE1_EG_LIMIT_CTRL2 0xEC
200 #define KSZ8864_PORT3_QUEUE2_EG_LIMIT_CTRL3 0xED
201 #define KSZ8864_PORT3_QUEUE3_EG_LIMIT_CTRL4 0xEE
202 #define KSZ8864_TEST3 0xEF
203 #define KSZ8864_PORT4_CTRL8 0xF0
204 #define KSZ8864_PORT4_CTRL9 0xF1
205 #define KSZ8864_PORT4_CTRL10 0xF2
206 #define KSZ8864_PORT4_CTRL11 0xF3
207 #define KSZ8864_PORT4_CTRL12 0xF4
208 #define KSZ8864_PORT4_CTRL13 0xF5
209 #define KSZ8864_PORT4_RATE_LIMIT_CTRL 0xF6
210 #define KSZ8864_PORT4_PRIO0_IG_LIMIT_CTRL1 0xF7
211 #define KSZ8864_PORT4_PRIO1_IG_LIMIT_CTRL2 0xF8
212 #define KSZ8864_PORT4_PRIO2_IG_LIMIT_CTRL3 0xF9
213 #define KSZ8864_PORT4_PRIO3_IG_LIMIT_CTRL4 0xFA
214 #define KSZ8864_PORT4_QUEUE0_EG_LIMIT_CTRL1 0xFB
215 #define KSZ8864_PORT4_QUEUE1_EG_LIMIT_CTRL2 0xFC
216 #define KSZ8864_PORT4_QUEUE2_EG_LIMIT_CTRL3 0xFD
217 #define KSZ8864_PORT4_QUEUE3_EG_LIMIT_CTRL4 0xFE
218 #define KSZ8864_TEST4 0xFF
219 
220 //KSZ8864 Switch register access macros
221 #define KSZ8864_PORTn_CTRL0(port) (0x10 + ((port) * 0x10))
222 #define KSZ8864_PORTn_CTRL1(port) (0x11 + ((port) * 0x10))
223 #define KSZ8864_PORTn_CTRL2(port) (0x12 + ((port) * 0x10))
224 #define KSZ8864_PORTn_CTRL3(port) (0x13 + ((port) * 0x10))
225 #define KSZ8864_PORTn_CTRL4(port) (0x14 + ((port) * 0x10))
226 #define KSZ8864_PORTn_STAT0(port) (0x19 + ((port) * 0x10))
227 #define KSZ8864_PORTn_PSCS(port) (0x1A + ((port) * 0x10))
228 #define KSZ8864_PORTn_LINKMD(port) (0x1B + ((port) * 0x10))
229 #define KSZ8864_PORTn_CTRL5(port) (0x1C + ((port) * 0x10))
230 #define KSZ8864_PORTn_CTRL6(port) (0x1D + ((port) * 0x10))
231 #define KSZ8864_PORTn_STAT1(port) (0x1E + ((port) * 0x10))
232 #define KSZ8864_PORTn_CTRL7_STAT2(port) (0x1F + ((port) * 0x10))
233 #define KSZ8864_PORTn_CTRL8(port) (0xB0 + ((port) * 0x10))
234 #define KSZ8864_PORTn_CTRL9(port) (0xB1 + ((port) * 0x10))
235 #define KSZ8864_PORTn_CTRL10(port) (0xB2 + ((port) * 0x10))
236 #define KSZ8864_PORTn_CTRL11(port) (0xB3 + ((port) * 0x10))
237 #define KSZ8864_PORTn_CTRL12(port) (0xB4 + ((port) * 0x10))
238 #define KSZ8864_PORTn_CTRL13(port) (0xB5 + ((port) * 0x10))
239 #define KSZ8864_PORTn_RATE_LIMIT_CTRL(port) (0xB6 + ((port) * 0x10))
240 #define KSZ8864_PORTn_PRIO0_IG_LIMIT_CTRL1(port) (0xB7 + ((port) * 0x10))
241 #define KSZ8864_PORTn_PRIO1_IG_LIMIT_CTRL2(port) (0xB8 + ((port) * 0x10))
242 #define KSZ8864_PORTn_PRIO2_IG_LIMIT_CTRL3(port) (0xB9 + ((port) * 0x10))
243 #define KSZ8864_PORTn_PRIO3_IG_LIMIT_CTRL4(port) (0xBA + ((port) * 0x10))
244 #define KSZ8864_PORTn_QUEUE0_EG_LIMIT_CTRL1(port) (0xBB + ((port) * 0x10))
245 #define KSZ8864_PORTn_QUEUE1_EG_LIMIT_CTRL2(port) (0xBC + ((port) * 0x10))
246 #define KSZ8864_PORTn_QUEUE2_EG_LIMIT_CTRL3(port) (0xBD + ((port) * 0x10))
247 #define KSZ8864_PORTn_QUEUE3_EG_LIMIT_CTRL4(port) (0xBE + ((port) * 0x10))
248 
249 //MII Control register
250 #define KSZ8864_BMCR_RESET 0x8000
251 #define KSZ8864_BMCR_LOOPBACK 0x4000
252 #define KSZ8864_BMCR_FORCE_100 0x2000
253 #define KSZ8864_BMCR_AN_EN 0x1000
254 #define KSZ8864_BMCR_POWER_DOWN 0x0800
255 #define KSZ8864_BMCR_ISOLATE 0x0400
256 #define KSZ8864_BMCR_RESTART_AN 0x0200
257 #define KSZ8864_BMCR_FORCE_FULL_DUPLEX 0x0100
258 #define KSZ8864_BMCR_COL_TEST 0x0080
259 #define KSZ8864_BMCR_HP_MDIX 0x0020
260 #define KSZ8864_BMCR_FORCE_MDI 0x0010
261 #define KSZ8864_BMCR_AUTO_MDIX_DIS 0x0008
262 #define KSZ8864_BMCR_FAR_END_FAULT_DIS 0x0004
263 #define KSZ8864_BMCR_TRANSMIT_DIS 0x0002
264 #define KSZ8864_BMCR_LED_DIS 0x0001
265 
266 //MII Status register
267 #define KSZ8864_BMSR_100BT4 0x8000
268 #define KSZ8864_BMSR_100BTX_FD 0x4000
269 #define KSZ8864_BMSR_100BTX_HD 0x2000
270 #define KSZ8864_BMSR_10BT_FD 0x1000
271 #define KSZ8864_BMSR_10BT_HD 0x0800
272 #define KSZ8864_BMSR_PREAMBLE_SUPPR 0x0040
273 #define KSZ8864_BMSR_AN_COMPLETE 0x0020
274 #define KSZ8864_BMSR_FAR_END_FAULT 0x0010
275 #define KSZ8864_BMSR_AN_CAPABLE 0x0008
276 #define KSZ8864_BMSR_LINK_STATUS 0x0004
277 #define KSZ8864_BMSR_JABBER_TEST 0x0002
278 #define KSZ8864_BMSR_EXTENDED_CAPABLE 0x0001
279 
280 //PHYID High register
281 #define KSZ8864_PHYID1_DEFAULT 0x0022
282 
283 //PHYID Low register
284 #define KSZ8864_PHYID2_DEFAULT 0x1450
285 
286 //Advertisement Ability register
287 #define KSZ8864_ANAR_NEXT_PAGE 0x8000
288 #define KSZ8864_ANAR_REMOTE_FAULT 0x2000
289 #define KSZ8864_ANAR_PAUSE 0x0400
290 #define KSZ8864_ANAR_100BTX_FD 0x0100
291 #define KSZ8864_ANAR_100BTX_HD 0x0080
292 #define KSZ8864_ANAR_10BT_FD 0x0040
293 #define KSZ8864_ANAR_10BT_HD 0x0020
294 #define KSZ8864_ANAR_SELECTOR 0x001F
295 #define KSZ8864_ANAR_SELECTOR_DEFAULT 0x0001
296 
297 //Link Partner Ability register
298 #define KSZ8864_ANLPAR_NEXT_PAGE 0x8000
299 #define KSZ8864_ANLPAR_LP_ACK 0x4000
300 #define KSZ8864_ANLPAR_REMOTE_FAULT 0x2000
301 #define KSZ8864_ANLPAR_PAUSE 0x0400
302 #define KSZ8864_ANLPAR_100BTX_FD 0x0100
303 #define KSZ8864_ANLPAR_100BTX_HD 0x0080
304 #define KSZ8864_ANLPAR_10BT_FD 0x0040
305 #define KSZ8864_ANLPAR_10BT_HD 0x0020
306 
307 //LinkMD Control/Status register
308 #define KSZ8864_LINKMD_TEST_EN 0x8000
309 #define KSZ8864_LINKMD_RESULT 0x6000
310 #define KSZ8864_LINKMD_SHORT 0x1000
311 #define KSZ8864_LINKMD_FAULT_COUNT 0x01FF
312 
313 //PHY Special Control/Status register
314 #define KSZ8864_PHYSCS_OP_MODE 0x0700
315 #define KSZ8864_PHYSCS_OP_MODE_AN 0x0100
316 #define KSZ8864_PHYSCS_OP_MODE_10BT_HD 0x0200
317 #define KSZ8864_PHYSCS_OP_MODE_100BTX_HD 0x0300
318 #define KSZ8864_PHYSCS_OP_MODE_10BT_FD 0x0500
319 #define KSZ8864_PHYSCS_OP_MODE_100BTX_FD 0x0600
320 #define KSZ8864_PHYSCS_OP_MODE_ISOLATE 0x0700
321 #define KSZ8864_PHYSCS_POLRVS 0x0020
322 #define KSZ8864_PHYSCS_MDIX_STATUS 0x0010
323 #define KSZ8864_PHYSCS_FORCE_LINK 0x0008
324 #define KSZ8864_PHYSCS_PWRSAVE 0x0004
325 #define KSZ8864_PHYSCS_REMOTE_LOOPBACK 0x0002
326 
327 //Chip ID0 register
328 #define KSZ8864_CHIP_ID0_FAMILY_ID 0xFF
329 #define KSZ8864_CHIP_ID0_FAMILY_ID_DEFAULT 0x95
330 
331 //Chip ID1 / Start Switch register
332 #define KSZ8864_CHIP_ID1_REVISION_ID 0x0E
333 #define KSZ8864_CHIP_ID1_START_SWITCH 0x01
334 
335 //Global Control 10 register
336 #define KSZ8864_GLOBAL_CTRL10_CLK_MODE 0x40
337 #define KSZ8864_GLOBAL_CTRL10_CPU_CLK_SEL 0x30
338 #define KSZ8864_GLOBAL_CTRL10_TAIL_TAG_EN 0x02
339 #define KSZ8864_GLOBAL_CTRL10_PASS_FLOW_CTRL_PKT 0x01
340 
341 //Port N Control 0 register
342 #define KSZ8864_PORTn_CTRL0_BCAST_STORM_PROTECT_EN 0x80
343 #define KSZ8864_PORTn_CTRL0_DIFFSERV_PRIO_CLASS_EN 0x40
344 #define KSZ8864_PORTn_CTRL0_802_1P_PRIO_CLASS_EN 0x20
345 #define KSZ8864_PORTn_CTRL0_PORT_PRIO_CLASS_EN 0x18
346 #define KSZ8864_PORTn_CTRL0_TAG_INSERTION 0x04
347 #define KSZ8864_PORTn_CTRL0_TAG_REMOVAL 0x02
348 #define KSZ8864_PORTn_CTRL0_TWO_QUEUE_SPLIT_EN 0x01
349 
350 //Port N Control 1 register
351 #define KSZ8864_PORTn_CTRL1_SNIFFER_PORT 0x80
352 #define KSZ8864_PORTn_CTRL1_RECEIVE_SNIFF 0x40
353 #define KSZ8864_PORTn_CTRL1_TRANSMIT_SNIFF 0x20
354 #define KSZ8864_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x1F
355 
356 //Port N Control 2 register
357 #define KSZ8864_PORTn_CTRL2_USER_PRIO_CEILING 0x80
358 #define KSZ8864_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
359 #define KSZ8864_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
360 #define KSZ8864_PORTn_CTRL2_FORCE_FLOW_CTRL 0x10
361 #define KSZ8864_PORTn_CTRL2_BACK_PRESSURE_EN 0x08
362 #define KSZ8864_PORTn_CTRL2_TRANSMIT_EN 0x04
363 #define KSZ8864_PORTn_CTRL2_RECEIVE_EN 0x02
364 #define KSZ8864_PORTn_CTRL2_LEARNING_DIS 0x01
365 
366 //Port N Control 3 register
367 #define KSZ8864_PORTn_CTRL3_DEFAULT_USER_PRIO 0xE0
368 #define KSZ8864_PORTn_CTRL3_DEFAULT_CFI 0x10
369 #define KSZ8864_PORTn_CTRL3_DEFAULT_VID_MSB 0x0F
370 
371 //Port N Control 4 register
372 #define KSZ8864_PORTn_CTRL4_DEFAULT_VID_LSB 0xFF
373 
374 //RMII Management Control register
375 #define KSZ8864_RMII_MGMT_CTRL_SW4_CLK_OUT_DIS 0x08
376 #define KSZ8864_RMII_MGMT_CTRL_SW3_CLK_OUT_DIS 0x04
377 
378 //Port N Status 0 register
379 #define KSZ8864_PORTn_STAT0_HP_MDIX 0x80
380 #define KSZ8864_PORTn_STAT0_POLRVS 0x20
381 #define KSZ8864_PORTn_STAT0_TX_FLOW_CTRL_EN 0x10
382 #define KSZ8864_PORTn_STAT0_RX_FLOW_CTRL_EN 0x08
383 #define KSZ8864_PORTn_STAT0_OP_SPEED 0x04
384 #define KSZ8864_PORTn_STAT0_OP_DUPLEX 0x02
385 
386 //Port N PHY Special Control/Status register
387 #define KSZ8864_PORTn_PSCS_VCT_10M_SHORT 0x80
388 #define KSZ8864_PORTn_PSCS_VCT_RESULT 0x60
389 #define KSZ8864_PORTn_PSCS_VCT_EN 0x10
390 #define KSZ8864_PORTn_PSCS_FORCE_LNK 0x08
391 #define KSZ8864_PORTn_PSCS_PWRSAVE 0x04
392 #define KSZ8864_PORTn_PSCS_REMOTE_LOOPBACK 0x02
393 #define KSZ8864_PORTn_PSCS_VCT_FAULT_COUNT_MSB 0x01
394 
395 //Port N LinkMD Result register
396 #define KSZ8864_PORTn_LINKMD_VCT_FAULT_COUNT_LSB 0xFF
397 
398 //Port N Status 1 register
399 #define KSZ8864_PORTn_STAT1_MDIX_STATUS 0x80
400 #define KSZ8864_PORTn_STAT1_AN_DONE 0x40
401 #define KSZ8864_PORTn_STAT1_LINK_GOOD 0x20
402 #define KSZ8864_PORTn_STAT1_LP_FLOW_CTRL_CAPABLE 0x10
403 #define KSZ8864_PORTn_STAT1_LP_100BTX_FD_CAPABLE 0x08
404 #define KSZ8864_PORTn_STAT1_LP_100BTX_HF_CAPABLE 0x04
405 #define KSZ8864_PORTn_STAT1_LP_10BT_FD_CAPABLE 0x02
406 #define KSZ8864_PORTn_STAT1_LP_10BT_HD_CAPABLE 0x01
407 
408 //Port N Control 7 / Status 2 register
409 #define KSZ8864_PORTn_CTRL7_STAT2_PHY_LOOPBACK 0x80
410 #define KSZ8864_PORTn_CTRL7_STAT2_PHY_ISOLATE 0x20
411 #define KSZ8864_PORTn_CTRL7_STAT2_SOFT_RESET 0x10
412 #define KSZ8864_PORTn_CTRL7_STAT2_FORCE_LINK 0x08
413 #define KSZ8864_PORTn_CTRL7_STAT2_OP_MODE 0x07
414 #define KSZ8864_PORTn_CTRL7_STAT2_OP_MODE_AN 0x01
415 #define KSZ8864_PORTn_CTRL7_STAT2_OP_MODE_10BT_HD 0x02
416 #define KSZ8864_PORTn_CTRL7_STAT2_OP_MODE_100BTX_HD 0x03
417 #define KSZ8864_PORTn_CTRL7_STAT2_OP_MODE_10BT_FD 0x05
418 #define KSZ8864_PORTn_CTRL7_STAT2_OP_MODE_100BTX_FD 0x06
419 
420 //Identification register
421 #define KSZ8864_ID_REVISION_ID 0xF0
422 #define KSZ8864_ID_REVISION_ID_CNX_REV_A2 0x40
423 #define KSZ8864_ID_REVISION_ID_RMNUB_REV_B2 0x40
424 #define KSZ8864_ID_REVISION_ID_CNX_REV_A3 0x50
425 #define KSZ8864_ID_REVISION_ID_CNX_REV_A4 0x60
426 
427 //Tail tag encoding
428 #define KSZ8864_TAIL_TAG_ENCODE(port) (0x40 | (1 << ((port) & 0x03)))
429 //Tail tag decoding
430 #define KSZ8864_TAIL_TAG_DECODE(tag) ((tag) & 0x03)
431 
432 //C++ guard
433 #ifdef __cplusplus
434 extern "C" {
435 #endif
436 
437 //KSZ8864 Ethernet switch driver
438 extern const PhyDriver ksz8864PhyDriver;
439 
440 //KSZ8864 related functions
441 error_t ksz8864Init(NetInterface *interface);
442 
443 bool_t ksz8864GetLinkState(NetInterface *interface, uint8_t port);
444 
445 void ksz8864Tick(NetInterface *interface);
446 
447 void ksz8864EnableIrq(NetInterface *interface);
448 void ksz8864DisableIrq(NetInterface *interface);
449 
450 void ksz8864EventHandler(NetInterface *interface);
451 
452 error_t ksz8864TagFrame(NetInterface *interface, NetBuffer *buffer,
453  size_t *offset, uint8_t port, uint16_t *type);
454 
455 error_t ksz8864UntagFrame(NetInterface *interface, uint8_t **frame,
456  size_t *length, uint8_t *port);
457 
458 void ksz8864WritePhyReg(NetInterface *interface, uint8_t port,
459  uint8_t address, uint16_t data);
460 
461 uint16_t ksz8864ReadPhyReg(NetInterface *interface, uint8_t port,
462  uint8_t address);
463 
464 void ksz8864DumpPhyReg(NetInterface *interface, uint8_t port);
465 
466 void ksz8864WriteSwitchReg(NetInterface *interface, uint8_t address,
467  uint8_t data);
468 
469 uint8_t ksz8864ReadSwitchReg(NetInterface *interface, uint8_t address);
470 
471 void ksz8864DumpSwitchReg(NetInterface *interface);
472 
473 //C++ guard
474 #ifdef __cplusplus
475 }
476 #endif
477 
478 #endif
uint8_t length
Definition: dtls_misc.h:149
int bool_t
Definition: compiler_port.h:49
void ksz8864EnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t ksz8864ReadSwitchReg(NetInterface *interface, uint8_t address)
Read switch register.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
PHY driver.
Definition: nic.h:214
void ksz8864Tick(NetInterface *interface)
KSZ8864 timer handler.
error_t ksz8864TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
void ksz8864EventHandler(NetInterface *interface)
KSZ8864 event handler.
void ksz8864DisableIrq(NetInterface *interface)
Disable interrupts.
char_t type
error_t
Error codes.
Definition: error.h:42
uint16_t ksz8864ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
error_t ksz8864UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
#define NetInterface
Definition: net.h:36
bool_t ksz8864GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
uint16_t port
Definition: dns_common.h:223
Network interface controller abstraction layer.
void ksz8864WriteSwitchReg(NetInterface *interface, uint8_t address, uint8_t data)
Write switch register.
Ipv6Addr address
void ksz8864DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
uint8_t data[]
Definition: dtls_misc.h:176
void ksz8864WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
error_t ksz8864Init(NetInterface *interface)
KSZ8864 Ethernet switch initialization.
const PhyDriver ksz8864PhyDriver
KSZ8864 Ethernet switch driver.
void ksz8864DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.