ksz8873_driver.h
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1 /**
2  * @file ksz8873_driver.h
3  * @brief KSZ8873 3-port Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _KSZ8873_DRIVER_H
32 #define _KSZ8873_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //KSZ8873 ports
38 #define KSZ8873_PORT1 1
39 #define KSZ8873_PORT2 2
40 
41 //SPI command byte
42 #define KSZ8873_SPI_CMD_WRITE 0x02
43 #define KSZ8873_SPI_CMD_READ 0x03
44 
45 //KSZ8873 PHY registers
46 #define KSZ8873_BMCR 0x00
47 #define KSZ8873_BMSR 0x01
48 #define KSZ8873_PHYID1 0x02
49 #define KSZ8873_PHYID2 0x03
50 #define KSZ8873_ANAR 0x04
51 #define KSZ8873_ANLPAR 0x05
52 #define KSZ8873_LINKMD 0x1D
53 #define KSZ8873_PHYSCS 0x1F
54 
55 //KSZ8873 Switch registers
56 #define KSZ8873_CHIP_ID0 0x00
57 #define KSZ8873_CHIP_ID1 0x01
58 #define KSZ8873_GLOBAL_CTRL0 0x02
59 #define KSZ8873_GLOBAL_CTRL1 0x03
60 #define KSZ8873_GLOBAL_CTRL2 0x04
61 #define KSZ8873_GLOBAL_CTRL3 0x05
62 #define KSZ8873_GLOBAL_CTRL4 0x06
63 #define KSZ8873_GLOBAL_CTRL5 0x07
64 #define KSZ8873_GLOBAL_CTRL6 0x08
65 #define KSZ8873_GLOBAL_CTRL7 0x09
66 #define KSZ8873_GLOBAL_CTRL8 0x0A
67 #define KSZ8873_GLOBAL_CTRL9 0x0B
68 #define KSZ8873_GLOBAL_CTRL10 0x0C
69 #define KSZ8873_GLOBAL_CTRL11 0x0D
70 #define KSZ8873_GLOBAL_CTRL12 0x0E
71 #define KSZ8873_GLOBAL_CTRL13 0x0F
72 #define KSZ8873_PORT1_CTRL0 0x10
73 #define KSZ8873_PORT1_CTRL1 0x11
74 #define KSZ8873_PORT1_CTRL2 0x12
75 #define KSZ8873_PORT1_CTRL3 0x13
76 #define KSZ8873_PORT1_CTRL4 0x14
77 #define KSZ8873_PORT1_CTRL5 0x15
78 #define KSZ8873_PORT1_Q0_IG_LIMIT 0x16
79 #define KSZ8873_PORT1_Q1_IG_LIMIT 0x17
80 #define KSZ8873_PORT1_Q2_IG_LIMIT 0x18
81 #define KSZ8873_PORT1_Q3_IG_LIMIT 0x19
82 #define KSZ8873_PORT1_PSCS 0x1A
83 #define KSZ8873_PORT1_LINKMD 0x1B
84 #define KSZ8873_PORT1_CTRL12 0x1C
85 #define KSZ8873_PORT1_CTRL13 0x1D
86 #define KSZ8873_PORT1_STAT0 0x1E
87 #define KSZ8873_PORT1_STAT1 0x1F
88 #define KSZ8873_PORT2_CTRL0 0x20
89 #define KSZ8873_PORT2_CTRL1 0x21
90 #define KSZ8873_PORT2_CTRL2 0x22
91 #define KSZ8873_PORT2_CTRL3 0x23
92 #define KSZ8873_PORT2_CTRL4 0x24
93 #define KSZ8873_PORT2_CTRL5 0x25
94 #define KSZ8873_PORT2_Q0_IG_LIMIT 0x26
95 #define KSZ8873_PORT2_Q1_IG_LIMIT 0x27
96 #define KSZ8873_PORT2_Q2_IG_LIMIT 0x28
97 #define KSZ8873_PORT2_Q3_IG_LIMIT 0x29
98 #define KSZ8873_PORT2_PSCS 0x2A
99 #define KSZ8873_PORT2_LINKMD 0x2B
100 #define KSZ8873_PORT2_CTRL12 0x2C
101 #define KSZ8873_PORT2_CTRL13 0x2D
102 #define KSZ8873_PORT2_STAT0 0x2E
103 #define KSZ8873_PORT2_STAT1 0x2F
104 #define KSZ8873_PORT3_CTRL0 0x30
105 #define KSZ8873_PORT3_CTRL1 0x31
106 #define KSZ8873_PORT3_CTRL2 0x32
107 #define KSZ8873_PORT3_CTRL3 0x33
108 #define KSZ8873_PORT3_CTRL4 0x34
109 #define KSZ8873_PORT3_CTRL5 0x35
110 #define KSZ8873_PORT3_Q0_IG_LIMIT 0x36
111 #define KSZ8873_PORT3_Q1_IG_LIMIT 0x37
112 #define KSZ8873_PORT3_Q2_IG_LIMIT 0x38
113 #define KSZ8873_PORT3_Q3_IG_LIMIT 0x39
114 #define KSZ8873_PORT3_STAT0 0x3E
115 #define KSZ8873_PORT3_STAT1 0x3F
116 #define KSZ8873_RESET 0x43
117 #define KSZ8873_TOS_PRIO_CTRL0 0x60
118 #define KSZ8873_TOS_PRIO_CTRL1 0x61
119 #define KSZ8873_TOS_PRIO_CTRL2 0x62
120 #define KSZ8873_TOS_PRIO_CTRL3 0x63
121 #define KSZ8873_TOS_PRIO_CTRL4 0x64
122 #define KSZ8873_TOS_PRIO_CTRL5 0x65
123 #define KSZ8873_TOS_PRIO_CTRL6 0x66
124 #define KSZ8873_TOS_PRIO_CTRL7 0x67
125 #define KSZ8873_TOS_PRIO_CTRL8 0x68
126 #define KSZ8873_TOS_PRIO_CTRL9 0x69
127 #define KSZ8873_TOS_PRIO_CTRL10 0x6A
128 #define KSZ8873_TOS_PRIO_CTRL11 0x6B
129 #define KSZ8873_TOS_PRIO_CTRL12 0x6C
130 #define KSZ8873_TOS_PRIO_CTRL13 0x6D
131 #define KSZ8873_TOS_PRIO_CTRL14 0x6E
132 #define KSZ8873_TOS_PRIO_CTRL15 0x6F
133 #define KSZ8873_MAC_ADDR0 0x70
134 #define KSZ8873_MAC_ADDR1 0x71
135 #define KSZ8873_MAC_ADDR2 0x72
136 #define KSZ8873_MAC_ADDR3 0x73
137 #define KSZ8873_MAC_ADDR4 0x74
138 #define KSZ8873_MAC_ADDR5 0x75
139 #define KSZ8873_UDR1 0x76
140 #define KSZ8873_UDR2 0x77
141 #define KSZ8873_UDR3 0x78
142 #define KSZ8873_IND_ACCESS_CTRL0 0x79
143 #define KSZ8873_IND_ACCESS_CTRL1 0x7A
144 #define KSZ8873_IND_DATA8 0x7B
145 #define KSZ8873_IND_DATA7 0x7C
146 #define KSZ8873_IND_DATA6 0x7D
147 #define KSZ8873_IND_DATA5 0x7E
148 #define KSZ8873_IND_DATA4 0x7F
149 #define KSZ8873_IND_DATA3 0x80
150 #define KSZ8873_IND_DATA2 0x81
151 #define KSZ8873_IND_DATA1 0x82
152 #define KSZ8873_IND_DATA0 0x83
153 #define KSZ8873_MACA1 0x8E
154 #define KSZ8873_MACA2 0x94
155 #define KSZ8873_PORT1_Q0_EG_LIMIT 0x9A
156 #define KSZ8873_PORT1_Q1_EG_LIMIT 0x9B
157 #define KSZ8873_PORT1_Q2_EG_LIMIT 0x9C
158 #define KSZ8873_PORT1_Q3_EG_LIMIT 0x9D
159 #define KSZ8873_PORT2_Q0_EG_LIMIT 0x9E
160 #define KSZ8873_PORT2_Q1_EG_LIMIT 0x9F
161 #define KSZ8873_PORT2_Q2_EG_LIMIT 0xA0
162 #define KSZ8873_PORT2_Q3_EG_LIMIT 0xA1
163 #define KSZ8873_PORT3_Q0_EG_LIMIT 0xA2
164 #define KSZ8873_PORT3_Q1_EG_LIMIT 0xA3
165 #define KSZ8873_PORT3_Q2_EG_LIMIT 0xA4
166 #define KSZ8873_PORT3_Q3_EG_LIMIT 0xA5
167 #define KSZ8873_MODE_INDICATOR 0xA6
168 #define KSZ8873_HIGH_PRIO_PKT_BUF_Q3 0xA7
169 #define KSZ8873_HIGH_PRIO_PKT_BUF_Q2 0xA8
170 #define KSZ8873_HIGH_PRIO_PKT_BUF_Q1 0xA9
171 #define KSZ8873_HIGH_PRIO_PKT_BUF_Q0 0xAA
172 #define KSZ8873_PM_USAGE_FLOW_CTRL_SEL_MODE1 0xAB
173 #define KSZ8873_PM_USAGE_FLOW_CTRL_SEL_MODE2 0xAC
174 #define KSZ8873_PM_USAGE_FLOW_CTRL_SEL_MODE3 0xAD
175 #define KSZ8873_PM_USAGE_FLOW_CTRL_SEL_MODE4 0xAE
176 #define KSZ8873_PORT1_Q3_TXQ_SPLIT 0xAF
177 #define KSZ8873_PORT1_Q2_TXQ_SPLIT 0xB0
178 #define KSZ8873_PORT1_Q1_TXQ_SPLIT 0xB1
179 #define KSZ8873_PORT1_Q0_TXQ_SPLIT 0xB2
180 #define KSZ8873_PORT2_Q3_TXQ_SPLIT 0xB3
181 #define KSZ8873_PORT2_Q2_TXQ_SPLIT 0xB4
182 #define KSZ8873_PORT2_Q1_TXQ_SPLIT 0xB5
183 #define KSZ8873_PORT2_Q0_TXQ_SPLIT 0xB6
184 #define KSZ8873_PORT3_Q3_TXQ_SPLIT 0xB7
185 #define KSZ8873_PORT3_Q2_TXQ_SPLIT 0xB8
186 #define KSZ8873_PORT3_Q1_TXQ_SPLIT 0xB9
187 #define KSZ8873_PORT3_Q0_TXQ_SPLIT 0xBA
188 #define KSZ8873_INT_EN 0xBB
189 #define KSZ8873_LINK_CHANGE_INT 0xBC
190 #define KSZ8873_FORCE_PAUSE_OFF_LIMIT_EN 0xBD
191 #define KSZ8873_FIBER_SIGNAL_THRESHOLD 0xC0
192 #define KSZ8873_INTERNAL_LDO_CTRL 0xC1
193 #define KSZ8873_INSERT_SRC_PVID 0xC2
194 #define KSZ8873_PWR_MGMT_LED_MODE 0xC3
195 #define KSZ8873_SLEEP_MODE 0xC4
196 #define KSZ8873_FWD_INVALID_VID_FRAME_HOST_MODE 0xC6
197 
198 //KSZ8873 Switch register access macros
199 #define KSZ8873_PORTn_CTRL0(port) (0x00 + ((port) * 0x10))
200 #define KSZ8873_PORTn_CTRL1(port) (0x01 + ((port) * 0x10))
201 #define KSZ8873_PORTn_CTRL2(port) (0x02 + ((port) * 0x10))
202 #define KSZ8873_PORTn_CTRL3(port) (0x03 + ((port) * 0x10))
203 #define KSZ8873_PORTn_CTRL4(port) (0x04 + ((port) * 0x10))
204 #define KSZ8873_PORTn_CTRL5(port) (0x05 + ((port) * 0x10))
205 #define KSZ8873_PORTn_Q0_IG_LIMIT(port) (0x06 + ((port) * 0x10))
206 #define KSZ8873_PORTn_Q1_IG_LIMIT(port) (0x07 + ((port) * 0x10))
207 #define KSZ8873_PORTn_Q2_IG_LIMIT(port) (0x08 + ((port) * 0x10))
208 #define KSZ8873_PORTn_Q3_IG_LIMIT(port) (0x09 + ((port) * 0x10))
209 #define KSZ8873_PORTn_PSCS(port) (0x0A + ((port) * 0x10))
210 #define KSZ8873_PORTn_LINKMD(port) (0x0B + ((port) * 0x10))
211 #define KSZ8873_PORTn_CTRL12(port) (0x0C + ((port) * 0x10))
212 #define KSZ8873_PORTn_CTRL13(port) (0x0D + ((port) * 0x10))
213 #define KSZ8873_PORTn_STAT0(port) (0x0E + ((port) * 0x10))
214 #define KSZ8873_PORTn_STAT1(port) (0x0F + ((port) * 0x10))
215 #define KSZ8873_PORTn_Q0_EG_LIMIT(port) (0x96 + ((port) * 0x04))
216 #define KSZ8873_PORTn_Q1_EG_LIMIT(port) (0x97 + ((port) * 0x04))
217 #define KSZ8873_PORTn_Q2_EG_LIMIT(port) (0x98 + ((port) * 0x04))
218 #define KSZ8873_PORTn_Q3_EG_LIMIT(port) (0x99 + ((port) * 0x04))
219 #define KSZ8873_PORTn_Q3_TXQ_SPLIT(port) (0xAB + ((port) * 0x04))
220 #define KSZ8873_PORTn_Q2_TXQ_SPLIT(port) (0xAC + ((port) * 0x04))
221 #define KSZ8873_PORTn_Q1_TXQ_SPLIT(port) (0xAD + ((port) * 0x04))
222 #define KSZ8873_PORTn_Q0_TXQ_SPLIT(port) (0xAE + ((port) * 0x04))
223 
224 //MII Basic Control register
225 #define KSZ8873_BMCR_RESET 0x8000
226 #define KSZ8873_BMCR_LOOPBACK 0x4000
227 #define KSZ8873_BMCR_FORCE_100 0x2000
228 #define KSZ8873_BMCR_AN_EN 0x1000
229 #define KSZ8873_BMCR_POWER_DOWN 0x0800
230 #define KSZ8873_BMCR_ISOLATE 0x0400
231 #define KSZ8873_BMCR_RESTART_AN 0x0200
232 #define KSZ8873_BMCR_FORCE_FULL_DUPLEX 0x0100
233 #define KSZ8873_BMCR_COL_TEST 0x0080
234 #define KSZ8873_BMCR_HP_MDIX 0x0020
235 #define KSZ8873_BMCR_FORCE_MDI 0x0010
236 #define KSZ8873_BMCR_AUTO_MDIX_DIS 0x0008
237 #define KSZ8873_BMCR_FAR_END_FAULT_DIS 0x0004
238 #define KSZ8873_BMCR_TRANSMIT_DIS 0x0002
239 #define KSZ8873_BMCR_LED_DIS 0x0001
240 
241 //MII Basic Status register
242 #define KSZ8873_BMSR_100BT4 0x8000
243 #define KSZ8873_BMSR_100BTX_FD 0x4000
244 #define KSZ8873_BMSR_100BTX_HD 0x2000
245 #define KSZ8873_BMSR_10BT_FD 0x1000
246 #define KSZ8873_BMSR_10BT_HD 0x0800
247 #define KSZ8873_BMSR_PREAMBLE_SUPPR 0x0040
248 #define KSZ8873_BMSR_AN_COMPLETE 0x0020
249 #define KSZ8873_BMSR_FAR_END_FAULT 0x0010
250 #define KSZ8873_BMSR_AN_CAPABLE 0x0008
251 #define KSZ8873_BMSR_LINK_STATUS 0x0004
252 #define KSZ8873_BMSR_JABBER_TEST 0x0002
253 #define KSZ8873_BMSR_EXTENDED_CAPABLE 0x0001
254 
255 //PHYID High register
256 #define KSZ8873_PHYID1_DEFAULT 0x0022
257 
258 //PHYID Low register
259 #define KSZ8873_PHYID2_DEFAULT 0x1430
260 
261 //Auto-Negotiation Advertisement Ability register
262 #define KSZ8873_ANAR_NEXT_PAGE 0x8000
263 #define KSZ8873_ANAR_REMOTE_FAULT 0x2000
264 #define KSZ8873_ANAR_PAUSE 0x0400
265 #define KSZ8873_ANAR_100BTX_FD 0x0100
266 #define KSZ8873_ANAR_100BTX_HD 0x0080
267 #define KSZ8873_ANAR_10BT_FD 0x0040
268 #define KSZ8873_ANAR_10BT_HD 0x0020
269 #define KSZ8873_ANAR_SELECTOR 0x001F
270 #define KSZ8873_ANAR_SELECTOR_DEFAULT 0x0001
271 
272 //Auto-Negotiation Link Partner Ability register
273 #define KSZ8873_ANLPAR_NEXT_PAGE 0x8000
274 #define KSZ8873_ANLPAR_LP_ACK 0x4000
275 #define KSZ8873_ANLPAR_REMOTE_FAULT 0x2000
276 #define KSZ8873_ANLPAR_PAUSE 0x0400
277 #define KSZ8873_ANLPAR_100BTX_FD 0x0100
278 #define KSZ8873_ANLPAR_100BTX_HD 0x0080
279 #define KSZ8873_ANLPAR_10BT_FD 0x0040
280 #define KSZ8873_ANLPAR_10BT_HD 0x0020
281 
282 //LinkMD Control/Status register
283 #define KSZ8873_LINKMD_TEST_EN 0x8000
284 #define KSZ8873_LINKMD_RESULT 0x6000
285 #define KSZ8873_LINKMD_SHORT 0x1000
286 #define KSZ8873_LINKMD_FAULT_COUNT 0x01FF
287 
288 //PHY Special Control/Status register
289 #define KSZ8873_PHYSCS_OP_MODE 0x0700
290 #define KSZ8873_PHYSCS_OP_MODE_AN 0x0100
291 #define KSZ8873_PHYSCS_OP_MODE_10BT_HD 0x0200
292 #define KSZ8873_PHYSCS_OP_MODE_100BTX_HD 0x0300
293 #define KSZ8873_PHYSCS_OP_MODE_10BT_FD 0x0500
294 #define KSZ8873_PHYSCS_OP_MODE_100BTX_FD 0x0600
295 #define KSZ8873_PHYSCS_OP_MODE_ISOLATE 0x0700
296 #define KSZ8873_PHYSCS_POLRVS 0x0020
297 #define KSZ8873_PHYSCS_MDIX_STATUS 0x0010
298 #define KSZ8873_PHYSCS_FORCE_LINK 0x0008
299 #define KSZ8873_PHYSCS_PWRSAVE 0x0004
300 #define KSZ8873_PHYSCS_REMOTE_LOOPBACK 0x0002
301 
302 //Chip ID0 register
303 #define KSZ8873_CHIP_ID0_FAMILY_ID 0xFF
304 #define KSZ8873_CHIP_ID0_FAMILY_ID_DEFAULT 0x88
305 
306 //Chip ID1 / Start Switch register
307 #define KSZ8873_CHIP_ID1_CHIP_ID 0xF0
308 #define KSZ8873_CHIP_ID1_CHIP_ID_DEFAULT 0x30
309 #define KSZ8873_CHIP_ID1_REVISION_ID 0x0E
310 #define KSZ8873_CHIP_ID1_START_SWITCH 0x01
311 
312 //Global Control 1 register
313 #define KSZ8873_GLOBAL_CTRL1_PASS_ALL_FRAMES 0x80
314 #define KSZ8873_GLOBAL_CTRL1_TAIL_TAG_EN 0x40
315 #define KSZ8873_GLOBAL_CTRL1_TX_FLOW_CTRL_EN 0x20
316 #define KSZ8873_GLOBAL_CTRL1_RX_FLOW_CTRL_EN 0x10
317 #define KSZ8873_GLOBAL_CTRL1_FRAME_LEN_CHECK_EN 0x08
318 #define KSZ8873_GLOBAL_CTRL1_AGING_EN 0x04
319 #define KSZ8873_GLOBAL_CTRL1_FAST_AGE_EN 0x02
320 #define KSZ8873_GLOBAL_CTRL1_AGGRESSIVE_BACK_OFF_EN 0x01
321 
322 //Port N Control 0 register
323 #define KSZ8873_PORTn_CTRL0_BCAST_STORM_PROTECT_EN 0x80
324 #define KSZ8873_PORTn_CTRL0_DIFFSERV_PRIO_CLASS_EN 0x40
325 #define KSZ8873_PORTn_CTRL0_802_1P_PRIO_CLASS_EN 0x20
326 #define KSZ8873_PORTn_CTRL0_PORT_PRIO_CLASS_EN 0x18
327 #define KSZ8873_PORTn_CTRL0_TAG_INSERTION 0x04
328 #define KSZ8873_PORTn_CTRL0_TAG_REMOVAL 0x02
329 #define KSZ8873_PORTn_CTRL0_TXQ_SPLIT_EN 0x01
330 
331 //Port N Control 1 register
332 #define KSZ8873_PORTn_CTRL1_SNIFFER_PORT 0x80
333 #define KSZ8873_PORTn_CTRL1_RECEIVE_SNIFF 0x40
334 #define KSZ8873_PORTn_CTRL1_TRANSMIT_SNIFF 0x20
335 #define KSZ8873_PORTn_CTRL1_DOUBLE_TAG 0x10
336 #define KSZ8873_PORTn_CTRL1_USER_PRIO_CEILING 0x08
337 #define KSZ8873_PORTn_CTRL1_PORT_VLAN_MEMBERSHIP 0x07
338 
339 //Port N Control 2 register
340 #define KSZ8873_PORTn_CTRL2_TWO_QUEUE_SPLIT_EN 0x80
341 #define KSZ8873_PORTn_CTRL2_INGRESS_VLAN_FILT 0x40
342 #define KSZ8873_PORTn_CTRL2_DISCARD_NON_PVID_PKT 0x20
343 #define KSZ8873_PORTn_CTRL2_FORCE_FLOW_CTRL 0x10
344 #define KSZ8873_PORTn_CTRL2_BACK_PRESSURE_EN 0x08
345 #define KSZ8873_PORTn_CTRL2_TRANSMIT_EN 0x04
346 #define KSZ8873_PORTn_CTRL2_RECEIVE_EN 0x02
347 #define KSZ8873_PORTn_CTRL2_LEARNING_DIS 0x01
348 
349 //Port N Control 3 register
350 #define KSZ8873_PORTn_CTRL3_DEFAULT_USER_PRIO 0xE0
351 #define KSZ8873_PORTn_CTRL3_DEFAULT_CFI 0x10
352 #define KSZ8873_PORTn_CTRL3_DEFAULT_VID_MSB 0x0F
353 
354 //Port N Control 4 register
355 #define KSZ8873_PORTn_CTRL4_DEFAULT_VID_LSB 0xFF
356 
357 //Port N PHY Special Control/Status register
358 #define KSZ8873_PORTn_PSCS_VCT_10M_SHORT 0x80
359 #define KSZ8873_PORTn_PSCS_VCT_RESULT 0x60
360 #define KSZ8873_PORTn_PSCS_VCT_EN 0x10
361 #define KSZ8873_PORTn_PSCS_FORCE_LNK 0x08
362 #define KSZ8873_PORTn_PSCS_REMOTE_LOOPBACK 0x02
363 #define KSZ8873_PORTn_PSCS_VCT_FAULT_COUNT_MSB 0x01
364 
365 //Port N LinkMD Result register
366 #define KSZ8873_PORTn_LINKMD_VCT_FAULT_COUNT_LSB 0xFF
367 
368 //Port N Status 0 register
369 #define KSZ8873_PORTn_STAT0_MDIX_STATUS 0x80
370 #define KSZ8873_PORTn_STAT0_AN_DONE 0x40
371 #define KSZ8873_PORTn_STAT0_LINK_GOOD 0x20
372 #define KSZ8873_PORTn_STAT0_LP_FLOW_CTRL_CAPABLE 0x10
373 #define KSZ8873_PORTn_STAT0_LP_100BTX_FD_CAPABLE 0x08
374 #define KSZ8873_PORTn_STAT0_LP_100BTX_HF_CAPABLE 0x04
375 #define KSZ8873_PORTn_STAT0_LP_10BT_FD_CAPABLE 0x02
376 #define KSZ8873_PORTn_STAT0_LP_10BT_HD_CAPABLE 0x01
377 
378 //Port N Status 1 register
379 #define KSZ8873_PORTn_STAT1_HP_MDIX 0x80
380 #define KSZ8873_PORTn_STAT1_POLRVS 0x20
381 #define KSZ8873_PORTn_STAT1_TX_FLOW_CTRL_EN 0x10
382 #define KSZ8873_PORTn_STAT1_RX_FLOW_CTRL_EN 0x08
383 #define KSZ8873_PORTn_STAT1_OP_SPEED 0x04
384 #define KSZ8873_PORTn_STAT1_OP_DUPLEX 0x02
385 #define KSZ8873_PORTn_STAT1_FAR_END_FAULT 0x01
386 
387 //Reset register
388 #define KSZ8873_RESET_SOFT_RESET 0x10
389 #define KSZ8873_RESET_PCS_RESET 0x01
390 
391 //KSZ8873 Mode Indicator register
392 #define KSZ8873_MODE_INDICATOR_FLL 0x41
393 #define KSZ8873_MODE_INDICATOR_MLL 0x43
394 #define KSZ8873_MODE_INDICATOR_RLL 0x53
395 
396 //Tail tag encoding
397 #define KSZ8873_TAIL_TAG_ENCODE(port) ((port) & 0x03)
398 //Tail tag decoding
399 #define KSZ8873_TAIL_TAG_DECODE(tag) (((tag) & 0x01) + 1)
400 
401 //C++ guard
402 #ifdef __cplusplus
403 extern "C" {
404 #endif
405 
406 //KSZ8873 Ethernet switch driver
407 extern const PhyDriver ksz8873PhyDriver;
408 
409 //KSZ8873 related functions
410 error_t ksz8873Init(NetInterface *interface);
411 
412 bool_t ksz8873GetLinkState(NetInterface *interface, uint8_t port);
413 
414 void ksz8873Tick(NetInterface *interface);
415 
416 void ksz8873EnableIrq(NetInterface *interface);
417 void ksz8873DisableIrq(NetInterface *interface);
418 
419 void ksz8873EventHandler(NetInterface *interface);
420 
421 error_t ksz8873TagFrame(NetInterface *interface, NetBuffer *buffer,
422  size_t *offset, uint8_t port, uint16_t *type);
423 
424 error_t ksz8873UntagFrame(NetInterface *interface, uint8_t **frame,
425  size_t *length, uint8_t *port);
426 
427 void ksz8873WritePhyReg(NetInterface *interface, uint8_t port,
428  uint8_t address, uint16_t data);
429 
430 uint16_t ksz8873ReadPhyReg(NetInterface *interface, uint8_t port,
431  uint8_t address);
432 
433 void ksz8873DumpPhyReg(NetInterface *interface, uint8_t port);
434 
435 void ksz8873WriteSwitchReg(NetInterface *interface, uint8_t address,
436  uint8_t data);
437 
438 uint8_t ksz8873ReadSwitchReg(NetInterface *interface, uint8_t address);
439 
440 void ksz8873DumpSwitchReg(NetInterface *interface);
441 
442 //C++ guard
443 #ifdef __cplusplus
444 }
445 #endif
446 
447 #endif
uint8_t length
Definition: dtls_misc.h:149
void ksz8873WriteSwitchReg(NetInterface *interface, uint8_t address, uint8_t data)
Write switch register.
int bool_t
Definition: compiler_port.h:49
void ksz8873EventHandler(NetInterface *interface)
KSZ8873 event handler.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
error_t ksz8873TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
PHY driver.
Definition: nic.h:214
uint8_t ksz8873ReadSwitchReg(NetInterface *interface, uint8_t address)
Read switch register.
const PhyDriver ksz8873PhyDriver
KSZ8873 Ethernet switch driver.
void ksz8873DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
char_t type
error_t
Error codes.
Definition: error.h:42
void ksz8873DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
#define NetInterface
Definition: net.h:36
error_t ksz8873Init(NetInterface *interface)
KSZ8873 Ethernet switch initialization.
bool_t ksz8873GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void ksz8873EnableIrq(NetInterface *interface)
Enable interrupts.
void ksz8873WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
error_t ksz8873UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
uint16_t port
Definition: dns_common.h:223
void ksz8873DisableIrq(NetInterface *interface)
Disable interrupts.
Network interface controller abstraction layer.
Ipv6Addr address
uint16_t ksz8873ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
uint8_t data[]
Definition: dtls_misc.h:176
void ksz8873Tick(NetInterface *interface)
KSZ8873 timer handler.