ksz9477_driver.h
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1 /**
2  * @file ksz9477_driver.h
3  * @brief KSZ9477 Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.2
29  **/
30 
31 #ifndef _KSZ9477_DRIVER_H
32 #define _KSZ9477_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //KSZ9477 ports
38 #define KSZ9477_PORT1 1
39 #define KSZ9477_PORT2 2
40 #define KSZ9477_PORT3 3
41 #define KSZ9477_PORT4 4
42 #define KSZ9477_PORT5 5
43 
44 //SPI command byte
45 #define KSZ9477_SPI_CMD_WRITE 0x40000000
46 #define KSZ9477_SPI_CMD_READ 0x60000000
47 #define KSZ9477_SPI_CMD_ADDR 0x001FFFE0
48 
49 //KSZ9477 PHY registers
50 #define KSZ9477_PHY_REG_BMCR 0x00
51 #define KSZ9477_PHY_REG_BMSR 0x01
52 #define KSZ9477_PHY_REG_PHYIDR1 0x02
53 #define KSZ9477_PHY_REG_PHYIDR2 0x03
54 #define KSZ9477_PHY_REG_ANAR 0x04
55 #define KSZ9477_PHY_REG_ANLPAR 0x05
56 #define KSZ9477_PHY_REG_ANER 0x06
57 #define KSZ9477_PHY_REG_ANNPTR 0x07
58 #define KSZ9477_PHY_REG_LPNPAR 0x08
59 #define KSZ9477_PHY_REG_1000BT_CTRL 0x09
60 #define KSZ9477_PHY_REG_1000BT_STATUS 0x0A
61 #define KSZ9477_PHY_REG_MMD_CTRL 0x0D
62 #define KSZ9477_PHY_REG_MMD_DATA 0x0E
63 #define KSZ9477_PHY_REG_EXT_STATUS 0x0F
64 #define KSZ9477_PHY_REG_RLB 0x11
65 #define KSZ9477_PHY_REG_LINKMDCD 0x12
66 #define KSZ9477_PHY_REG_DPMAPCSS 0x13
67 #define KSZ9477_PHY_REG_RXERCTR 0x15
68 #define KSZ9477_PHY_REG_ICSR 0x1B
69 #define KSZ9477_PHY_REG_AUTOMDI 0x1C
70 #define KSZ9477_PHY_REG_PHYCON 0x1F
71 
72 //BMCR register
73 #define BMCR_SOFT_RESET (1 << 15)
74 #define BMCR_LOOPBACK (1 << 14)
75 #define BMCR_SPEED_SEL_LSB (1 << 13)
76 #define BMCR_AN_EN (1 << 12)
77 #define BMCR_POWER_DOWN (1 << 11)
78 #define BMCR_ISOLATE (1 << 10)
79 #define BMCR_RESTART_AN (1 << 9)
80 #define BMCR_DUPLEX_MODE (1 << 8)
81 #define BMCR_COL_TEST (1 << 7)
82 #define BMCR_SPEED_SEL_MSB (1 << 6)
83 
84 //BMSR register
85 #define BMSR_100BT4 (1 << 15)
86 #define BMSR_100BTX_FD (1 << 14)
87 #define BMSR_100BTX_HD (1 << 13)
88 #define BMSR_10BT_FD (1 << 12)
89 #define BMSR_10BT_HD (1 << 11)
90 #define BMSR_EXTENDED_STATUS (1 << 8)
91 #define BMSR_MF_PREAMBLE_SUPPR (1 << 6)
92 #define BMSR_AN_COMPLETE (1 << 5)
93 #define BMSR_REMOTE_FAULT (1 << 4)
94 #define BMSR_AN_ABLE (1 << 3)
95 #define BMSR_LINK_STATUS (1 << 2)
96 #define BMSR_JABBER_DETECT (1 << 1)
97 #define BMSR_EXTENDED_CAP (1 << 0)
98 
99 //ANAR register
100 #define ANAR_NEXT_PAGE (1 << 15)
101 #define ANAR_REMOTE_FAULT (1 << 13)
102 #define ANAR_PAUSE1 (1 << 11)
103 #define ANAR_PAUSE0 (1 << 10)
104 #define ANAR_100BT4 (1 << 9)
105 #define ANAR_100BTX_FD (1 << 8)
106 #define ANAR_100BTX_HD (1 << 7)
107 #define ANAR_10BT_FD (1 << 6)
108 #define ANAR_10BT_HD (1 << 5)
109 #define ANAR_SELECTOR4 (1 << 4)
110 #define ANAR_SELECTOR3 (1 << 3)
111 #define ANAR_SELECTOR2 (1 << 2)
112 #define ANAR_SELECTOR1 (1 << 1)
113 #define ANAR_SELECTOR0 (1 << 0)
114 
115 //ANLPAR register
116 #define ANLPAR_NEXT_PAGE (1 << 15)
117 #define ANLPAR_LP_ACK (1 << 14)
118 #define ANLPAR_REMOTE_FAULT (1 << 13)
119 #define ANLPAR_PAUSE1 (1 << 11)
120 #define ANLPAR_PAUSE0 (1 << 10)
121 #define ANLPAR_100BT4 (1 << 9)
122 #define ANLPAR_100BTX_FD (1 << 8)
123 #define ANLPAR_100BTX_HD (1 << 7)
124 #define ANLPAR_10BT_FD (1 << 6)
125 #define ANLPAR_10BT_HD (1 << 5)
126 #define ANLPAR_SELECTOR4 (1 << 4)
127 #define ANLPAR_SELECTOR3 (1 << 3)
128 #define ANLPAR_SELECTOR2 (1 << 2)
129 #define ANLPAR_SELECTOR1 (1 << 1)
130 #define ANLPAR_SELECTOR0 (1 << 0)
131 
132 //ANER register
133 #define ANER_PAR_DET_FAULT (1 << 4)
134 #define ANER_LP_NEXT_PAGE_ABLE (1 << 3)
135 #define ANER_NEXT_PAGE_ABLE (1 << 2)
136 #define ANER_PAGE_RECEIVED (1 << 1)
137 #define ANER_LP_AN_ABLE (1 << 0)
138 
139 //ANNPTR register
140 #define ANNPTR_NEXT_PAGE (1 << 15)
141 #define ANNPTR_MSG_PAGE (1 << 13)
142 #define ANNPTR_ACK2 (1 << 12)
143 #define ANNPTR_TOGGLE (1 << 11)
144 #define ANNPTR_MESSAGE10 (1 << 10)
145 #define ANNPTR_MESSAGE9 (1 << 9)
146 #define ANNPTR_MESSAGE8 (1 << 8)
147 #define ANNPTR_MESSAGE7 (1 << 7)
148 #define ANNPTR_MESSAGE6 (1 << 6)
149 #define ANNPTR_MESSAGE5 (1 << 5)
150 #define ANNPTR_MESSAGE4 (1 << 4)
151 #define ANNPTR_MESSAGE3 (1 << 3)
152 #define ANNPTR_MESSAGE2 (1 << 2)
153 #define ANNPTR_MESSAGE1 (1 << 1)
154 #define ANNPTR_MESSAGE0 (1 << 0)
155 
156 //LPNPAR register
157 #define LPNPAR_NEXT_PAGE (1 << 15)
158 #define LPNPAR_ACK (1 << 14)
159 #define LPNPAR_MSG_PAGE (1 << 13)
160 #define LPNPAR_ACK2 (1 << 12)
161 #define LPNPAR_TOGGLE (1 << 11)
162 #define LPNPAR_MESSAGE10 (1 << 10)
163 #define LPNPAR_MESSAGE9 (1 << 9)
164 #define LPNPAR_MESSAGE8 (1 << 8)
165 #define LPNPAR_MESSAGE7 (1 << 7)
166 #define LPNPAR_MESSAGE6 (1 << 6)
167 #define LPNPAR_MESSAGE5 (1 << 5)
168 #define LPNPAR_MESSAGE4 (1 << 4)
169 #define LPNPAR_MESSAGE3 (1 << 3)
170 #define LPNPAR_MESSAGE2 (1 << 2)
171 #define LPNPAR_MESSAGE1 (1 << 1)
172 #define LPNPAR_MESSAGE0 (1 << 0)
173 
174 //1000BT_CTRL register
175 #define _1000BT_CTRL_TEST_MODE2 (1 << 15)
176 #define _1000BT_CTRL_TEST_MODE1 (1 << 14)
177 #define _1000BT_CTRL_TEST_MODE0 (1 << 13)
178 #define _1000BT_CTRL_MS_MAN_CONF_EN (1 << 12)
179 #define _1000BT_CTRL_MS_MAN_CONF_VAL (1 << 11)
180 #define _1000BT_CTRL_PORT_TYPE (1 << 10)
181 #define _1000BT_CTRL_1000BT_FD (1 << 9)
182 #define _1000BT_CTRL_1000BT_HD (1 << 8)
183 
184 //1000BT_STATUS register
185 #define _1000BT_STATUS_MS_CONF_FAULT (1 << 15)
186 #define _1000BT_STATUS_MS_CONF_RES (1 << 14)
187 #define _1000BT_STATUS_LOC_REC_STATUS (1 << 13)
188 #define _1000BT_STATUS_REM_REC_STATUS (1 << 12)
189 #define _1000BT_STATUS_LP_1000BT_FD (1 << 11)
190 #define _1000BT_STATUS_LP_1000BT_HD (1 << 10)
191 #define _1000BT_STATUS_IDLE_ERR_CTR7 (1 << 7)
192 #define _1000BT_STATUS_IDLE_ERR_CTR6 (1 << 6)
193 #define _1000BT_STATUS_IDLE_ERR_CTR5 (1 << 5)
194 #define _1000BT_STATUS_IDLE_ERR_CTR4 (1 << 4)
195 #define _1000BT_STATUS_IDLE_ERR_CTR3 (1 << 3)
196 #define _1000BT_STATUS_IDLE_ERR_CTR2 (1 << 2)
197 #define _1000BT_STATUS_IDLE_ERR_CTR1 (1 << 1)
198 #define _1000BT_STATUS_IDLE_ERR_CTR0 (1 << 0)
199 
200 //MMD_CTRL register
201 #define MMD_CTRL_DEVICE_OP_MODE1 (1 << 15)
202 #define MMD_CTRL_DEVICE_OP_MODE0 (1 << 14)
203 #define MMD_CTRL_DEVICE_ADDR4 (1 << 4)
204 #define MMD_CTRL_DEVICE_ADDR3 (1 << 3)
205 #define MMD_CTRL_DEVICE_ADDR2 (1 << 2)
206 #define MMD_CTRL_DEVICE_ADDR1 (1 << 1)
207 #define MMD_CTRL_DEVICE_ADDR0 (1 << 0)
208 
209 //EXT_STATUS register
210 #define EXT_STATUS_1000BX_FD (1 << 15)
211 #define EXT_STATUS_1000BX_HD (1 << 14)
212 #define EXT_STATUS_1000BT_FD (1 << 13)
213 #define EXT_STATUS_1000BT_HD (1 << 12)
214 
215 //RLB register
216 #define RLB_REMOTE_LOOPBACK (1 << 8)
217 
218 //LINKMDCD register
219 #define LINKMDCD_CDT_EN (1 << 15)
220 #define LINKMDCD_CDT_PAIR1 (1 << 13)
221 #define LINKMDCD_CDT_PAIR0 (1 << 12)
222 #define LINKMDCD_CDT_STATUS1 (1 << 9)
223 #define LINKMDCD_CDT_STATUS0 (1 << 8)
224 #define LINKMDCD_CDT_RESULT7 (1 << 7)
225 #define LINKMDCD_CDT_RESULT6 (1 << 6)
226 #define LINKMDCD_CDT_RESULT5 (1 << 5)
227 #define LINKMDCD_CDT_RESULT4 (1 << 4)
228 #define LINKMDCD_CDT_RESULT3 (1 << 3)
229 #define LINKMDCD_CDT_RESULT2 (1 << 2)
230 #define LINKMDCD_CDT_RESULT1 (1 << 1)
231 #define LINKMDCD_CDT_RESULT0 (1 << 0)
232 
233 //DPMAPCSS register
234 #define DPMAPCSS_1000BT_LINK_STATUS (1 << 2)
235 #define DPMAPCSS_100BTX_LINK_STATUS (1 << 1)
236 
237 //ICSR register
238 #define ICSR_JABBER_IE (1 << 15)
239 #define ICSR_RECEIVE_ERROR_IE (1 << 14)
240 #define ICSR_PAGE_RECEIVED_IE (1 << 13)
241 #define ICSR_PAR_DET_FAULT_IE (1 << 12)
242 #define ICSR_LP_ACK_IE (1 << 11)
243 #define ICSR_LINK_DOWN_IE (1 << 10)
244 #define ICSR_REMOTE_FAULT_IE (1 << 9)
245 #define ICSR_LINK_UP_IE (1 << 8)
246 #define ICSR_JABBER_IF (1 << 7)
247 #define ICSR_RECEIVE_ERROR_IF (1 << 6)
248 #define ICSR_PAGE_RECEIVED_IF (1 << 5)
249 #define ICSR_PAR_DET_FAULT_IF (1 << 4)
250 #define ICSR_LP_ACK_IF (1 << 3)
251 #define ICSR_LINK_DOWN_IF (1 << 2)
252 #define ICSR_REMOTE_FAULT_IF (1 << 1)
253 #define ICSR_LINK_UP_IF (1 << 0)
254 
255 //AUTOMDI register
256 #define AUTOMDI_MDI_SEL (1 << 7)
257 #define AUTOMDI_SWAP_OFF (1 << 6)
258 
259 //PHYCON register
260 #define PHYCON_JABBER_EN (1 << 9)
261 #define PHYCON_SPEED_1000BT (1 << 6)
262 #define PHYCON_SPEED_100BTX (1 << 5)
263 #define PHYCON_SPEED_10BT (1 << 4)
264 #define PHYCON_DUPLEX_STATUS (1 << 3)
265 #define PHYCON_1000BT_MS_STATUS (1 << 2)
266 
267 //KSZ9477 switch registers
268 #define KSZ9477_SW_REG_CHIP_ID0 0x0000
269 #define KSZ9477_SW_REG_CHIP_ID1 0x0001
270 #define KSZ9477_SW_REG_CHIP_ID2 0x0002
271 #define KSZ9477_SW_REG_CHIP_ID3 0x0003
272 #define KSZ9477_SW_REG_SWITCH_OP 0x0300
273 #define KSZ9477_SW_REG_PORT_OP_CTRL0(n) (0x0020 + ((n) * 0x1000))
274 #define KSZ9477_SW_REG_XMII_PORT_CTRL0(n) (0x0300 + ((n) * 0x1000))
275 #define KSZ9477_SW_REG_XMII_PORT_CTRL1(n) (0x0301 + ((n) * 0x1000))
276 #define KSZ9477_SW_REG_PORT_MSTP_STATE(n) (0x0B04 + ((n) * 0x1000))
277 
278 //Chip ID1 register
279 #define CHIP_ID1_CHIP_ID_MSB 0xFF
280 #define CHIP_ID1_CHIP_ID_MSB_DEFAULT 0x94
281 
282 //Chip ID2 register
283 #define CHIP_ID2_CHIP_ID_LSB 0xFF
284 #define CHIP_ID2_CHIP_ID_LSB_DEFAULT 0x77
285 
286 //Switch operation register
287 #define SWITCH_OP_DOUBLE_TAG_EN (1 << 7)
288 #define SWITCH_OP_SOFT_RESET (1 << 1)
289 #define SWITCH_OP_START_SWITCH (1 << 0)
290 
291 //Port operation control 0 register
292 #define PORT_OP_CTRL0_LOCAL_LOOPBACK (1 << 7)
293 #define PORT_OP_CTRL0_REMOTE_LOOPBACK (1 << 6)
294 #define PORT_OP_CTRL0_TAIL_TAG_EN (1 << 2)
295 #define PORT_OP_CTRL0_TX_QUEUE_SPLIT_EN1 (1 << 1)
296 #define PORT_OP_CTRL0_TX_QUEUE_SPLIT_EN0 (1 << 0)
297 
298 //XMII port control 0 register
299 #define XMII_PORT_CTRL0_PORT_DUPLEX (1 << 6)
300 #define XMII_PORT_CTRL0_PORT_TX_FLOW_CTRL_EN (1 << 5)
301 #define XMII_PORT_CTRL0_PORT_SPEED_10_100 (1 << 4)
302 #define XMII_PORT_CTRL0_PORT_RX_FLOW_CTRL_EN (1 << 3)
303 
304 //XMII port control 1 register
305 #define XMII_PORT_CTRL1_PORT_SPEED_1000 (1 << 6)
306 #define XMII_PORT_CTRL1_RGMII_ID_IG (1 << 4)
307 #define XMII_PORT_CTRL1_RGMII_ID_EG (1 << 3)
308 #define XMII_PORT_CTRL1_MII_RMII_MODE (1 << 2)
309 #define XMII_PORT_CTRL1_PORT_IF_TYPE1 (1 << 1)
310 #define XMII_PORT_CTRL1_PORT_IF_TYPE0 (1 << 0)
311 
312 //Port MSTP state register
313 #define PORT_MSTP_STATE_TRANSMIT_EN (1 << 2)
314 #define PORT_MSTP_STATE_RECEIVE_EN (1 << 1)
315 #define PORT_MSTP_STATE_LEARNING_DIS (1 << 0)
316 
317 //KSZ9477 PHY registers
318 #define KSZ9477_SW_REG_PORT_ETH_PHY(n, a) (0x0100 + ((n) * 0x1000) + ((a) * 2))
319 
320 //Tail tag encoding
321 #define KSZ9477_TAIL_TAG_ENCODE(port) HTONS(0x0200 | (1 << (((port) - 1) & 0x0007)))
322 //Tail tag decoding
323 #define KSZ9477_TAIL_TAG_DECODE(tag) (((tag) & 0x07) + 1)
324 
325 //C++ guard
326 #ifdef __cplusplus
327  extern "C" {
328 #endif
329 
330 //KSZ9477 Ethernet switch driver
331 extern const PhyDriver ksz9477PhyDriver;
332 
333 //KSZ9477 related functions
334 error_t ksz9477Init(NetInterface *interface);
335 
336 bool_t ksz9477GetLinkState(NetInterface *interface, uint8_t port);
337 
338 void ksz9477Tick(NetInterface *interface);
339 
340 void ksz9477EnableIrq(NetInterface *interface);
341 void ksz9477DisableIrq(NetInterface *interface);
342 
343 void ksz9477EventHandler(NetInterface *interface);
344 
345 error_t ksz9477TagFrame(NetInterface *interface, NetBuffer *buffer,
346  size_t *offset, uint8_t port, uint16_t *type);
347 
348 error_t ksz9477UntagFrame(NetInterface *interface, uint8_t **frame,
349  size_t *length, uint8_t *port);
350 
351 void ksz9477WritePhyReg(NetInterface *interface, uint8_t port,
352  uint8_t address, uint16_t data);
353 
354 uint16_t ksz9477ReadPhyReg(NetInterface *interface, uint8_t port,
355  uint8_t address);
356 
357 void ksz9477DumpPhyReg(NetInterface *interface, uint8_t port);
358 
359 void ksz9477WriteSwitchReg(NetInterface *interface, uint16_t address,
360  uint8_t data);
361 
362 uint8_t ksz9477ReadSwitchReg(NetInterface *interface, uint16_t address);
363 
364 void ksz9477DumpSwitchReg(NetInterface *interface);
365 
366 //C++ guard
367 #ifdef __cplusplus
368  }
369 #endif
370 
371 #endif
bool_t ksz9477GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void ksz9477WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
error_t ksz9477Init(NetInterface *interface)
KSZ9477 Ethernet switch initialization.
void ksz9477EnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t ksz9477ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
char_t type
void ksz9477EventHandler(NetInterface *interface)
KSZ9477 event handler.
error_t ksz9477UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
PHY driver.
Definition: nic.h:199
void ksz9477DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
void ksz9477DisableIrq(NetInterface *interface)
Disable interrupts.
error_t ksz9477TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
uint16_t ksz9477ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:42
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
uint16_t port
Definition: dns_common.h:223
void ksz9477DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
const PhyDriver ksz9477PhyDriver
KSZ9477 Ethernet switch driver.
void ksz9477Tick(NetInterface *interface)
KSZ9477 timer handler.
uint8_t length
Definition: dtls_misc.h:142
void ksz9477WriteSwitchReg(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register.
int bool_t
Definition: compiler_port.h:49
Network interface controller abstraction layer.