ksz9477_driver.c
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1 /**
2  * @file ksz9477_driver.c
3  * @brief KSZ9477 7-port Gigabit Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 //Switch to the appropriate trace level
32 #define TRACE_LEVEL NIC_TRACE_LEVEL
33 
34 //Dependencies
35 #include "core/net.h"
36 #include "core/ethernet_misc.h"
38 #include "debug.h"
39 
40 
41 /**
42  * @brief KSZ9477 Ethernet switch driver
43  **/
44 
46 {
54 };
55 
56 
57 /**
58  * @brief Tail tag rules (host to KSZ9477)
59  **/
60 
61 const uint16_t ksz9477IngressTailTag[6] =
62 {
63  0,
69 };
70 
71 
72 /**
73  * @brief KSZ9477 Ethernet switch initialization
74  * @param[in] interface Underlying network interface
75  * @return Error code
76  **/
77 
79 {
80  uint_t port;
81  uint8_t temp;
82 
83  //Debug message
84  TRACE_INFO("Initializing KSZ9477...\r\n");
85 
86  //SPI slave mode?
87  if(interface->spiDriver != NULL)
88  {
89  //Initialize SPI
90  interface->spiDriver->init();
91 
92  //Wait for the serial interface to be ready
93  do
94  {
95  //Read CHIP_ID1 register
96  temp = ksz9477ReadSwitchReg(interface, KSZ9477_CHIP_ID1);
97 
98  //The returned data is invalid until the serial interface is ready
99  } while(temp != KSZ9477_CHIP_ID1_DEFAULT);
100 
101 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
102  //Tail tagging mode?
103  if(interface->port != 0)
104  {
105  //Enable tail tag feature
106  temp = ksz9477ReadSwitchReg(interface, KSZ9477_PORT6_OP_CTRL0);
109 
110  //Loop through ports
112  {
113  //Disable packet transmission and switch address learning
119  }
120  }
121  else
122 #endif
123  {
124  //Disable tail tag feature
125  temp = ksz9477ReadSwitchReg(interface, KSZ9477_PORT6_OP_CTRL0);
128 
129  //Loop through ports
131  {
132  //Enable transmission, reception and switch address learning
138  }
139  }
140 
141  //Add internal delay to ingress and egress RGMII clocks
146 
147  //Start switch operation
150  }
151 
152  //Loop through ports
154  {
155  //Debug message
156  TRACE_DEBUG("Port %u:\r\n", port);
157  //Dump PHY registers for debugging purpose
158  ksz9477DumpPhyReg(interface, port);
159  }
160 
161  //Force the TCP/IP stack to poll the link state at startup
162  interface->phyEvent = TRUE;
163  //Notify the TCP/IP stack of the event
165 
166  //Successful initialization
167  return NO_ERROR;
168 }
169 
170 
171 /**
172  * @brief Get link state
173  * @param[in] interface Underlying network interface
174  * @param[in] port Port number
175  * @return Link state
176  **/
177 
179 {
180  uint16_t value;
181  bool_t linkState;
182 
183  //Check port number
184  if(port >= KSZ9477_PORT1 && port <= KSZ9477_PORT5)
185  {
186  //Get exclusive access
188 
189  //Any link failure condition is latched in the BMSR register. Reading
190  //the register twice will always return the actual link status
191  value = ksz9477ReadPhyReg(interface, port, KSZ9477_BMSR);
192  value = ksz9477ReadPhyReg(interface, port, KSZ9477_BMSR);
193 
194  //Retrieve current link state
195  linkState = (value & KSZ9477_BMSR_LINK_STATUS) ? TRUE : FALSE;
196 
197  //Release exclusive access
199  }
200  else
201  {
202  //The specified port number is not valid
203  linkState = FALSE;
204  }
205 
206  //Return link status
207  return linkState;
208 }
209 
210 
211 /**
212  * @brief KSZ9477 timer handler
213  * @param[in] interface Underlying network interface
214  **/
215 
216 void ksz9477Tick(NetInterface *interface)
217 {
218  uint_t port;
219  uint16_t value;
220  bool_t linkState;
221 
222 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
223  //Tail tagging mode?
224  if(interface->port != 0)
225  {
226  uint_t i;
227  NetInterface *virtualInterface;
228 
229  //Loop through network interfaces
230  for(i = 0; i < NET_INTERFACE_COUNT; i++)
231  {
232  //Point to the current interface
233  virtualInterface = &netInterface[i];
234 
235  //Check whether the current virtual interface is attached to the
236  //physical interface
237  if(virtualInterface == interface || virtualInterface->parent == interface)
238  {
239  //The tail tag is used to indicate the source/destination port
240  port = virtualInterface->port;
241 
242  //Valid port?
243  if(port >= KSZ9477_PORT1 && port <= KSZ9477_PORT5)
244  {
245  //Read status register
246  value = ksz9477ReadPhyReg(interface, port, KSZ9477_BMSR);
247 
248  //Retrieve current link state
249  linkState = (value & KSZ9477_BMSR_LINK_STATUS) ? TRUE : FALSE;
250 
251  //Link up or link down event?
252  if(linkState != virtualInterface->linkState)
253  {
254  //Set event flag
255  interface->phyEvent = TRUE;
256  //Notify the TCP/IP stack of the event
258  }
259  }
260  }
261  }
262  }
263  else
264 #endif
265  {
266  //Initialize link state
267  linkState = FALSE;
268 
269  //Loop through ports
271  {
272  //Read status register
273  value = ksz9477ReadPhyReg(interface, port, KSZ9477_BMSR);
274 
275  //Retrieve current link state
277  linkState = TRUE;
278  }
279 
280  //Link up or link down event?
281  if(linkState != interface->linkState)
282  {
283  //Set event flag
284  interface->phyEvent = TRUE;
285  //Notify the TCP/IP stack of the event
287  }
288  }
289 }
290 
291 
292 /**
293  * @brief Enable interrupts
294  * @param[in] interface Underlying network interface
295  **/
296 
298 {
299 }
300 
301 
302 /**
303  * @brief Disable interrupts
304  * @param[in] interface Underlying network interface
305  **/
306 
308 {
309 }
310 
311 
312 /**
313  * @brief KSZ9477 event handler
314  * @param[in] interface Underlying network interface
315  **/
316 
318 {
319  uint_t port;
320  uint16_t value;
321  bool_t linkState;
322 
323 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
324  //Tail tagging mode?
325  if(interface->port != 0)
326  {
327  uint_t i;
328  NetInterface *virtualInterface;
329 
330  //Loop through network interfaces
331  for(i = 0; i < NET_INTERFACE_COUNT; i++)
332  {
333  //Point to the current interface
334  virtualInterface = &netInterface[i];
335 
336  //Check whether the current virtual interface is attached to the
337  //physical interface
338  if(virtualInterface == interface ||
339  virtualInterface->parent == interface)
340  {
341  //The tail tag is used to indicate the source/destination port
342  port = virtualInterface->port;
343 
344  //Valid port?
345  if(port >= KSZ9477_PORT1 && port <= KSZ9477_PORT5)
346  {
347  //Any link failure condition is latched in the BMSR register. Reading
348  //the register twice will always return the actual link status
349  value = ksz9477ReadPhyReg(interface, port, KSZ9477_BMSR);
350  value = ksz9477ReadPhyReg(interface, port, KSZ9477_BMSR);
351 
352  //Retrieve current link state
353  linkState = (value & KSZ9477_BMSR_LINK_STATUS) ? TRUE : FALSE;
354 
355  //Link up event?
356  if(linkState && !virtualInterface->linkState)
357  {
358  //Adjust MAC configuration parameters for proper operation
359  interface->linkSpeed = NIC_LINK_SPEED_1GBPS;
360  interface->duplexMode = NIC_FULL_DUPLEX_MODE;
361  interface->nicDriver->updateMacConfig(interface);
362 
363  //Read PHY control register
365 
366  //Check current speed
368  {
369  //1000BASE-T
370  virtualInterface->linkSpeed = NIC_LINK_SPEED_1GBPS;
371  }
373  {
374  //100BASE-TX
375  virtualInterface->linkSpeed = NIC_LINK_SPEED_100MBPS;
376  }
378  {
379  //10BASE-T
380  virtualInterface->linkSpeed = NIC_LINK_SPEED_10MBPS;
381  }
382  else
383  {
384  //Debug message
385  TRACE_WARNING("Invalid speed!\r\n");
386  }
387 
388  //Check current duplex mode
390  virtualInterface->duplexMode = NIC_FULL_DUPLEX_MODE;
391  else
392  virtualInterface->duplexMode = NIC_HALF_DUPLEX_MODE;
393 
394  //Update link state
395  virtualInterface->linkState = TRUE;
396 
397  //Process link state change event
398  nicNotifyLinkChange(virtualInterface);
399  }
400  //Link down event
401  else if(!linkState && virtualInterface->linkState)
402  {
403  //Update link state
404  virtualInterface->linkState = FALSE;
405 
406  //Process link state change event
407  nicNotifyLinkChange(virtualInterface);
408  }
409  }
410  }
411  }
412  }
413  else
414 #endif
415  {
416  //Initialize link state
417  linkState = FALSE;
418 
419  //Loop through ports
421  {
422  //Any link failure condition is latched in the BMSR register. Reading
423  //the register twice will always return the actual link status
424  value = ksz9477ReadPhyReg(interface, port, KSZ9477_BMSR);
425  value = ksz9477ReadPhyReg(interface, port, KSZ9477_BMSR);
426 
427  //Retrieve current link state
429  linkState = TRUE;
430  }
431 
432  //Link up event?
433  if(linkState)
434  {
435  //Adjust MAC configuration parameters for proper operation
436  interface->linkSpeed = NIC_LINK_SPEED_1GBPS;
437  interface->duplexMode = NIC_FULL_DUPLEX_MODE;
438  interface->nicDriver->updateMacConfig(interface);
439 
440  //Update link state
441  interface->linkState = TRUE;
442  }
443  else
444  {
445  //Update link state
446  interface->linkState = FALSE;
447  }
448 
449  //Process link state change event
450  nicNotifyLinkChange(interface);
451  }
452 }
453 
454 
455 /**
456  * @brief Add tail tag to Ethernet frame
457  * @param[in] interface Underlying network interface
458  * @param[in] buffer Multi-part buffer containing the payload
459  * @param[in,out] offset Offset to the first payload byte
460  * @param[in] port Switch port identifier
461  * @param[in,out] type Ethernet type
462  * @return Error code
463  **/
464 
466  size_t *offset, uint8_t port, uint16_t *type)
467 {
468 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
469  error_t error;
470  size_t length;
471  const uint16_t *tailTag;
472 
473  //Valid port?
474  if(port >= KSZ9477_PORT1 && port <= KSZ9477_PORT5)
475  {
476  //The two-byte tail tagging is used to indicate the destination port
477  tailTag = &ksz9477IngressTailTag[port];
478 
479  //Retrieve the length of the frame
480  length = netBufferGetLength(buffer) - *offset;
481 
482  //The host controller should manually add padding to the packet before
483  //inserting the tail tag
484  error = ethPadFrame(buffer, &length);
485 
486  //Check status code
487  if(!error)
488  {
489  //The tail tag is inserted at the end of the packet, just before the CRC
490  error = netBufferAppend(buffer, tailTag, sizeof(uint16_t));
491  }
492  }
493  else
494  {
495  //Invalid port identifier
496  error = ERROR_WRONG_IDENTIFIER;
497  }
498 
499  //Return status code
500  return error;
501 #else
502  //Tail tagging mode is not implemented
503  return NO_ERROR;
504 #endif
505 }
506 
507 
508 /**
509  * @brief Decode tail tag from incoming Ethernet frame
510  * @param[in] interface Underlying network interface
511  * @param[in,out] frame Pointer to the received Ethernet frame
512  * @param[in,out] length Length of the frame, in bytes
513  * @param[out] port Switch port identifier
514  * @return Error code
515  **/
516 
517 error_t ksz9477UntagFrame(NetInterface *interface, uint8_t **frame,
518  size_t *length, uint8_t *port)
519 {
520 #if (ETH_PORT_TAGGING_SUPPORT == ENABLED)
521  error_t error;
522  uint8_t *tailTag;
523 
524  //Valid Ethernet frame received?
525  if(*length >= (sizeof(EthHeader) + sizeof(uint8_t)))
526  {
527  //The tail tag is inserted at the end of the packet, just before the CRC
528  tailTag = *frame + *length - sizeof(uint8_t);
529 
530  //The one byte tail tagging is used to indicate the source port
531  *port = KSZ9477_TAIL_TAG_DECODE(*tailTag);
532 
533  //Strip tail tag from Ethernet frame
534  *length -= sizeof(uint8_t);
535 
536  //Successful processing
537  error = NO_ERROR;
538  }
539  else
540  {
541  //Drop the received frame
542  error = ERROR_INVALID_LENGTH;
543  }
544 
545  //Return status code
546  return error;
547 #else
548  //Tail tagging mode is not implemented
549  return NO_ERROR;
550 #endif
551 }
552 
553 
554 /**
555  * @brief Write PHY register
556  * @param[in] interface Underlying network interface
557  * @param[in] port Port number
558  * @param[in] address PHY register address
559  * @param[in] data Register value
560  **/
561 
562 void ksz9477WritePhyReg(NetInterface *interface, uint8_t port,
563  uint8_t address, uint16_t data)
564 {
565  uint32_t command;
566 
567  //SPI slave mode?
568  if(interface->spiDriver != NULL)
569  {
570  //Set up a write operation
571  command = KSZ9477_SPI_CMD_WRITE;
572  //Set register address
573  command |= KSZ9477_PORTn_ETH_PHY_REG(port, address) << 5;
574 
575  //Pull the CS pin low
576  interface->spiDriver->assertCs();
577 
578  //Write 32-bit command
579  interface->spiDriver->transfer((command >> 24) & 0xFF);
580  interface->spiDriver->transfer((command >> 16) & 0xFF);
581  interface->spiDriver->transfer((command >> 8) & 0xFF);
582  interface->spiDriver->transfer(command & 0xFF);
583 
584  //Write 16-bit data
585  interface->spiDriver->transfer(MSB(data));
586  interface->spiDriver->transfer(LSB(data));
587 
588  //Terminate the operation by raising the CS pin
589  interface->spiDriver->deassertCs();
590  }
591  else
592  {
593  //Write the specified PHY register
594  interface->nicDriver->writePhyReg(SMI_OPCODE_WRITE, port, address, data);
595  }
596 }
597 
598 
599 /**
600  * @brief Read PHY register
601  * @param[in] interface Underlying network interface
602  * @param[in] port Port number
603  * @param[in] address PHY register address
604  * @return Register value
605  **/
606 
607 uint16_t ksz9477ReadPhyReg(NetInterface *interface, uint8_t port,
608  uint8_t address)
609 {
610  uint16_t data;
611  uint32_t command;
612 
613  //SPI slave mode?
614  if(interface->spiDriver != NULL)
615  {
616  //Set up a read operation
617  command = KSZ9477_SPI_CMD_READ;
618  //Set register address
619  command |= KSZ9477_PORTn_ETH_PHY_REG(port, address) << 5;
620 
621  //Pull the CS pin low
622  interface->spiDriver->assertCs();
623 
624  //Write 32-bit command
625  interface->spiDriver->transfer((command >> 24) & 0xFF);
626  interface->spiDriver->transfer((command >> 16) & 0xFF);
627  interface->spiDriver->transfer((command >> 8) & 0xFF);
628  interface->spiDriver->transfer(command & 0xFF);
629 
630  //Read 16-bit data
631  data = interface->spiDriver->transfer(0xFF) << 8;
632  data |= interface->spiDriver->transfer(0xFF);
633 
634  //Terminate the operation by raising the CS pin
635  interface->spiDriver->deassertCs();
636  }
637  else
638  {
639  //Read the specified PHY register
640  data = interface->nicDriver->readPhyReg(SMI_OPCODE_READ, port, address);
641  }
642 
643  //Return register value
644  return data;
645 }
646 
647 
648 /**
649  * @brief Dump PHY registers for debugging purpose
650  * @param[in] interface Underlying network interface
651  * @param[in] port Port number
652  **/
653 
654 void ksz9477DumpPhyReg(NetInterface *interface, uint8_t port)
655 {
656  uint8_t i;
657 
658  //Loop through PHY registers
659  for(i = 0; i < 32; i++)
660  {
661  //Display current PHY register
662  TRACE_DEBUG("%02" PRIu8 ": 0x%04" PRIX16 "\r\n", i,
663  ksz9477ReadPhyReg(interface, port, i));
664  }
665 
666  //Terminate with a line feed
667  TRACE_DEBUG("\r\n");
668 }
669 
670 
671 /**
672  * @brief Write switch register
673  * @param[in] interface Underlying network interface
674  * @param[in] address Switch register address
675  * @param[in] data Register value
676  **/
677 
678 void ksz9477WriteSwitchReg(NetInterface *interface, uint16_t address,
679  uint8_t data)
680 {
681  uint32_t command;
682 
683  //SPI slave mode?
684  if(interface->spiDriver != NULL)
685  {
686  //Set up a write operation
687  command = KSZ9477_SPI_CMD_WRITE;
688  //Set register address
689  command |= (address << 5) & KSZ9477_SPI_CMD_ADDR;
690 
691  //Pull the CS pin low
692  interface->spiDriver->assertCs();
693 
694  //Write 32-bit command
695  interface->spiDriver->transfer((command >> 24) & 0xFF);
696  interface->spiDriver->transfer((command >> 16) & 0xFF);
697  interface->spiDriver->transfer((command >> 8) & 0xFF);
698  interface->spiDriver->transfer(command & 0xFF);
699 
700  //Write data
701  interface->spiDriver->transfer(data);
702 
703  //Terminate the operation by raising the CS pin
704  interface->spiDriver->deassertCs();
705  }
706  else
707  {
708  //The MDC/MDIO interface does not have access to all the configuration
709  //registers. It can only access the standard MIIM registers
710  }
711 }
712 
713 
714 /**
715  * @brief Read switch register
716  * @param[in] interface Underlying network interface
717  * @param[in] address Switch register address
718  * @return Register value
719  **/
720 
721 uint8_t ksz9477ReadSwitchReg(NetInterface *interface, uint16_t address)
722 {
723  uint8_t data;
724  uint32_t command;
725 
726  //SPI slave mode?
727  if(interface->spiDriver != NULL)
728  {
729  //Set up a read operation
730  command = KSZ9477_SPI_CMD_READ;
731  //Set register address
732  command |= (address << 5) & KSZ9477_SPI_CMD_ADDR;
733 
734  //Pull the CS pin low
735  interface->spiDriver->assertCs();
736 
737  //Write 32-bit command
738  interface->spiDriver->transfer((command >> 24) & 0xFF);
739  interface->spiDriver->transfer((command >> 16) & 0xFF);
740  interface->spiDriver->transfer((command >> 8) & 0xFF);
741  interface->spiDriver->transfer(command & 0xFF);
742 
743  //Read data
744  data = interface->spiDriver->transfer(0xFF);
745 
746  //Terminate the operation by raising the CS pin
747  interface->spiDriver->deassertCs();
748  }
749  else
750  {
751  //The MDC/MDIO interface does not have access to all the configuration
752  //registers. It can only access the standard MIIM registers
753  data = 0;
754  }
755 
756  //Return register value
757  return data;
758 }
759 
760 
761 /**
762  * @brief Dump switch registers for debugging purpose
763  * @param[in] interface Underlying network interface
764  **/
765 
767 {
768  uint16_t i;
769 
770  //Loop through switch registers
771  for(i = 0; i < 256; i++)
772  {
773  //Display current switch register
774  TRACE_DEBUG("0x%02" PRIX16 " (%02" PRIu16 ") : 0x%02" PRIX8 "\r\n",
775  i, i, ksz9477ReadSwitchReg(interface, i));
776  }
777 
778  //Terminate with a line feed
779  TRACE_DEBUG("\r\n");
780 }
error_t ksz9477Init(NetInterface *interface)
KSZ9477 Ethernet switch initialization.
#define KSZ9477_PORTn_MSTP_STATE_TRANSMIT_EN
#define KSZ9477_PORTn_MSTP_STATE(port)
void ksz9477EventHandler(NetInterface *interface)
KSZ9477 event handler.
void nicNotifyLinkChange(NetInterface *interface)
Process link state change notification.
Definition: nic.c:536
#define KSZ9477_PORTn_XMII_CTRL1_RGMII_ID_EG
#define KSZ9477_TAIL_TAG_ENCODE(port)
#define MSB(x)
Definition: os_port.h:58
#define KSZ9477_BMSR
TCP/IP stack core.
#define KSZ9477_SPI_CMD_WRITE
Debugging facilities.
size_t netBufferGetLength(const NetBuffer *buffer)
Get the actual length of a multi-part buffer.
Definition: net_mem.c:297
error_t ksz9477UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
const uint16_t ksz9477IngressTailTag[6]
Tail tag rules (host to KSZ9477)
Helper functions for Ethernet.
char_t type
#define SMI_OPCODE_READ
Definition: nic.h:63
#define LSB(x)
Definition: os_port.h:54
error_t ethPadFrame(NetBuffer *buffer, size_t *length)
Ethernet frame padding.
void ksz9477DisableIrq(NetInterface *interface)
Disable interrupts.
void ksz9477WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
__start_packed struct @110 EthHeader
Ethernet frame header.
#define TRUE
Definition: os_port.h:50
#define SMI_OPCODE_WRITE
Definition: nic.h:62
#define KSZ9477_BMSR_LINK_STATUS
#define KSZ9477_PORTn_ETH_PHY_REG(port, addr)
PHY driver.
Definition: nic.h:214
#define KSZ9477_PHYCON
error_t ksz9477TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
#define KSZ9477_PORTn_XMII_CTRL1_RGMII_ID_IG
#define NET_INTERFACE_COUNT
Definition: net.h:109
#define KSZ9477_PORTn_OP_CTRL0_TAIL_TAG_EN
#define KSZ9477_PHYCON_DUPLEX_STATUS
#define KSZ9477_SWITCH_OP
KSZ9477 7-port Gigabit Ethernet switch.
#define KSZ9477_PORT6_OP_CTRL0
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
NetInterface netInterface[NET_INTERFACE_COUNT]
Definition: net.c:76
#define KSZ9477_SPI_CMD_ADDR
#define KSZ9477_SPI_CMD_READ
void ksz9477EnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t ksz9477ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
#define TRACE_INFO(...)
Definition: debug.h:94
Success.
Definition: error.h:44
Ipv6Addr address
OsEvent netEvent
Definition: net.c:74
#define KSZ9477_PORTn_MSTP_STATE_LEARNING_DIS
void osSetEvent(OsEvent *event)
Set the specified event object to the signaled state.
error_t
Error codes.
Definition: error.h:42
#define TRACE_WARNING(...)
Definition: debug.h:84
#define KSZ9477_PHYCON_SPEED_1000BT
const PhyDriver ksz9477PhyDriver
KSZ9477 Ethernet switch driver.
void ksz9477Tick(NetInterface *interface)
KSZ9477 timer handler.
unsigned int uint_t
Definition: compiler_port.h:45
error_t netBufferAppend(NetBuffer *dest, const void *src, size_t length)
Append data a multi-part buffer.
Definition: net_mem.c:586
#define KSZ9477_PHYCON_SPEED_100BTX
void osReleaseMutex(OsMutex *mutex)
Release ownership of the specified mutex object.
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
#define KSZ9477_SWITCH_OP_START_SWITCH
#define KSZ9477_CHIP_ID1
uint8_t value[]
Definition: dtls_misc.h:143
uint16_t port
Definition: dns_common.h:223
void ksz9477DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
#define KSZ9477_CHIP_ID1_DEFAULT
OsMutex netMutex
Definition: net.c:72
#define KSZ9477_PORT6_XMII_CTRL1
void ksz9477DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
void ksz9477WriteSwitchReg(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register.
#define KSZ9477_TAIL_TAG_DECODE(tag)
#define KSZ9477_PORT5
uint8_t length
Definition: dtls_misc.h:142
#define KSZ9477_PORT1
#define FALSE
Definition: os_port.h:46
int bool_t
Definition: compiler_port.h:49
bool_t ksz9477GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
#define KSZ9477_PHYCON_SPEED_10BT
#define KSZ9477_PORTn_MSTP_STATE_RECEIVE_EN
void osAcquireMutex(OsMutex *mutex)
Acquire ownership of the specified mutex object.
uint16_t ksz9477ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
#define TRACE_DEBUG(...)
Definition: debug.h:106