ksz9563_driver.h
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1 /**
2  * @file ksz9563_driver.h
3  * @brief KSZ9563 3-port Gigabit Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.4
29  **/
30 
31 #ifndef _KSZ9563_DRIVER_H
32 #define _KSZ9563_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //KSZ9563 ports
38 #define KSZ9563_PORT1 1
39 #define KSZ9563_PORT2 2
40 
41 //SPI command byte
42 #define KSZ9563_SPI_CMD_WRITE 0x40000000
43 #define KSZ9563_SPI_CMD_READ 0x60000000
44 #define KSZ9563_SPI_CMD_ADDR 0x001FFFE0
45 
46 //KSZ9563 PHY registers
47 #define KSZ9563_BMCR 0x00
48 #define KSZ9563_BMSR 0x01
49 #define KSZ9563_PHYID1 0x02
50 #define KSZ9563_PHYID2 0x03
51 #define KSZ9563_ANAR 0x04
52 #define KSZ9563_ANLPAR 0x05
53 #define KSZ9563_ANER 0x06
54 #define KSZ9563_ANNPR 0x07
55 #define KSZ9563_ANLPNPR 0x08
56 #define KSZ9563_GBCR 0x09
57 #define KSZ9563_GBSR 0x0A
58 #define KSZ9563_MMDACR 0x0D
59 #define KSZ9563_MMDAADR 0x0E
60 #define KSZ9563_GBESR 0x0F
61 #define KSZ9563_RLB 0x11
62 #define KSZ9563_LINKMD 0x12
63 #define KSZ9563_DPMAPCSS 0x13
64 #define KSZ9563_RXERCTR 0x15
65 #define KSZ9563_ICSR 0x1B
66 #define KSZ9563_AUTOMDI 0x1C
67 #define KSZ9563_PHYCON 0x1F
68 
69 //KSZ9563 Switch registers
70 #define KSZ9563_CHIP_ID0 0x0000
71 #define KSZ9563_CHIP_ID1 0x0001
72 #define KSZ9563_CHIP_ID2 0x0002
73 #define KSZ9563_CHIP_ID3 0x0003
74 #define KSZ9563_SWITCH_OP 0x0300
75 #define KSZ9563_PORT1_INT_STATUS 0x101B
76 #define KSZ9563_PORT1_INT_MASK 0x101F
77 #define KSZ9563_PORT1_OP_CTRL0 0x1020
78 #define KSZ9563_PORT1_STATUS 0x1030
79 #define KSZ9563_PORT1_MSTP_STATE 0x1B04
80 #define KSZ9563_PORT2_INT_STATUS 0x201B
81 #define KSZ9563_PORT2_INT_MASK 0x201F
82 #define KSZ9563_PORT2_OP_CTRL0 0x2020
83 #define KSZ9563_PORT2_STATUS 0x2030
84 #define KSZ9563_PORT2_MSTP_STATE 0x2B04
85 #define KSZ9563_PORT3_INT_STATUS 0x301B
86 #define KSZ9563_PORT3_INT_MASK 0x301F
87 #define KSZ9563_PORT3_OP_CTRL0 0x3020
88 #define KSZ9563_PORT3_STATUS 0x3030
89 #define KSZ9563_PORT3_XMII_CTRL0 0x3300
90 #define KSZ9563_PORT3_XMII_CTRL1 0x3301
91 #define KSZ9563_PORT3_MSTP_STATE 0x3B04
92 
93 //KSZ9563 Switch register access macros
94 #define KSZ9563_PORTn_INT_STATUS(port) (0x001B + ((port) * 0x1000))
95 #define KSZ9563_PORTn_INT_MASK(port) (0x001F + ((port) * 0x1000))
96 #define KSZ9563_PORTn_OP_CTRL0(port) (0x0020 + ((port) * 0x1000))
97 #define KSZ9563_PORTn_STATUS(port) (0x0030 + ((port) * 0x1000))
98 #define KSZ9563_PORTn_XMII_CTRL0(port) (0x0300 + ((port) * 0x1000))
99 #define KSZ9563_PORTn_XMII_CTRL1(port) (0x0301 + ((port) * 0x1000))
100 #define KSZ9563_PORTn_MSTP_STATE(port) (0x0B04 + ((port) * 0x1000))
101 #define KSZ9563_PORTn_ETH_PHY_REG(port, addr) (0x0100 + ((port) * 0x1000) + ((addr) * 2))
102 
103 //PHY Basic Control register
104 #define KSZ9563_BMCR_RESET 0x8000
105 #define KSZ9563_BMCR_LOOPBACK 0x4000
106 #define KSZ9563_BMCR_SPEED_SEL_LSB 0x2000
107 #define KSZ9563_BMCR_AN_EN 0x1000
108 #define KSZ9563_BMCR_POWER_DOWN 0x0800
109 #define KSZ9563_BMCR_ISOLATE 0x0400
110 #define KSZ9563_BMCR_RESTART_AN 0x0200
111 #define KSZ9563_BMCR_DUPLEX_MODE 0x0100
112 #define KSZ9563_BMCR_COL_TEST 0x0080
113 #define KSZ9563_BMCR_SPEED_SEL_MSB 0x0040
114 
115 //PHY Basic Status register
116 #define KSZ9563_BMSR_100BT4 0x8000
117 #define KSZ9563_BMSR_100BTX_FD 0x4000
118 #define KSZ9563_BMSR_100BTX_HD 0x2000
119 #define KSZ9563_BMSR_10BT_FD 0x1000
120 #define KSZ9563_BMSR_10BT_HD 0x0800
121 #define KSZ9563_BMSR_EXTENDED_STATUS 0x0100
122 #define KSZ9563_BMSR_MF_PREAMBLE_SUPPR 0x0040
123 #define KSZ9563_BMSR_AN_COMPLETE 0x0020
124 #define KSZ9563_BMSR_REMOTE_FAULT 0x0010
125 #define KSZ9563_BMSR_AN_CAPABLE 0x0008
126 #define KSZ9563_BMSR_LINK_STATUS 0x0004
127 #define KSZ9563_BMSR_JABBER_DETECT 0x0002
128 #define KSZ9563_BMSR_EXTENDED_CAPABLE 0x0001
129 
130 //PHY ID High register
131 #define KSZ9563_PHYID1_DEFAULT 0x0022
132 
133 //PHY ID Low register
134 #define KSZ9563_PHYID2_DEFAULT 0x1631
135 
136 //PHY Auto-Negotiation Advertisement register
137 #define KSZ9563_ANAR_NEXT_PAGE 0x8000
138 #define KSZ9563_ANAR_REMOTE_FAULT 0x2000
139 #define KSZ9563_ANAR_PAUSE 0x0C00
140 #define KSZ9563_ANAR_100BT4 0x0200
141 #define KSZ9563_ANAR_100BTX_FD 0x0100
142 #define KSZ9563_ANAR_100BTX_HD 0x0080
143 #define KSZ9563_ANAR_10BT_FD 0x0040
144 #define KSZ9563_ANAR_10BT_HD 0x0020
145 #define KSZ9563_ANAR_SELECTOR 0x001F
146 #define KSZ9563_ANAR_SELECTOR_DEFAULT 0x0001
147 
148 //PHY Auto-Negotiation Link Partner Ability register
149 #define KSZ9563_ANLPAR_NEXT_PAGE 0x8000
150 #define KSZ9563_ANLPAR_ACK 0x4000
151 #define KSZ9563_ANLPAR_REMOTE_FAULT 0x2000
152 #define KSZ9563_ANLPAR_PAUSE 0x0C00
153 #define KSZ9563_ANLPAR_100BT4 0x0200
154 #define KSZ9563_ANLPAR_100BTX_FD 0x0100
155 #define KSZ9563_ANLPAR_100BTX_HD 0x0080
156 #define KSZ9563_ANLPAR_10BT_FD 0x0040
157 #define KSZ9563_ANLPAR_10BT_HD 0x0020
158 #define KSZ9563_ANLPAR_SELECTOR 0x001F
159 #define KSZ9563_ANLPAR_SELECTOR_DEFAULT 0x0001
160 
161 //PHY Auto-Negotiation Expansion Status register
162 #define KSZ9563_ANER_PAR_DETECT_FAULT 0x0010
163 #define KSZ9563_ANER_LP_NEXT_PAGE_ABLE 0x0008
164 #define KSZ9563_ANER_NEXT_PAGE_ABLE 0x0004
165 #define KSZ9563_ANER_PAGE_RECEIVED 0x0002
166 #define KSZ9563_ANER_LP_AN_ABLE 0x0001
167 
168 //PHY Auto-Negotiation Next Page register
169 #define KSZ9563_ANNPR_NEXT_PAGE 0x8000
170 #define KSZ9563_ANNPR_MSG_PAGE 0x2000
171 #define KSZ9563_ANNPR_ACK2 0x1000
172 #define KSZ9563_ANNPR_TOGGLE 0x0800
173 #define KSZ9563_ANNPR_MESSAGE 0x07FF
174 
175 //PHY Auto-Negotiation Link Partner Next Page Ability register
176 #define KSZ9563_ANLPNPR_NEXT_PAGE 0x8000
177 #define KSZ9563_ANLPNPR_ACK 0x4000
178 #define KSZ9563_ANLPNPR_MSG_PAGE 0x2000
179 #define KSZ9563_ANLPNPR_ACK2 0x1000
180 #define KSZ9563_ANLPNPR_TOGGLE 0x0800
181 #define KSZ9563_ANLPNPR_MESSAGE 0x07FF
182 
183 //PHY 1000BASE-T Control register
184 #define KSZ9563_GBCR_TEST_MODE 0xE000
185 #define KSZ9563_GBCR_MS_MAN_CONF_EN 0x1000
186 #define KSZ9563_GBCR_MS_MAN_CONF_VAL 0x0800
187 #define KSZ9563_GBCR_PORT_TYPE 0x0400
188 #define KSZ9563_GBCR_1000BT_FD 0x0200
189 #define KSZ9563_GBCR_1000BT_HD 0x0100
190 
191 //PHY 1000BASE-T Status register
192 #define KSZ9563_GBSR_MS_CONF_FAULT 0x8000
193 #define KSZ9563_GBSR_MS_CONF_RES 0x4000
194 #define KSZ9563_GBSR_LOCAL_RECEIVER_STATUS 0x2000
195 #define KSZ9563_GBSR_REMOTE_RECEIVER_STATUS 0x1000
196 #define KSZ9563_GBSR_LP_1000BT_FD 0x0800
197 #define KSZ9563_GBSR_LP_1000BT_HD 0x0400
198 #define KSZ9563_GBSR_IDLE_ERR_COUNT 0x00FF
199 
200 //PHY MMD Setup register
201 #define KSZ9563_MMDACR_FUNC 0xC000
202 #define KSZ9563_MMDACR_FUNC_ADDR 0x0000
203 #define KSZ9563_MMDACR_FUNC_DATA_NO_POST_INC 0x4000
204 #define KSZ9563_MMDACR_FUNC_DATA_POST_INC_RW 0x8000
205 #define KSZ9563_MMDACR_FUNC_DATA_POST_INC_W 0xC000
206 #define KSZ9563_MMDACR_DEVAD 0x001F
207 
208 //PHY Extended Status register
209 #define KSZ9563_GBESR_1000BX_FD 0x8000
210 #define KSZ9563_GBESR_1000BX_HD 0x4000
211 #define KSZ9563_GBESR_1000BT_FD 0x2000
212 #define KSZ9563_GBESR_1000BT_HD 0x1000
213 
214 //PHY Remote Loopback register
215 #define KSZ9563_RLB_REMOTE_LOOPBACK 0x0100
216 
217 //PHY LinkMD register
218 #define KSZ9563_LINKMD_TEST_EN 0x8000
219 #define KSZ9563_LINKMD_PAIR 0x3000
220 #define KSZ9563_LINKMD_PAIR_A 0x0000
221 #define KSZ9563_LINKMD_PAIR_B 0x1000
222 #define KSZ9563_LINKMD_PAIR_C 0x2000
223 #define KSZ9563_LINKMD_PAIR_D 0x3000
224 #define KSZ9563_LINKMD_STATUS 0x0300
225 #define KSZ9563_LINKMD_STATUS_NORMAL 0x0000
226 #define KSZ9563_LINKMD_STATUS_OPEN 0x0100
227 #define KSZ9563_LINKMD_STATUS_SHORT 0x0200
228 
229 //PHY Digital PMA/PCS Status register
230 #define KSZ9563_DPMAPCSS_1000BT_LINK_STATUS 0x0002
231 #define KSZ9563_DPMAPCSS_100BTX_LINK_STATUS 0x0001
232 
233 //Port Interrupt Control/Status register
234 #define KSZ9563_ICSR_JABBER_IE 0x8000
235 #define KSZ9563_ICSR_RECEIVE_ERROR_IE 0x4000
236 #define KSZ9563_ICSR_PAGE_RECEIVED_IE 0x2000
237 #define KSZ9563_ICSR_PAR_DETECT_FAULT_IE 0x1000
238 #define KSZ9563_ICSR_LP_ACK_IE 0x0800
239 #define KSZ9563_ICSR_LINK_DOWN_IE 0x0400
240 #define KSZ9563_ICSR_REMOTE_FAULT_IE 0x0200
241 #define KSZ9563_ICSR_LINK_UP_IE 0x0100
242 #define KSZ9563_ICSR_JABBER_IF 0x0080
243 #define KSZ9563_ICSR_RECEIVE_ERROR_IF 0x0040
244 #define KSZ9563_ICSR_PAGE_RECEIVED_IF 0x0020
245 #define KSZ9563_ICSR_PAR_DETECT_FAULT_IF 0x0010
246 #define KSZ9563_ICSR_LP_ACK_IF 0x0008
247 #define KSZ9563_ICSR_LINK_DOWN_IF 0x0004
248 #define KSZ9563_ICSR_REMOTE_FAULT_IF 0x0002
249 #define KSZ9563_ICSR_LINK_UP_IF 0x0001
250 
251 //PHY Auto MDI/MDI-X register
252 #define KSZ9563_AUTOMDI_MDI_SET 0x0080
253 #define KSZ9563_AUTOMDI_SWAP_OFF 0x0040
254 
255 //PHY Control register
256 #define KSZ9563_PHYCON_JABBER_EN 0x0200
257 #define KSZ9563_PHYCON_SPEED_1000BT 0x0040
258 #define KSZ9563_PHYCON_SPEED_100BTX 0x0020
259 #define KSZ9563_PHYCON_SPEED_10BT 0x0010
260 #define KSZ9563_PHYCON_DUPLEX_STATUS 0x0008
261 #define KSZ9563_PHYCON_1000BT_MS_STATUS 0x0004
262 
263 //Global Chip ID 0 register
264 #define KSZ9563_CHIP_ID0_DEFAULT 0x00
265 
266 //Global Chip ID 1 register
267 #define KSZ9563_CHIP_ID1_DEFAULT 0x98
268 
269 //Global Chip ID 2 register
270 #define KSZ9563_CHIP_ID2_DEFAULT 0x93
271 
272 //Global Chip ID 3 register
273 #define KSZ9563_CHIP_ID3_REVISION_ID 0xF0
274 #define KSZ9563_CHIP_ID3_GLOBAL_SOFT_RESET 0x01
275 
276 //Switch Operation register
277 #define KSZ9563_SWITCH_OP_DOUBLE_TAG_EN 0x80
278 #define KSZ9563_SWITCH_OP_SOFT_HARD_RESET 0x02
279 #define KSZ9563_SWITCH_OP_START_SWITCH 0x01
280 
281 //Port N Interrupt Status register
282 #define KSZ9563_PORTn_INT_STATUS_PTP 0x04
283 #define KSZ9563_PORTn_INT_STATUS_PHY 0x02
284 #define KSZ9563_PORTn_INT_STATUS_ACL 0x01
285 
286 //Port N Interrupt Mask register
287 #define KSZ9563_PORTn_INT_MASK_PTP 0x04
288 #define KSZ9563_PORTn_INT_MASK_PHY 0x02
289 #define KSZ9563_PORTn_INT_MASK_ACL 0x01
290 
291 //Port N Operation Control 0 register
292 #define KSZ9563_PORTn_OP_CTRL0_LOCAL_LOOPBACK 0x80
293 #define KSZ9563_PORTn_OP_CTRL0_REMOTE_LOOPBACK 0x40
294 #define KSZ9563_PORTn_OP_CTRL0_TAIL_TAG_EN 0x04
295 #define KSZ9563_PORTn_OP_CTRL0_TX_QUEUE_SPLIT_EN 0x03
296 
297 //Port N Status register
298 #define KSZ9563_PORTn_STATUS_SPEED 0x18
299 #define KSZ9563_PORTn_STATUS_SPEED_10MBPS 0x00
300 #define KSZ9563_PORTn_STATUS_SPEED_100MBPS 0x08
301 #define KSZ9563_PORTn_STATUS_SPEED_1000MBPS 0x10
302 #define KSZ9563_PORTn_STATUS_DUPLEX 0x04
303 #define KSZ9563_PORTn_STATUS_TX_FLOW_CTRL_EN 0x02
304 #define KSZ9563_PORTn_STATUS_RX_FLOW_CTRL_EN 0x01
305 
306 //XMII Port N Control 0 register
307 #define KSZ9563_PORTn_XMII_CTRL0_DUPLEX 0x40
308 #define KSZ9563_PORTn_XMII_CTRL0_TX_FLOW_CTRL_EN 0x20
309 #define KSZ9563_PORTn_XMII_CTRL0_SPEED_10_100 0x10
310 #define KSZ9563_PORTn_XMII_CTRL0_RX_FLOW_CTRL_EN 0x08
311 
312 //XMII Port N Control 1 register
313 #define KSZ9563_PORTn_XMII_CTRL1_SPEED_1000 0x40
314 #define KSZ9563_PORTn_XMII_CTRL1_RGMII_ID_IG 0x10
315 #define KSZ9563_PORTn_XMII_CTRL1_RGMII_ID_EG 0x08
316 #define KSZ9563_PORTn_XMII_CTRL1_MII_RMII_MODE 0x04
317 #define KSZ9563_PORTn_XMII_CTRL1_IF_TYPE 0x03
318 #define KSZ9563_PORTn_XMII_CTRL1_IF_TYPE_MII 0x00
319 #define KSZ9563_PORTn_XMII_CTRL1_IF_TYPE_RMII 0x01
320 #define KSZ9563_PORTn_XMII_CTRL1_IF_TYPE_RGMII 0x03
321 
322 //Port N MSTP State register
323 #define KSZ9563_PORTn_MSTP_STATE_TRANSMIT_EN 0x04
324 #define KSZ9563_PORTn_MSTP_STATE_RECEIVE_EN 0x02
325 #define KSZ9563_PORTn_MSTP_STATE_LEARNING_DIS 0x01
326 
327 //Tail tag encoding
328 #define KSZ9563_TAIL_TAG_ENCODE(port) (0x20 | ((port) & 0x03))
329 //Tail tag decoding
330 #define KSZ9563_TAIL_TAG_DECODE(tag) (((tag) & 0x01) + 1)
331 
332 //C++ guard
333 #ifdef __cplusplus
334  extern "C" {
335 #endif
336 
337 //KSZ9563 Ethernet switch driver
338 extern const PhyDriver ksz9563PhyDriver;
339 
340 //KSZ9563 related functions
341 error_t ksz9563Init(NetInterface *interface);
342 
343 bool_t ksz9563GetLinkState(NetInterface *interface, uint8_t port);
344 
345 void ksz9563Tick(NetInterface *interface);
346 
347 void ksz9563EnableIrq(NetInterface *interface);
348 void ksz9563DisableIrq(NetInterface *interface);
349 
350 void ksz9563EventHandler(NetInterface *interface);
351 
352 error_t ksz9563TagFrame(NetInterface *interface, NetBuffer *buffer,
353  size_t *offset, uint8_t port, uint16_t *type);
354 
355 error_t ksz9563UntagFrame(NetInterface *interface, uint8_t **frame,
356  size_t *length, uint8_t *port);
357 
358 void ksz9563WritePhyReg(NetInterface *interface, uint8_t port,
359  uint8_t address, uint16_t data);
360 
361 uint16_t ksz9563ReadPhyReg(NetInterface *interface, uint8_t port,
362  uint8_t address);
363 
364 void ksz9563DumpPhyReg(NetInterface *interface, uint8_t port);
365 
366 void ksz9563WriteSwitchReg(NetInterface *interface, uint16_t address,
367  uint8_t data);
368 
369 uint8_t ksz9563ReadSwitchReg(NetInterface *interface, uint16_t address);
370 
371 void ksz9563DumpSwitchReg(NetInterface *interface);
372 
373 //C++ guard
374 #ifdef __cplusplus
375  }
376 #endif
377 
378 #endif
error_t ksz9563Init(NetInterface *interface)
KSZ9563 Ethernet switch initialization.
char_t type
void ksz9563WriteSwitchReg(NetInterface *interface, uint16_t address, uint8_t data)
Write switch register.
void ksz9563EventHandler(NetInterface *interface)
KSZ9563 event handler.
const PhyDriver ksz9563PhyDriver
KSZ9563 Ethernet switch driver.
error_t ksz9563TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add tail tag to Ethernet frame.
void ksz9563DumpSwitchReg(NetInterface *interface)
Dump switch registers for debugging purpose.
uint8_t ksz9563ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch register.
error_t ksz9563UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode tail tag from incoming Ethernet frame.
PHY driver.
Definition: nic.h:214
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
Ipv6Addr address
error_t
Error codes.
Definition: error.h:42
void ksz9563Tick(NetInterface *interface)
KSZ9563 timer handler.
void ksz9563DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
uint16_t ksz9563ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
uint8_t data[]
Definition: dtls_misc.h:169
#define NetInterface
Definition: net.h:36
bool_t ksz9563GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
void ksz9563WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
uint16_t port
Definition: dns_common.h:223
void ksz9563EnableIrq(NetInterface *interface)
Enable interrupts.
uint8_t length
Definition: dtls_misc.h:142
void ksz9563DisableIrq(NetInterface *interface)
Disable interrupts.
int bool_t
Definition: compiler_port.h:49
Network interface controller abstraction layer.