lan9303_driver.h
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1 /**
2  * @file lan9303_driver.h
3  * @brief LAN9303 Ethernet switch
4  *
5  * @section License
6  *
7  * Copyright (C) 2010-2018 Oryx Embedded SARL. All rights reserved.
8  *
9  * This file is part of CycloneTCP Open.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version 2
14  * of the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software Foundation,
23  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24  *
25  * @author Oryx Embedded SARL (www.oryx-embedded.com)
26  * @version 1.9.0
27  **/
28 
29 #ifndef _LAN9303_DRIVER_H
30 #define _LAN9303_DRIVER_H
31 
32 //Dependencies
33 #include "core/nic.h"
34 
35 //LAN9303 ports
36 #define LAN9303_PORT1 1
37 #define LAN9303_PORT2 2
38 
39 //LAN9303 PHY registers
40 #define LAN9303_PHY_REG_BMCR 0x00
41 #define LAN9303_PHY_REG_BMSR 0x01
42 #define LAN9303_PHY_REG_PHYIDR1 0x02
43 #define LAN9303_PHY_REG_PHYIDR2 0x03
44 #define LAN9303_PHY_REG_ANAR 0x04
45 #define LAN9303_PHY_REG_ANLPAR 0x05
46 #define LAN9303_PHY_REG_ANER 0x06
47 #define LAN9303_PHY_REG_MCSR 0x11
48 #define LAN9303_PHY_REG_SMR 0x12
49 #define LAN9303_PHY_REG_SCSIR 0x1B
50 #define LAN9303_PHY_REG_PISR 0x1D
51 #define LAN9303_PHY_REG_PIMR 0x1E
52 #define LAN9303_PHY_REG_PSCSR 0x1F
53 
54 //BMCR register
55 #define BMCR_RESET (1 << 15)
56 #define BMCR_LOOPBACK (1 << 14)
57 #define BMCR_SPEED_SEL (1 << 13)
58 #define BMCR_AN_EN (1 << 12)
59 #define BMCR_POWER_DOWN (1 << 11)
60 #define BMCR_ISOLATE (1 << 10)
61 #define BMCR_RESTART_AN (1 << 9)
62 #define BMCR_DUPLEX_MODE (1 << 8)
63 #define BMCR_COL_TEST (1 << 7)
64 
65 //BMSR register
66 #define BMSR_100BT4 (1 << 15)
67 #define BMSR_100BTX_FD (1 << 14)
68 #define BMSR_100BTX (1 << 13)
69 #define BMSR_10BT_FD (1 << 12)
70 #define BMSR_10BT (1 << 11)
71 #define BMSR_100BT2_FD (1 << 10)
72 #define BMSR_100BT2 (1 << 9)
73 #define BMSR_EXTENTED_STATUS (1 << 8)
74 #define BMSR_AN_COMPLETE (1 << 5)
75 #define BMSR_REMOTE_FAULT (1 << 4)
76 #define BMSR_AN_ABLE (1 << 3)
77 #define BMSR_LINK_STATUS (1 << 2)
78 #define BMSR_JABBER_DETECT (1 << 1)
79 #define BMSR_EXTENDED_CAP (1 << 0)
80 
81 //ANAR register
82 #define ANAR_RF (1 << 13)
83 #define ANAR_PAUSE1 (1 << 11)
84 #define ANAR_PAUSE0 (1 << 10)
85 #define ANAR_100BTX_FD (1 << 8)
86 #define ANAR_100BTX (1 << 7)
87 #define ANAR_10BT_FD (1 << 6)
88 #define ANAR_10BT (1 << 5)
89 #define ANAR_SELECTOR4 (1 << 4)
90 #define ANAR_SELECTOR3 (1 << 3)
91 #define ANAR_SELECTOR2 (1 << 2)
92 #define ANAR_SELECTOR1 (1 << 1)
93 #define ANAR_SELECTOR0 (1 << 0)
94 
95 //ANLPAR register
96 #define ANLPAR_NP (1 << 15)
97 #define ANLPAR_ACK (1 << 14)
98 #define ANLPAR_RF (1 << 13)
99 #define ANLPAR_PAUSE1 (1 << 11)
100 #define ANLPAR_PAUSE0 (1 << 10)
101 #define ANLPAR_100BT4 (1 << 9)
102 #define ANLPAR_100BTX_FD (1 << 8)
103 #define ANLPAR_100BTX (1 << 7)
104 #define ANLPAR_10BT_FD (1 << 6)
105 #define ANLPAR_10BT (1 << 5)
106 #define ANLPAR_SELECTOR4 (1 << 4)
107 #define ANLPAR_SELECTOR3 (1 << 3)
108 #define ANLPAR_SELECTOR2 (1 << 2)
109 #define ANLPAR_SELECTOR1 (1 << 1)
110 #define ANLPAR_SELECTOR0 (1 << 0)
111 
112 //ANER register
113 #define ANER_PDF (1 << 4)
114 #define ANER_LP_NP_ABLE (1 << 3)
115 #define ANER_NP_ABLE (1 << 2)
116 #define ANER_PAGE_RX (1 << 1)
117 #define ANER_LP_AN_ABLE (1 << 0)
118 
119 //MCSR register
120 #define MCSR_EDPWRDOWN (1 << 13)
121 #define MCSR_ENERGYON (1 << 1)
122 
123 //SMR register
124 #define SMR_MODE2 (1 << 7)
125 #define SMR_MODE1 (1 << 6)
126 #define SMR_MODE0 (1 << 5)
127 #define SMR_PHYAD4 (1 << 4)
128 #define SMR_PHYAD3 (1 << 3)
129 #define SMR_PHYAD2 (1 << 2)
130 #define SMR_PHYAD1 (1 << 1)
131 #define SMR_PHYAD0 (1 << 0)
132 
133 //SCSIR register
134 #define SCSIR_AMDIXCTRL (1 << 15)
135 #define SCSIR_AMDIXEN (1 << 14)
136 #define SCSIR_AMDIXSTATE (1 << 13)
137 #define SCSIR_SQEOFF (1 << 11)
138 #define SCSIR_VCOOFF_LP (1 << 10)
139 #define SCSIR_XPOL (1 << 4)
140 
141 //ISR register
142 #define ISR_ENERGYON (1 << 7)
143 #define ISR_AN_COMPLETE (1 << 6)
144 #define ISR_REMOTE_FAULT (1 << 5)
145 #define ISR_LINK_DOWN (1 << 4)
146 #define ISR_AN_LP_ACK (1 << 3)
147 #define ISR_PD_FAULT (1 << 2)
148 #define ISR_AN_PAGE_RECEIVED (1 << 1)
149 
150 //IMR register
151 #define IMR_ENERGYON (1 << 7)
152 #define IMR_AN_COMPLETE (1 << 6)
153 #define IMR_REMOTE_FAULT (1 << 5)
154 #define IMR_LINK_DOWN (1 << 4)
155 #define IMR_AN_LP_ACK (1 << 3)
156 #define IMR_PD_FAULT (1 << 2)
157 #define IMR_AN_PAGE_RECEIVED (1 << 1)
158 
159 //PSCSR register
160 #define PSCSR_AUTODONE (1 << 12)
161 #define PSCSR_HCDSPEED2 (1 << 4)
162 #define PSCSR_HCDSPEED1 (1 << 3)
163 #define PSCSR_HCDSPEED0 (1 << 2)
164 
165 //Speed indication
166 #define PSCSR_HCDSPEED_MASK (7 << 2)
167 #define PSCSR_HCDSPEED_10BT (1 << 2)
168 #define PSCSR_HCDSPEED_100BTX (2 << 2)
169 #define PSCSR_HCDSPEED_10BT_FD (5 << 2)
170 #define PSCSR_HCDSPEED_100BTX_FD (6 << 2)
171 
172 //C++ guard
173 #ifdef __cplusplus
174  extern "C" {
175 #endif
176 
177 //LAN9303 Ethernet switch driver
178 extern const PhyDriver lan9303PhyDriver;
179 
180 //LAN9303 related functions
181 error_t lan9303Init(NetInterface *interface);
182 
183 bool_t lan9303GetLinkState(NetInterface *interface, uint8_t port);
184 
185 void lan9303Tick(NetInterface *interface);
186 
187 void lan9303EnableIrq(NetInterface *interface);
188 void lan9303DisableIrq(NetInterface *interface);
189 
190 void lan9303EventHandler(NetInterface *interface);
191 
192 void lan9303WritePhyReg(NetInterface *interface,
193  uint8_t port, uint8_t address, uint16_t data);
194 
195 uint16_t lan9303ReadPhyReg(NetInterface *interface,
196  uint8_t port, uint8_t address);
197 
198 void lan9303DumpPhyReg(NetInterface *interface, uint8_t port);
199 
200 void lan9303WriteSmiReg(NetInterface *interface, uint16_t address,
201  uint32_t data);
202 
203 uint32_t lan9303ReadSmiReg(NetInterface *interface, uint16_t address);
204 
205 void lan9303DumpSmiReg(NetInterface *interface);
206 
207 //C++ guard
208 #ifdef __cplusplus
209  }
210 #endif
211 
212 #endif
void lan9303WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
void lan9303DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
void lan9303WriteSmiReg(NetInterface *interface, uint16_t address, uint32_t data)
Write SMI register.
const PhyDriver lan9303PhyDriver
LAN9303 Ethernet switch driver.
void lan9303DumpSmiReg(NetInterface *interface)
Dump SMI registers for debugging purpose.
bool_t lan9303GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
PHY driver.
Definition: nic.h:196
uint16_t lan9303ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.
void lan9303DisableIrq(NetInterface *interface)
Disable interrupts.
void lan9303EventHandler(NetInterface *interface)
LAN9303 event handler.
void lan9303EnableIrq(NetInterface *interface)
Enable interrupts.
Ipv6Addr address
error_t
Error codes.
Definition: error.h:40
error_t lan9303Init(NetInterface *interface)
LAN9303 Ethernet switch initialization.
uint8_t data[]
Definition: dtls_misc.h:167
#define NetInterface
Definition: net.h:34
uint16_t port
Definition: dns_common.h:221
void lan9303Tick(NetInterface *interface)
LAN9303 timer handler.
uint32_t lan9303ReadSmiReg(NetInterface *interface, uint16_t address)
Read SMI register.
int bool_t
Definition: compiler_port.h:47
Network interface controller abstraction layer.