lan9303_driver.h
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1 /**
2  * @file lan9303_driver.h
3  * @brief LAN9303 3-port Ethernet switch
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _LAN9303_DRIVER_H
32 #define _LAN9303_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //LAN9303 ports
38 #define LAN9303_PORT1 1
39 #define LAN9303_PORT2 2
40 
41 //LAN9303 PHY registers
42 #define LAN9303_BMCR 0x00
43 #define LAN9303_BMSR 0x01
44 #define LAN9303_PHYID1 0x02
45 #define LAN9303_PHYID2 0x03
46 #define LAN9303_ANAR 0x04
47 #define LAN9303_ANLPAR 0x05
48 #define LAN9303_ANER 0x06
49 #define LAN9303_PMCSR 0x11
50 #define LAN9303_PSMR 0x12
51 #define LAN9303_PSCSIR 0x1B
52 #define LAN9303_PISR 0x1D
53 #define LAN9303_PIMR 0x1E
54 #define LAN9303_PSCSR 0x1F
55 
56 //LAN9303 System registers
57 #define LAN9303_BYTE_TEST 0x0064
58 #define LAN9303_HW_CFG 0x0074
59 #define LAN9303_SWITCH_CSR_DATA 0x01AC
60 #define LAN9303_SWITCH_CSR_CMD 0x01B0
61 
62 //LAN9303 Switch Fabric registers
63 #define LAN9303_SW_DEV_ID 0x0000
64 #define LAN9303_SW_RESET 0x0001
65 #define LAN9303_SW_IMR 0x0004
66 #define LAN9303_SW_IPR 0x0005
67 #define LAN9303_MAC_VER_ID0 0x0400
68 #define LAN9303_MAC_RX_CFG0 0x0401
69 #define LAN9303_MAC_TX_CFG0 0x0440
70 #define LAN9303_MAC_VER_ID1 0x0800
71 #define LAN9303_MAC_RX_CFG1 0x0801
72 #define LAN9303_MAC_TX_CFG1 0x0840
73 #define LAN9303_MAC_VER_ID2 0x0C00
74 #define LAN9303_MAC_RX_CFG2 0x0C01
75 #define LAN9303_MAC_TX_CFG2 0x0C40
76 #define LAN9303_SWE_PORT_STATE 0x1843
77 #define LAN9303_SWE_PORT_MIRROR 0x1846
78 #define LAN9303_SWE_INGRSS_PORT_TYP 0x1847
79 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1C0C
80 
81 //LAN9303 Switch Fabric register access macros
82 #define LAN9303_MAC_VER_ID(port) (0x0400 + ((port) * 0x0400))
83 #define LAN9303_MAC_RX_CFG(port) (0x0401 + ((port) * 0x0400))
84 #define LAN9303_MAC_TX_CFG(port) (0x0440 + ((port) * 0x0400))
85 
86 //PHY Basic Control register
87 #define LAN9303_BMCR_RESET 0x8000
88 #define LAN9303_BMCR_LOOPBACK 0x4000
89 #define LAN9303_BMCR_SPEED_SEL 0x2000
90 #define LAN9303_BMCR_AN_EN 0x1000
91 #define LAN9303_BMCR_POWER_DOWN 0x0800
92 #define LAN9303_BMCR_RESTART_AN 0x0200
93 #define LAN9303_BMCR_DUPLEX_MODE 0x0100
94 #define LAN9303_BMCR_COL_TEST 0x0080
95 
96 //PHY Basic Status register
97 #define LAN9303_BMSR_100BT4 0x8000
98 #define LAN9303_BMSR_100BTX_FD 0x4000
99 #define LAN9303_BMSR_100BTX_HD 0x2000
100 #define LAN9303_BMSR_10BT_FD 0x1000
101 #define LAN9303_BMSR_10BT_HD 0x0800
102 #define LAN9303_BMSR_100BT2_FD 0x0400
103 #define LAN9303_BMSR_100BT2_HD 0x0200
104 #define LAN9303_BMSR_AN_COMPLETE 0x0020
105 #define LAN9303_BMSR_REMOTE_FAULT 0x0010
106 #define LAN9303_BMSR_AN_CAPABLE 0x0008
107 #define LAN9303_BMSR_LINK_STATUS 0x0004
108 #define LAN9303_BMSR_JABBER_DETECT 0x0002
109 #define LAN9303_BMSR_EXTENDED_CAPABLE 0x0001
110 
111 //PHY Identification MSB register
112 #define LAN9303_PHYID1_PHY_ID_MSB 0xFFFF
113 #define LAN9303_PHYID1_PHY_ID_MSB_DEFAULT 0x0007
114 
115 //PHY Identification LSB register
116 #define LAN9303_PHYID2_PHY_ID_LSB 0xFFFF
117 #define LAN9303_PHYID2_PHY_ID_LSB_DEFAULT 0x0030
118 #define LAN9303_PHYID2_MODEL_NUM 0x03F0
119 #define LAN9303_PHYID2_MODEL_NUM_DEFAULT 0x00D0
120 #define LAN9303_PHYID2_REVISION_NUM 0x000F
121 
122 //PHY Auto-Negotiation Advertisement register
123 #define LAN9303_ANAR_REMOTE_FAULT 0x2000
124 #define LAN9303_ANAR_ASYM_PAUSE 0x0800
125 #define LAN9303_ANAR_SYM_PAUSE 0x0400
126 #define LAN9303_ANAR_100BTX_FD 0x0100
127 #define LAN9303_ANAR_100BTX_HD 0x0080
128 #define LAN9303_ANAR_10BT_FD 0x0040
129 #define LAN9303_ANAR_10BT_HD 0x0020
130 #define LAN9303_ANAR_SELECTOR 0x001F
131 #define LAN9303_ANAR_SELECTOR_DEFAULT 0x0001
132 
133 //PHY Auto-Negotiation Link Partner Base Page Ability register
134 #define LAN9303_ANLPAR_NEXT_PAGE 0x8000
135 #define LAN9303_ANLPAR_ACK 0x4000
136 #define LAN9303_ANLPAR_REMOTE_FAULT 0x2000
137 #define LAN9303_ANLPAR_ASYM_PAUSE 0x0800
138 #define LAN9303_ANLPAR_SYM_PAUSE 0x0400
139 #define LAN9303_ANLPAR_100BT4 0x0200
140 #define LAN9303_ANLPAR_100BTX_FD 0x0100
141 #define LAN9303_ANLPAR_100BTX_HD 0x0080
142 #define LAN9303_ANLPAR_10BT_FD 0x0040
143 #define LAN9303_ANLPAR_10BT_HD 0x0020
144 #define LAN9303_ANLPAR_SELECTOR 0x001F
145 #define LAN9303_ANLPAR_SELECTOR_DEFAULT 0x0001
146 
147 //PHY Auto-Negotiation Expansion register
148 #define LAN9303_ANER_PAR_DETECT_FAULT 0x0010
149 #define LAN9303_ANER_LP_NEXT_PAGE_ABLE 0x0008
150 #define LAN9303_ANER_NEXT_PAGE_ABLE 0x0004
151 #define LAN9303_ANER_PAGE_RECEIVED 0x0002
152 #define LAN9303_ANER_LP_AN_ABLE 0x0001
153 
154 //PHY Mode Control/Status register
155 #define LAN9303_PMCSR_EDPWRDOWN 0x2000
156 #define LAN9303_PMCSR_ENERGYON 0x0002
157 
158 //PHY Special Modes register
159 #define LAN9303_PSMR_MODE 0x00E0
160 #define LAN9303_PSMR_MODE_10BT_HD 0x0000
161 #define LAN9303_PSMR_MODE_10BT_FD 0x0020
162 #define LAN9303_PSMR_MODE_100BTX_HD 0x0040
163 #define LAN9303_PSMR_MODE_100BTX_FD 0x0060
164 #define LAN9303_PSMR_MODE_POWER_DOWN 0x00C0
165 #define LAN9303_PSMR_MODE_AN 0x00E0
166 #define LAN9303_PSMR_PHYAD 0x001F
167 
168 //PHY Special Control/Status Indication register
169 #define LAN9303_PSCSIR_AMDIXCTRL 0x8000
170 #define LAN9303_PSCSIR_AMDIXEN 0x4000
171 #define LAN9303_PSCSIR_AMDIXSTATE 0x2000
172 #define LAN9303_PSCSIR_SQEOFF 0x0800
173 #define LAN9303_PSCSIR_VCOOFF_LP 0x0400
174 #define LAN9303_PSCSIR_XPOL 0x0010
175 
176 //PHY Interrupt Source Flags register
177 #define LAN9303_PISR_ENERGYON 0x0080
178 #define LAN9303_PISR_AN_COMPLETE 0x0040
179 #define LAN9303_PISR_REMOTE_FAULT 0x0020
180 #define LAN9303_PISR_LINK_DOWN 0x0010
181 #define LAN9303_PISR_AN_LP_ACK 0x0008
182 #define LAN9303_PISR_PAR_DETECT_FAULT 0x0004
183 #define LAN9303_PISR_AN_PAGE_RECEIVED 0x0002
184 
185 //PHY Interrupt Mask register
186 #define LAN9303_PIMR_ENERGYON 0x0080
187 #define LAN9303_PIMR_AN_COMPLETE 0x0040
188 #define LAN9303_PIMR_REMOTE_FAULT 0x0020
189 #define LAN9303_PIMR_LINK_DOWN 0x0010
190 #define LAN9303_PIMR_AN_LP_ACK 0x0008
191 #define LAN9303_PIMR_PAR_DETECT_FAULT 0x0004
192 #define LAN9303_PIMR_AN_PAGE_RECEIVED 0x0002
193 
194 //PHY Special Control/Status register
195 #define LAN9303_PSCSR_AUTODONE 0x1000
196 #define LAN9303_PSCSR_SPEED 0x001C
197 #define LAN9303_PSCSR_SPEED_10BT_HD 0x0004
198 #define LAN9303_PSCSR_SPEED_100BTX_HD 0x0008
199 #define LAN9303_PSCSR_SPEED_10BT_FD 0x0014
200 #define LAN9303_PSCSR_SPEED_100BTX_FD 0x0018
201 
202 //Byte Order Test register
203 #define LAN9303_BYTE_TEST_DEFAULT 0x87654321
204 
205 //Hardware Configuration register
206 #define LAN9303_HW_CFG_DEVICE_READY 0x08000000
207 #define LAN9303_HW_CFG_AMDIX_EN_STRAP_STATE_PORT2 0x04000000
208 #define LAN9303_HW_CFG_AMDIX_EN_STRAP_STATE_PORT1 0x02000000
209 
210 //Switch Fabric CSR Interface Command register
211 #define LAN9303_SWITCH_CSR_CMD_BUSY 0x80000000
212 #define LAN9303_SWITCH_CSR_CMD_READ 0x40000000
213 #define LAN9303_SWITCH_CSR_CMD_AUTO_INC 0x20000000
214 #define LAN9303_SWITCH_CSR_CMD_AUTO_DEC 0x10000000
215 #define LAN9303_SWITCH_CSR_CMD_BE 0x000F0000
216 #define LAN9303_SWITCH_CSR_CMD_BE_0 0x00010000
217 #define LAN9303_SWITCH_CSR_CMD_BE_1 0x00020000
218 #define LAN9303_SWITCH_CSR_CMD_BE_2 0x00040000
219 #define LAN9303_SWITCH_CSR_CMD_BE_3 0x00080000
220 #define LAN9303_SWITCH_CSR_CMD_ADDR 0x0000FFFF
221 
222 //Switch Device ID register
223 #define LAN9303_SW_DEV_ID_DEVICE_TYPE 0x00FF0000
224 #define LAN9303_SW_DEV_ID_DEVICE_TYPE_DEFAULT 0x00030000
225 #define LAN9303_SW_DEV_ID_CHIP_VERSION 0x0000FF00
226 #define LAN9303_SW_DEV_ID_CHIP_VERSION_DEFAULT 0x00000400
227 #define LAN9303_SW_DEV_ID_REVISION 0x000000FF
228 #define LAN9303_SW_DEV_ID_REVISION_DEFAULT 0x00000007
229 
230 //Switch Reset register
231 #define LAN9303_SW_RESET_SW_RESET 0x00000001
232 
233 //Switch Global Interrupt Mask register
234 #define LAN9303_SW_IMR_BM 0x00000040
235 #define LAN9303_SW_IMR_SWE 0x00000020
236 #define LAN9303_SW_IMR_MAC2 0x00000004
237 #define LAN9303_SW_IMR_MAC1 0x00000002
238 #define LAN9303_SW_IMR_MAC0 0x00000001
239 
240 //Switch Global Interrupt Pending register
241 #define LAN9303_SW_IPR_BM 0x00000040
242 #define LAN9303_SW_IPR_SWE 0x00000020
243 #define LAN9303_SW_IPR_MAC2 0x00000004
244 #define LAN9303_SW_IPR_MAC1 0x00000002
245 #define LAN9303_SW_IPR_MAC0 0x00000001
246 
247 //Port x MAC Version ID register
248 #define LAN9303_MAC_VER_ID_DEVICE_TYPE 0x00000F00
249 #define LAN9303_MAC_VER_ID_DEVICE_TYPE_DEFAULT 0x00000500
250 #define LAN9303_MAC_VER_ID_CHIP_VERSION 0x000000F0
251 #define LAN9303_MAC_VER_ID_CHIP_VERSION_DEFAULT 0x00000080
252 #define LAN9303_MAC_VER_ID_REVISION 0x0000000F
253 #define LAN9303_MAC_VER_ID_REVISION_DEFAULT 0x00000003
254 
255 //Port x MAC Receive Configuration register
256 #define LAN9303_MAC_RX_CFG_RECEIVE_OWN_TRANSMIT_EN 0x00000020
257 #define LAN9303_MAC_RX_CFG_JUMBO_2K 0x00000008
258 #define LAN9303_MAC_RX_CFG_REJECT_MAC_TYPES 0x00000002
259 #define LAN9303_MAC_RX_CFG_RX_EN 0x00000001
260 
261 //Port x MAC Transmit Configuration register
262 #define LAN9303_MAC_TX_CFG_MAC_COUNTER_TEST 0x00000080
263 #define LAN9303_MAC_TX_CFG_IFG_CONFIG 0x0000007C
264 #define LAN9303_MAC_TX_CFG_IFG_CONFIG_DEFAULT 0x00000054
265 #define LAN9303_MAC_TX_CFG_TX_PAD_EN 0x00000002
266 #define LAN9303_MAC_TX_CFG_TX_EN 0x00000001
267 
268 //Switch Engine Port State register
269 #define LAN9303_SWE_PORT_STATE_PORT2 0x00000030
270 #define LAN9303_SWE_PORT_STATE_PORT2_FORWARDING 0x00000000
271 #define LAN9303_SWE_PORT_STATE_PORT2_LISTENING 0x00000010
272 #define LAN9303_SWE_PORT_STATE_PORT2_LEARNING 0x00000020
273 #define LAN9303_SWE_PORT_STATE_PORT2_DISABLED 0x00000030
274 #define LAN9303_SWE_PORT_STATE_PORT1 0x0000000C
275 #define LAN9303_SWE_PORT_STATE_PORT1_FORWARDING 0x00000000
276 #define LAN9303_SWE_PORT_STATE_PORT1_LISTENING 0x00000004
277 #define LAN9303_SWE_PORT_STATE_PORT1_LEARNING 0x00000008
278 #define LAN9303_SWE_PORT_STATE_PORT1_DISABLED 0x0000000C
279 #define LAN9303_SWE_PORT_STATE_PORT0 0x00000003
280 #define LAN9303_SWE_PORT_STATE_PORT0_FORWARDING 0x00000000
281 #define LAN9303_SWE_PORT_STATE_PORT0_LISTENING 0x00000001
282 #define LAN9303_SWE_PORT_STATE_PORT0_LEARNING 0x00000002
283 #define LAN9303_SWE_PORT_STATE_PORT0_DISABLED 0x00000003
284 
285 //Switch Engine Port Mirroring register
286 #define LAN9303_SWE_PORT_MIRROR_RX_MIRRORING_FILT_EN 0x00000100
287 #define LAN9303_SWE_PORT_MIRROR_SNIFFER 0x000000E0
288 #define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 0x00000020
289 #define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 0x00000040
290 #define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 0x00000080
291 #define LAN9303_SWE_PORT_MIRROR_MIRRORED 0x0000001C
292 #define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 0x00000004
293 #define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 0x00000008
294 #define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 0x00000010
295 #define LAN9303_SWE_PORT_MIRROR_RX_MIRRORING_EN 0x00000002
296 #define LAN9303_SWE_PORT_MIRROR_TX_MIRRORING_EN 0x00000001
297 
298 //Switch Engine Ingress Port Type register
299 #define LAN9303_SWE_INGRSS_PORT_TYP_PORT2 0x00000030
300 #define LAN9303_SWE_INGRSS_PORT_TYP_PORT2_DIS 0x00000000
301 #define LAN9303_SWE_INGRSS_PORT_TYP_PORT2_EN 0x00000030
302 #define LAN9303_SWE_INGRSS_PORT_TYP_PORT1 0x0000000C
303 #define LAN9303_SWE_INGRSS_PORT_TYP_PORT1_DIS 0x00000000
304 #define LAN9303_SWE_INGRSS_PORT_TYP_PORT1_EN 0x0000000C
305 #define LAN9303_SWE_INGRSS_PORT_TYP_PORT0 0x00000003
306 #define LAN9303_SWE_INGRSS_PORT_TYP_PORT0_DIS 0x00000000
307 #define LAN9303_SWE_INGRSS_PORT_TYP_PORT0_EN 0x00000003
308 
309 //Buffer Manager Egress Port Type register
310 #define LAN9303_BM_EGRSS_PORT_TYPE_VID_SEL_PORT2 0x00400000
311 #define LAN9303_BM_EGRSS_PORT_TYPE_INSERT_TAG_PORT2 0x00200000
312 #define LAN9303_BM_EGRSS_PORT_TYPE_CHANGE_VID_PORT2 0x00100000
313 #define LAN9303_BM_EGRSS_PORT_TYPE_CHANGE_PRIO_PORT2 0x00080000
314 #define LAN9303_BM_EGRSS_PORT_TYPE_CHANGE_TAG_PORT2 0x00040000
315 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT2 0x00030000
316 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT2_DUMB 0x00000000
317 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT2_ACCESS 0x00010000
318 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT2_HYBRID 0x00020000
319 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT2_CPU 0x00030000
320 #define LAN9303_BM_EGRSS_PORT_TYPE_VID_SEL_PORT1 0x00004000
321 #define LAN9303_BM_EGRSS_PORT_TYPE_INSERT_TAG_PORT1 0x00002000
322 #define LAN9303_BM_EGRSS_PORT_TYPE_CHANGE_VID_PORT1 0x00001000
323 #define LAN9303_BM_EGRSS_PORT_TYPE_CHANGE_PRIO_PORT1 0x00000800
324 #define LAN9303_BM_EGRSS_PORT_TYPE_CHANGE_TAG_PORT1 0x00000400
325 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT1 0x00000300
326 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT1_DUMB 0x00000000
327 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT1_ACCESS 0x00000100
328 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT1_HYBRID 0x00000200
329 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT1_CPU 0x00000300
330 #define LAN9303_BM_EGRSS_PORT_TYPE_VID_SEL_PORT0 0x00000040
331 #define LAN9303_BM_EGRSS_PORT_TYPE_INSERT_TAG_PORT0 0x00000020
332 #define LAN9303_BM_EGRSS_PORT_TYPE_CHANGE_VID_PORT0 0x00000010
333 #define LAN9303_BM_EGRSS_PORT_TYPE_CHANGE_PRIO_PORT0 0x00000008
334 #define LAN9303_BM_EGRSS_PORT_TYPE_CHANGE_TAG_PORT0 0x00000004
335 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT0 0x00000003
336 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT0_DUMB 0x00000000
337 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT0_ACCESS 0x00000001
338 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT0_HYBRID 0x00000002
339 #define LAN9303_BM_EGRSS_PORT_TYPE_PORT0_CPU 0x00000003
340 
341 //VLAN tag encoding
342 #define LAN9303_VLAN_ID_ENCODE(port) htons(0x10 | ((port) & 0x03))
343 //VLAN tag decoding
344 #define LAN9303_VLAN_ID_DECODE(tag) (ntohs(tag) & 0x03)
345 
346 //C++ guard
347 #ifdef __cplusplus
348 extern "C" {
349 #endif
350 
351 //LAN9303 Ethernet switch driver
352 extern const PhyDriver lan9303PhyDriver;
353 
354 //LAN9303 related functions
355 error_t lan9303Init(NetInterface *interface);
356 
357 bool_t lan9303GetLinkState(NetInterface *interface, uint8_t port);
358 
359 void lan9303Tick(NetInterface *interface);
360 
361 void lan9303EnableIrq(NetInterface *interface);
362 void lan9303DisableIrq(NetInterface *interface);
363 
364 void lan9303EventHandler(NetInterface *interface);
365 
366 error_t lan9303TagFrame(NetInterface *interface, NetBuffer *buffer,
367  size_t *offset, uint8_t port, uint16_t *type);
368 
369 error_t lan9303UntagFrame(NetInterface *interface, uint8_t **frame,
370  size_t *length, uint8_t *port);
371 
372 void lan9303WritePhyReg(NetInterface *interface, uint8_t port,
373  uint8_t address, uint16_t data);
374 
375 uint16_t lan9303ReadPhyReg(NetInterface *interface, uint8_t port,
376  uint8_t address);
377 
378 void lan9303DumpPhyReg(NetInterface *interface, uint8_t port);
379 
380 void lan9303WriteSysReg(NetInterface *interface, uint16_t address,
381  uint32_t data);
382 
383 uint32_t lan9303ReadSysReg(NetInterface *interface, uint16_t address);
384 
385 void lan9303DumpSysReg(NetInterface *interface);
386 
387 void lan9303WriteSwitchReg(NetInterface *interface, uint16_t address,
388  uint32_t data);
389 
390 uint32_t lan9303ReadSwitchReg(NetInterface *interface, uint16_t address);
391 
392 //C++ guard
393 #ifdef __cplusplus
394 }
395 #endif
396 
397 #endif
bool_t lan9303GetLinkState(NetInterface *interface, uint8_t port)
Get link state.
uint8_t length
Definition: dtls_misc.h:149
void lan9303EnableIrq(NetInterface *interface)
Enable interrupts.
int bool_t
Definition: compiler_port.h:49
error_t lan9303TagFrame(NetInterface *interface, NetBuffer *buffer, size_t *offset, uint8_t port, uint16_t *type)
Add special VLAN tag to Ethernet frame.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
PHY driver.
Definition: nic.h:214
uint32_t lan9303ReadSysReg(NetInterface *interface, uint16_t address)
Read system CSR register.
void lan9303WriteSwitchReg(NetInterface *interface, uint16_t address, uint32_t data)
Write switch fabric CSR register.
void lan9303DumpPhyReg(NetInterface *interface, uint8_t port)
Dump PHY registers for debugging purpose.
void lan9303EventHandler(NetInterface *interface)
LAN9303 event handler.
error_t lan9303Init(NetInterface *interface)
LAN9303 Ethernet switch initialization.
char_t type
error_t
Error codes.
Definition: error.h:42
#define NetInterface
Definition: net.h:36
error_t lan9303UntagFrame(NetInterface *interface, uint8_t **frame, size_t *length, uint8_t *port)
Decode special VLAN tag from incoming Ethernet frame.
void lan9303Tick(NetInterface *interface)
LAN9303 timer handler.
uint16_t port
Definition: dns_common.h:223
void lan9303WriteSysReg(NetInterface *interface, uint16_t address, uint32_t data)
Write system CSR register.
Network interface controller abstraction layer.
Ipv6Addr address
uint32_t lan9303ReadSwitchReg(NetInterface *interface, uint16_t address)
Read switch fabric CSR register.
void lan9303DisableIrq(NetInterface *interface)
Disable interrupts.
uint8_t data[]
Definition: dtls_misc.h:176
void lan9303DumpSysReg(NetInterface *interface)
Dump system CSR registers for debugging purpose.
void lan9303WritePhyReg(NetInterface *interface, uint8_t port, uint8_t address, uint16_t data)
Write PHY register.
const PhyDriver lan9303PhyDriver
LAN9303 Ethernet switch driver.
uint16_t lan9303ReadPhyReg(NetInterface *interface, uint8_t port, uint8_t address)
Read PHY register.