m487_eth_driver.h
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1 /**
2  * @file m487_eth_driver.h
3  * @brief Nuvoton M487 Ethernet MAC controller
4  *
5  * @section License
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
10  *
11  * This file is part of CycloneTCP Open.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License
15  * as published by the Free Software Foundation; either version 2
16  * of the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software Foundation,
25  * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
26  *
27  * @author Oryx Embedded SARL (www.oryx-embedded.com)
28  * @version 1.9.6
29  **/
30 
31 #ifndef _M487_ETH_DRIVER_H
32 #define _M487_ETH_DRIVER_H
33 
34 //Dependencies
35 #include "core/nic.h"
36 
37 //Number of TX buffers
38 #ifndef M487_ETH_TX_BUFFER_COUNT
39  #define M487_ETH_TX_BUFFER_COUNT 2
40 #elif (M487_ETH_TX_BUFFER_COUNT < 1)
41  #error M487_ETH_TX_BUFFER_COUNT parameter is not valid
42 #endif
43 
44 //TX buffer size
45 #ifndef M487_ETH_TX_BUFFER_SIZE
46  #define M487_ETH_TX_BUFFER_SIZE 1536
47 #elif (M487_ETH_TX_BUFFER_SIZE != 1536)
48  #error M487_ETH_TX_BUFFER_SIZE parameter is not valid
49 #endif
50 
51 //Number of RX buffers
52 #ifndef M487_ETH_RX_BUFFER_COUNT
53  #define M487_ETH_RX_BUFFER_COUNT 4
54 #elif (M487_ETH_RX_BUFFER_COUNT < 1)
55  #error M487_ETH_RX_BUFFER_COUNT parameter is not valid
56 #endif
57 
58 //RX buffer size
59 #ifndef M487_ETH_RX_BUFFER_SIZE
60  #define M487_ETH_RX_BUFFER_SIZE 1536
61 #elif (M487_ETH_RX_BUFFER_SIZE != 1536)
62  #error M487_ETH_RX_BUFFER_SIZE parameter is not valid
63 #endif
64 
65 //Interrupt priority grouping
66 #ifndef M487_ETH_IRQ_PRIORITY_GROUPING
67  #define M487_ETH_IRQ_PRIORITY_GROUPING 3
68 #elif (M487_ETH_IRQ_PRIORITY_GROUPING < 0)
69  #error M487_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
70 #endif
71 
72 //Ethernet interrupt group priority
73 #ifndef M487_ETH_IRQ_GROUP_PRIORITY
74  #define M487_ETH_IRQ_GROUP_PRIORITY 12
75 #elif (M487_ETH_IRQ_GROUP_PRIORITY < 0)
76  #error M487_ETH_IRQ_GROUP_PRIORITY parameter is not valid
77 #endif
78 
79 //Ethernet interrupt subpriority
80 #ifndef M487_ETH_IRQ_SUB_PRIORITY
81  #define M487_ETH_IRQ_SUB_PRIORITY 0
82 #elif (M487_ETH_IRQ_SUB_PRIORITY < 0)
83  #error M487_ETH_IRQ_SUB_PRIORITY parameter is not valid
84 #endif
85 
86 //Transmit DMA descriptor flags
87 #define EMAC_TXDES0_OWNER 0x80000000
88 #define EMAC_TXDES0_TTSEN 0x00000008
89 #define EMAC_TXDES0_INTEN 0x00000004
90 #define EMAC_TXDES0_CRCAPP 0x00000002
91 #define EMAC_TXDES0_PADEN 0x00000001
92 #define EMAC_TXDES1_TXBSA 0xFFFFFFFF
93 #define EMAC_TXDES2_COLCNT 0xF0000000
94 #define EMAC_TXDES2_TTSAS 0x08000000
95 #define EMAC_TXDES2_SQE 0x04000000
96 #define EMAC_TXDES2_TXPAUSED 0x02000000
97 #define EMAC_TXDES2_TXHALT 0x01000000
98 #define EMAC_TXDES2_LCIF 0x00800000
99 #define EMAC_TXDES2_TXABTIF 0x00400000
100 #define EMAC_TXDES2_NCSIF 0x00200000
101 #define EMAC_TXDES2_EXDEFIF 0x00100000
102 #define EMAC_TXDES2_TXCPIF 0x00080000
103 #define EMAC_TXDES2_DEF 0x00020000
104 #define EMAC_TXDES2_TXIF 0x00010000
105 #define EMAC_TXDES2_TBC 0x0000FFFF
106 #define EMAC_TXDES2_NTXDSA 0xFFFFFFFF
107 
108 //Receive DMA descriptor flags
109 #define EMAC_RXDES0_OWNER 0x80000000
110 #define EMAC_RXDES0_RTSAS 0x00800000
111 #define EMAC_RXDES0_RPIF 0x00400000
112 #define EMAC_RXDES0_ALIEIF 0x00200000
113 #define EMAC_RXDES0_RXGDIF 0x00100000
114 #define EMAC_RXDES0_LPIF 0x00080000
115 #define EMAC_RXDES0_CRCEIF 0x00020000
116 #define EMAC_RXDES0_RXIF 0x00010000
117 #define EMAC_RXDES0_RBC 0x0000FFFF
118 #define EMAC_RXDES1_RXBSA 0xFFFFFFFF
119 #define EMAC_RXDES3_NRXDSA 0xFFFFFFFF
120 
121 //C++ guard
122 #ifdef __cplusplus
123 extern "C" {
124 #endif
125 
126 
127 /**
128  * @brief TX DMA descriptor
129  **/
130 
131 typedef struct
132 {
133  uint32_t txdes0;
134  uint32_t txdes1;
135  uint32_t txdes2;
136  uint32_t txdes3;
138 
139 
140 /**
141  * @brief RX DMA descriptor
142  **/
143 
144 typedef struct
145 {
146  uint32_t rxdes0;
147  uint32_t rxdes1;
148  uint32_t rxdes2;
149  uint32_t rxdes3;
151 
152 
153 //M487 Ethernet MAC driver
154 extern const NicDriver m487EthDriver;
155 
156 //M487 Ethernet MAC related functions
157 error_t m487EthInit(NetInterface *interface);
158 void m487EthInitGpio(NetInterface *interface);
159 void m487EthInitDmaDesc(NetInterface *interface);
160 
161 void m487EthTick(NetInterface *interface);
162 
163 void m487EthEnableIrq(NetInterface *interface);
164 void m487EthDisableIrq(NetInterface *interface);
165 void m487EthEventHandler(NetInterface *interface);
166 
168  const NetBuffer *buffer, size_t offset);
169 
171 
174 
175 void m487EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
176  uint8_t regAddr, uint16_t data);
177 
178 uint16_t m487EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
179  uint8_t regAddr);
180 
181 //C++ guard
182 #ifdef __cplusplus
183 }
184 #endif
185 
186 #endif
void m487EthTick(NetInterface *interface)
M487 Ethernet MAC timer handler.
TX DMA descriptor.
uint8_t opcode
Definition: dns_common.h:172
void m487EthEventHandler(NetInterface *interface)
M487 Ethernet MAC event handler.
Structure describing a buffer that spans multiple chunks.
Definition: net_mem.h:88
uint16_t m487EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr)
Read PHY register.
void m487EthInitDmaDesc(NetInterface *interface)
Initialize DMA descriptor lists.
RX DMA descriptor.
error_t
Error codes.
Definition: error.h:42
error_t m487EthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset)
Send a packet.
error_t m487EthInit(NetInterface *interface)
M487 Ethernet MAC initialization.
#define NetInterface
Definition: net.h:36
error_t m487EthUpdateMacAddrFilter(NetInterface *interface)
Configure MAC address filtering.
const NicDriver m487EthDriver
M487 Ethernet MAC driver.
void m487EthInitGpio(NetInterface *interface)
void m487EthDisableIrq(NetInterface *interface)
Disable interrupts.
uint16_t regAddr
Network interface controller abstraction layer.
error_t m487EthUpdateMacConfig(NetInterface *interface)
Adjust MAC configuration parameters for proper operation.
void m487EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Write PHY register.
error_t m487EthReceivePacket(NetInterface *interface)
Receive a packet.
uint8_t data[]
Definition: dtls_misc.h:176
NIC driver.
Definition: nic.h:179
void m487EthEnableIrq(NetInterface *interface)
Enable interrupts.